CA2468615C - Procede de fabrication de transistors non lithographiques a autoalignement avec des longueurs de canal ultracourtes - Google Patents
Procede de fabrication de transistors non lithographiques a autoalignement avec des longueurs de canal ultracourtes Download PDFInfo
- Publication number
- CA2468615C CA2468615C CA002468615A CA2468615A CA2468615C CA 2468615 C CA2468615 C CA 2468615C CA 002468615 A CA002468615 A CA 002468615A CA 2468615 A CA2468615 A CA 2468615A CA 2468615 C CA2468615 C CA 2468615C
- Authority
- CA
- Canada
- Prior art keywords
- electrodes
- substrate
- conducting material
- transistors
- depositing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 230000005669 field effect Effects 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims description 38
- 239000004020 conductor Substances 0.000 claims description 22
- 238000000059 patterning Methods 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 9
- 239000011159 matrix material Substances 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000001419 dependent effect Effects 0.000 claims description 4
- 238000005507 spraying Methods 0.000 claims description 3
- 229920001577 copolymer Polymers 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 239000011368 organic material Substances 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 29
- 238000001459 lithography Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000002411 adverse Effects 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 241000272470 Circus Species 0.000 description 1
- 238000001015 X-ray lithography Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000003278 mimic effect Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 230000000135 prohibitive effect Effects 0.000 description 1
- 238000001338 self-assembly Methods 0.000 description 1
- 238000002174 soft lithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Abstract
La présente invention concerne un procédé de fabrication de transistors à longueur de canal ultracourte dans lequel le dépôt des électrodes de source, de drain et de grille peut s'effectuer lors d'une première étape selon une technologie de l'état antérieur de la technique limitant les dimensions de l'électrode en fonction des règles de dessin applicables, tandis que les dimensions d'une de ces électrodes sur deux peuvent être ajustées selon les besoins lors des étapes de traitement subséquentes. Selon le procédé précité, on forme une zone de canal entre une électrode de source et une électrode de drain sans être limité par une quelconque règle de dessin, ce qui permet de former des canaux de transistor possédant des longueurs de canal L extrêmement courtes, bien inférieures à 10 nm, par exemple. On peut ajuster la largeur des électrodes de grille proportionnellement afin d'obtenir une grande largeur de canal W et obtenir de la sorte des transistors possédant des rapports de forme longueur/diamètre presque arbitrairement élevés et, partant, des caractéristiques de commutation et de courant désirées. Le procédé de l'invention peut être utilisé pour fabriquer n'importe quel type de transistor à effet de champ, même sur le même substrat et il peut également être adapté à la fabrication d'autres types de structures de transistors.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NO20015837 | 2001-11-29 | ||
NO20015837A NO20015837A (no) | 2001-11-29 | 2001-11-29 | Fremgangsmåte til fremstilling av selvregistrerende ikke-litografiske transistorer med ultrakorte kanallengder |
PCT/NO2002/000397 WO2003046921A1 (fr) | 2001-11-29 | 2002-11-01 | Procede de fabrication de transistors non lithographiques a autoalignement avec des longueurs de canal ultracourtes |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2468615A1 CA2468615A1 (fr) | 2003-06-05 |
CA2468615C true CA2468615C (fr) | 2007-03-20 |
Family
ID=19913080
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002468615A Expired - Fee Related CA2468615C (fr) | 2001-11-29 | 2002-11-01 | Procede de fabrication de transistors non lithographiques a autoalignement avec des longueurs de canal ultracourtes |
Country Status (9)
Country | Link |
---|---|
EP (1) | EP1449217A1 (fr) |
JP (1) | JP2005510864A (fr) |
KR (1) | KR100543076B1 (fr) |
CN (1) | CN1599936A (fr) |
AU (1) | AU2002365533A1 (fr) |
CA (1) | CA2468615C (fr) |
NO (1) | NO20015837A (fr) |
RU (1) | RU2261499C2 (fr) |
WO (1) | WO2003046921A1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6724028B2 (en) | 2001-12-10 | 2004-04-20 | Hans Gude Gudesen | Matrix-addressable array of integrated transistor/memory structures |
US6649504B2 (en) | 2001-12-14 | 2003-11-18 | Thin Film Electronics Asa | Method for fabricating high aspect ratio electrodes |
US9035281B2 (en) | 2009-06-30 | 2015-05-19 | Nokia Technologies Oy | Graphene device and method of fabricating a graphene device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4952031A (en) * | 1987-06-19 | 1990-08-28 | Victor Company Of Japan, Ltd. | Liquid crystal display device |
JPH07106450A (ja) * | 1993-10-08 | 1995-04-21 | Olympus Optical Co Ltd | 強誘電体ゲートトランジスタメモリ |
DE69739045D1 (de) * | 1997-08-27 | 2008-11-27 | St Microelectronics Srl | Herstellungsverfahren für elektronische Speicherbauelemente mit virtueller Masse |
US6072716A (en) * | 1999-04-14 | 2000-06-06 | Massachusetts Institute Of Technology | Memory structures and methods of making same |
US6473388B1 (en) * | 2000-08-31 | 2002-10-29 | Hewlett Packard Company | Ultra-high density information storage device based on modulated cathodoconductivity |
-
2001
- 2001-11-29 NO NO20015837A patent/NO20015837A/no unknown
-
2002
- 2002-11-01 WO PCT/NO2002/000397 patent/WO2003046921A1/fr not_active Application Discontinuation
- 2002-11-01 CN CNA028239601A patent/CN1599936A/zh active Pending
- 2002-11-01 EP EP02803936A patent/EP1449217A1/fr not_active Withdrawn
- 2002-11-01 KR KR1020047008231A patent/KR100543076B1/ko not_active IP Right Cessation
- 2002-11-01 CA CA002468615A patent/CA2468615C/fr not_active Expired - Fee Related
- 2002-11-01 AU AU2002365533A patent/AU2002365533A1/en not_active Abandoned
- 2002-11-01 JP JP2003548252A patent/JP2005510864A/ja not_active Abandoned
- 2002-11-01 RU RU2004118416/28A patent/RU2261499C2/ru not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CA2468615A1 (fr) | 2003-06-05 |
WO2003046921A1 (fr) | 2003-06-05 |
CN1599936A (zh) | 2005-03-23 |
RU2004118416A (ru) | 2005-04-10 |
NO314738B1 (no) | 2003-05-12 |
NO20015837D0 (no) | 2001-11-29 |
KR20040064290A (ko) | 2004-07-16 |
EP1449217A1 (fr) | 2004-08-25 |
RU2261499C2 (ru) | 2005-09-27 |
AU2002365533A1 (en) | 2003-06-10 |
KR100543076B1 (ko) | 2006-01-20 |
JP2005510864A (ja) | 2005-04-21 |
NO20015837A (no) | 2003-05-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed | ||
MKLA | Lapsed |
Effective date: 20081103 |
|
MKLA | Lapsed |
Effective date: 20081103 |