CA2468615A1 - Procede de fabrication de transistors non lithographiques a autoalignement avec des longueurs de canal ultracourtes - Google Patents

Procede de fabrication de transistors non lithographiques a autoalignement avec des longueurs de canal ultracourtes Download PDF

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Publication number
CA2468615A1
CA2468615A1 CA002468615A CA2468615A CA2468615A1 CA 2468615 A1 CA2468615 A1 CA 2468615A1 CA 002468615 A CA002468615 A CA 002468615A CA 2468615 A CA2468615 A CA 2468615A CA 2468615 A1 CA2468615 A1 CA 2468615A1
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CA
Canada
Prior art keywords
transistors
adjusted
channel lengths
lithographic
channel
Prior art date
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Granted
Application number
CA002468615A
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English (en)
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CA2468615C (fr
Inventor
Hans Gude Gudesen
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Ensurge Micropower ASA
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Individual
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Publication of CA2468615A1 publication Critical patent/CA2468615A1/fr
Application granted granted Critical
Publication of CA2468615C publication Critical patent/CA2468615C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un procédé de fabrication de transistors à longueur de canal ultracourte dans lequel le dépôt des électrodes de source, de drain et de grille peut s'effectuer lors d'une première étape selon une technologie de l'état antérieur de la technique limitant les dimensions de l'électrode en fonction des règles de dessin applicables, tandis que les dimensions d'une de ces électrodes sur deux peuvent être ajustées selon les besoins lors des étapes de traitement subséquentes. Selon le procédé précité, on forme une zone de canal entre une électrode de source et une électrode de drain sans être limité par une quelconque règle de dessin, ce qui permet de former des canaux de transistor possédant des longueurs de canal L extrêmement courtes, bien inférieures à 10 nm, par exemple. On peut ajuster la largeur des électrodes de grille proportionnellement afin d'obtenir une grande largeur de canal W et obtenir de la sorte des transistors possédant des rapports de forme longueur/diamètre presque arbitrairement élevés et, partant, des caractéristiques de commutation et de courant désirées. Le procédé de l'invention peut être utilisé pour fabriquer n'importe quel type de transistor à effet de champ, même sur le même substrat et il peut également être adapté à la fabrication d'autres types de structures de transistors.
CA002468615A 2001-11-29 2002-11-01 Procede de fabrication de transistors non lithographiques a autoalignement avec des longueurs de canal ultracourtes Expired - Fee Related CA2468615C (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
NO20015837 2001-11-29
NO20015837A NO314738B1 (no) 2001-11-29 2001-11-29 Fremgangsmåte til fremstilling av selvregistrerende ikke- litografiske transistorer med ultrakorte kanallengder
PCT/NO2002/000397 WO2003046921A1 (fr) 2001-11-29 2002-11-01 Procede de fabrication de transistors non lithographiques a autoalignement avec des longueurs de canal ultracourtes

Publications (2)

Publication Number Publication Date
CA2468615A1 true CA2468615A1 (fr) 2003-06-05
CA2468615C CA2468615C (fr) 2007-03-20

Family

ID=19913080

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002468615A Expired - Fee Related CA2468615C (fr) 2001-11-29 2002-11-01 Procede de fabrication de transistors non lithographiques a autoalignement avec des longueurs de canal ultracourtes

Country Status (9)

Country Link
EP (1) EP1449217A1 (fr)
JP (1) JP2005510864A (fr)
KR (1) KR100543076B1 (fr)
CN (1) CN1599936A (fr)
AU (1) AU2002365533A1 (fr)
CA (1) CA2468615C (fr)
NO (1) NO314738B1 (fr)
RU (1) RU2261499C2 (fr)
WO (1) WO2003046921A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724028B2 (en) 2001-12-10 2004-04-20 Hans Gude Gudesen Matrix-addressable array of integrated transistor/memory structures
US6649504B2 (en) 2001-12-14 2003-11-18 Thin Film Electronics Asa Method for fabricating high aspect ratio electrodes
US9035281B2 (en) 2009-06-30 2015-05-19 Nokia Technologies Oy Graphene device and method of fabricating a graphene device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4952031A (en) * 1987-06-19 1990-08-28 Victor Company Of Japan, Ltd. Liquid crystal display device
JPH07106450A (ja) * 1993-10-08 1995-04-21 Olympus Optical Co Ltd 強誘電体ゲートトランジスタメモリ
DE69739045D1 (de) * 1997-08-27 2008-11-27 St Microelectronics Srl Herstellungsverfahren für elektronische Speicherbauelemente mit virtueller Masse
US6072716A (en) * 1999-04-14 2000-06-06 Massachusetts Institute Of Technology Memory structures and methods of making same
US6473388B1 (en) * 2000-08-31 2002-10-29 Hewlett Packard Company Ultra-high density information storage device based on modulated cathodoconductivity

Also Published As

Publication number Publication date
AU2002365533A1 (en) 2003-06-10
NO20015837A (no) 2003-05-12
CN1599936A (zh) 2005-03-23
JP2005510864A (ja) 2005-04-21
NO20015837D0 (no) 2001-11-29
RU2004118416A (ru) 2005-04-10
KR100543076B1 (ko) 2006-01-20
RU2261499C2 (ru) 2005-09-27
WO2003046921A1 (fr) 2003-06-05
CA2468615C (fr) 2007-03-20
KR20040064290A (ko) 2004-07-16
EP1449217A1 (fr) 2004-08-25
NO314738B1 (no) 2003-05-12

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