DE69739045D1 - Herstellungsverfahren für elektronische Speicherbauelemente mit virtueller Masse - Google Patents

Herstellungsverfahren für elektronische Speicherbauelemente mit virtueller Masse

Info

Publication number
DE69739045D1
DE69739045D1 DE69739045T DE69739045T DE69739045D1 DE 69739045 D1 DE69739045 D1 DE 69739045D1 DE 69739045 T DE69739045 T DE 69739045T DE 69739045 T DE69739045 T DE 69739045T DE 69739045 D1 DE69739045 D1 DE 69739045D1
Authority
DE
Germany
Prior art keywords
manufacturing
memory devices
electronic memory
virtual ground
virtual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69739045T
Other languages
English (en)
Inventor
Claudio Brambilla
Valerio Cassio
Paolo Caprara
Manlio Sergio Cereda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69739045D1 publication Critical patent/DE69739045D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE69739045T 1997-08-27 1997-08-27 Herstellungsverfahren für elektronische Speicherbauelemente mit virtueller Masse Expired - Lifetime DE69739045D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP97830427A EP0902465B1 (de) 1997-08-27 1997-08-27 Herstellungsverfahren für elektronische Speicherbauelemente mit virtueller Masse

Publications (1)

Publication Number Publication Date
DE69739045D1 true DE69739045D1 (de) 2008-11-27

Family

ID=8230759

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69739045T Expired - Lifetime DE69739045D1 (de) 1997-08-27 1997-08-27 Herstellungsverfahren für elektronische Speicherbauelemente mit virtueller Masse

Country Status (3)

Country Link
US (1) US6326266B1 (de)
EP (1) EP0902465B1 (de)
DE (1) DE69739045D1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3602010B2 (ja) * 1999-08-02 2004-12-15 シャープ株式会社 半導体記憶装置の製造方法
JP2001351993A (ja) * 2000-06-05 2001-12-21 Nec Corp 半導体記憶装置及びその製造方法
US6387814B1 (en) * 2001-08-07 2002-05-14 Macronix International Co. Ltd. Method of fabricating a stringerless flash memory
US6833593B2 (en) 2001-11-09 2004-12-21 Thin Film Electronics Asa Electrode means, a method for its manufacture, an apparatus comprising the electrode means as well as use of the latter
NO20015509D0 (no) * 2001-11-09 2001-11-09 Hans Gude Gudesen Elektrodeanordning, fremgangsmåte til dets fremstilling, apparat omfattende elektrodeanordningene, samt bruk av sistnevnte
NO20015815A (no) * 2001-11-28 2003-03-10 Hans Gude Gudesen Matriseadresserbart apparat med en eller flere minneinnretninger
NO314738B1 (no) * 2001-11-29 2003-05-12 Hans Gude Gudesen Fremgangsmåte til fremstilling av selvregistrerende ikke- litografiske transistorer med ultrakorte kanallengder
NO20016041A (no) * 2001-12-10 2003-05-12 Hans Gude Gudesen Matriseadresserbar gruppe av integrerte transistor/minnestrukturer
JP4278940B2 (ja) * 2002-09-09 2009-06-17 株式会社 液晶先端技術開発センター 結晶化装置および結晶化方法
US7005335B2 (en) 2003-07-15 2006-02-28 Hewlett-Packard Development, L.P. Array of nanoscopic mosfet transistors and fabrication methods
KR100583609B1 (ko) * 2004-07-05 2006-05-26 삼성전자주식회사 반도체 장치의 게이트 구조물 제조방법 및 이를 이용한불휘발성 메모리 장치의 셀 게이트 구조물 제조방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1213249B (it) * 1984-11-26 1989-12-14 Ates Componenti Elettron Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori.
US4833514A (en) * 1985-05-01 1989-05-23 Texas Instruments Incorporated Planar FAMOS transistor with sealed floating gate and DCS+N2 O oxide
IT1235690B (it) * 1989-04-07 1992-09-21 Sgs Thomson Microelectronics Procedimento di fabbricazione per una matrice di celle eprom organizzate a tovaglia.
KR960012303B1 (ko) * 1992-08-18 1996-09-18 삼성전자 주식회사 불휘발성 반도체메모리장치 및 그 제조방법
US5313419A (en) * 1993-02-01 1994-05-17 National Semiconductor Corporation Self-aligned trench isolation scheme for select transistors in an alternate metal virtual ground (AMG) EPROM array
US5717635A (en) * 1996-08-27 1998-02-10 International Business Machines Corporation High density EEPROM for solid state file

Also Published As

Publication number Publication date
EP0902465A1 (de) 1999-03-17
US6326266B1 (en) 2001-12-04
EP0902465B1 (de) 2008-10-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition