BR9814844A - "sistema e processo para prover arbitragem especulativa para transferência de dados" - Google Patents

"sistema e processo para prover arbitragem especulativa para transferência de dados"

Info

Publication number
BR9814844A
BR9814844A BR9814844-3A BR9814844A BR9814844A BR 9814844 A BR9814844 A BR 9814844A BR 9814844 A BR9814844 A BR 9814844A BR 9814844 A BR9814844 A BR 9814844A
Authority
BR
Brazil
Prior art keywords
data
bus
modules
main memory
early warning
Prior art date
Application number
BR9814844-3A
Other languages
English (en)
Inventor
Mitchell A Bauman
Joseph S Schibinger
Donald R Kalvestrand
Douglas E Morrissey
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Publication of BR9814844A publication Critical patent/BR9814844A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)

Abstract

"SISTEMA E PROCESSO PARA PROVER ARBITRAGEM ESPECULATIVA PARA TRANSFERêNCIA DE DADOS" Trata-se de um sistema e um processo para otimizar a quantidade de tempo que um dispositivo solicitante ( 540, 320) leva para receber dados (230) de uma unidade de armazenamento de memória (110) em um ambiente de transmissor com vários solicitantes. A presente invenção fornece um sinal de resposta unidirecional (740) denominado de sinal de aviso antecipado (740), enviado de uma unidade de armazenamento de memória (110) a um dispositivo (540, 320), algum tempo depois que o dispositivo (540, 320) tenha executado uma solicitação de busca de dados (230), para alertar o dispositivo (540, 320) de que os dados (230) estão chegando. Esse sinal de aviso antecipado (740) permite ao dispositivo (540, 320) arbitre pelo transmissor de dados (520, 340), de modo que quando os dados (230) chegam, o dispositivo (540, 320) terá propriedade exclusiva do transmissor de dados (520, 340) para aceitar os dados (230) imediatamente. A presente invenção compreende uma memória principal (110), uma memória cache (510), um ou mais módulos de processador (120), um ou mais módulos I/O (320), e um transmissor de aviso antecipado (710). A memória cache (510) é ligada à memória principal (110) por meio de transmissor de interface (130). Os módulos de processador (120) são ligados à memória cache (510) por meio de um transmissor de interface de processador (520). Os módulos I/O (320) são ligados à memória principal (110) por meio de um transmissor de interface I/O (340). Tantos os módulos de processador (120) quanto os módulos I/O incluem dispositivos para solicitar uma unidade de dados da memória principal. O transmissor de aviso antecipado (710) é ligado entre a memória principal (110) , a memória cache (510) e o módulo I/O (320).
BR9814844-3A 1997-11-05 1998-11-04 "sistema e processo para prover arbitragem especulativa para transferência de dados" BR9814844A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/964,630 US6049845A (en) 1997-11-05 1997-11-05 System and method for providing speculative arbitration for transferring data
PCT/US1998/023459 WO1999023570A1 (en) 1997-11-05 1998-11-04 System and method for providing speculative arbitration for transferring data

Publications (1)

Publication Number Publication Date
BR9814844A true BR9814844A (pt) 2000-10-03

Family

ID=25508789

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9814844-3A BR9814844A (pt) 1997-11-05 1998-11-04 "sistema e processo para prover arbitragem especulativa para transferência de dados"

Country Status (9)

Country Link
US (1) US6049845A (pt)
EP (1) EP1029283B1 (pt)
JP (1) JP3635634B2 (pt)
KR (1) KR100381619B1 (pt)
AT (1) ATE235713T1 (pt)
AU (1) AU1305199A (pt)
BR (1) BR9814844A (pt)
DE (1) DE69812685T2 (pt)
WO (1) WO1999023570A1 (pt)

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Also Published As

Publication number Publication date
ATE235713T1 (de) 2003-04-15
JP3635634B2 (ja) 2005-04-06
WO1999023570A1 (en) 1999-05-14
KR100381619B1 (ko) 2003-04-26
EP1029283B1 (en) 2003-03-26
US6049845A (en) 2000-04-11
KR20010031690A (ko) 2001-04-16
JP2001522092A (ja) 2001-11-13
AU1305199A (en) 1999-05-24
DE69812685T2 (de) 2003-11-06
DE69812685D1 (de) 2003-04-30
EP1029283A1 (en) 2000-08-23

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B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements