DE69906585D1 - Datenverarbeitungssystem mit nichtuniformen speicherzugriffen (numa) mit spekulativer weiterleitung einer leseanforderung an einen entfernten verarbeitungsknoten - Google Patents

Datenverarbeitungssystem mit nichtuniformen speicherzugriffen (numa) mit spekulativer weiterleitung einer leseanforderung an einen entfernten verarbeitungsknoten

Info

Publication number
DE69906585D1
DE69906585D1 DE69906585T DE69906585T DE69906585D1 DE 69906585 D1 DE69906585 D1 DE 69906585D1 DE 69906585 T DE69906585 T DE 69906585T DE 69906585 T DE69906585 T DE 69906585T DE 69906585 D1 DE69906585 D1 DE 69906585D1
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DE
Germany
Prior art keywords
node
processing node
local
interconnect
response
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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DE69906585T
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English (en)
Other versions
DE69906585T2 (de
Inventor
Yoanna Baumgartner
Edward Dean
Anna Elman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
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Publication date
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Application granted granted Critical
Publication of DE69906585D1 publication Critical patent/DE69906585D1/de
Publication of DE69906585T2 publication Critical patent/DE69906585T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/507—Control mechanisms for virtual memory, cache or TLB using speculative control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
DE69906585T 1998-12-15 1999-12-10 Datenverarbeitungssystem mit nichtuniformen speicherzugriffen (numa) mit spekulativer weiterleitung einer leseanforderung an einen entfernten verarbeitungsknoten Expired - Lifetime DE69906585T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/211,351 US6338122B1 (en) 1998-12-15 1998-12-15 Non-uniform memory access (NUMA) data processing system that speculatively forwards a read request to a remote processing node
US211351 1998-12-15
PCT/GB1999/004204 WO2000036514A1 (en) 1998-12-15 1999-12-10 Non-uniform memory access (numa) data processing system that speculatively forwards a read request to a remote processing node

Publications (2)

Publication Number Publication Date
DE69906585D1 true DE69906585D1 (de) 2003-05-08
DE69906585T2 DE69906585T2 (de) 2004-02-12

Family

ID=22786571

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69906585T Expired - Lifetime DE69906585T2 (de) 1998-12-15 1999-12-10 Datenverarbeitungssystem mit nichtuniformen speicherzugriffen (numa) mit spekulativer weiterleitung einer leseanforderung an einen entfernten verarbeitungsknoten

Country Status (16)

Country Link
US (1) US6338122B1 (de)
EP (1) EP1153349B1 (de)
KR (1) KR100465583B1 (de)
CN (1) CN1157659C (de)
AT (1) ATE236431T1 (de)
AU (1) AU1672500A (de)
CA (1) CA2349569C (de)
CZ (1) CZ20012153A3 (de)
DE (1) DE69906585T2 (de)
ES (1) ES2196893T3 (de)
HU (1) HUP0104577A3 (de)
IL (2) IL142265A0 (de)
PL (1) PL348859A1 (de)
RU (1) RU2220444C2 (de)
TW (1) TW446883B (de)
WO (1) WO2000036514A1 (de)

Families Citing this family (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69806812T2 (de) * 1997-12-19 2003-03-13 Unilever N.V., Rotterdam Olivenöl enthaltende nahrungsmittelzusammensetzung
US6546429B1 (en) * 1998-09-21 2003-04-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that holds and reissues requests at a target processing node in response to a retry
US6591307B1 (en) * 1999-11-09 2003-07-08 International Business Machines Corporation Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response
JP2001167077A (ja) * 1999-12-09 2001-06-22 Nec Kofu Ltd ネットワークシステムにおけるデータアクセス方法、ネットワークシステムおよび記録媒体
US6938128B1 (en) 2000-07-20 2005-08-30 Silicon Graphics, Inc. System and method for reducing memory latency during read requests
US6678798B1 (en) * 2000-07-20 2004-01-13 Silicon Graphics, Inc. System and method for reducing memory latency during read requests
US6915387B1 (en) 2000-07-20 2005-07-05 Silicon Graphics, Inc. System and method for handling updates to memory in a distributed shared memory system
US8635410B1 (en) 2000-07-20 2014-01-21 Silicon Graphics International, Corp. System and method for removing data from processor caches in a distributed multi-processor computer system
US6810467B1 (en) * 2000-08-21 2004-10-26 Intel Corporation Method and apparatus for centralized snoop filtering
US20020078118A1 (en) * 2000-12-19 2002-06-20 Cone Robert W. Network interface application specific integrated circuit to allow direct attachment for an appliance,such as a printer device
US7234029B2 (en) * 2000-12-28 2007-06-19 Intel Corporation Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
US6799217B2 (en) * 2001-06-04 2004-09-28 Fujitsu Limited Shared memory multiprocessor expansion port for multi-node systems
US6748479B2 (en) 2001-11-20 2004-06-08 Broadcom Corporation System having interfaces and switch that separates coherent and packet traffic
US7394823B2 (en) * 2001-11-20 2008-07-01 Broadcom Corporation System having configurable interfaces for flexible system configurations
US7206879B2 (en) * 2001-11-20 2007-04-17 Broadcom Corporation Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems
EP1316891B1 (de) * 2001-12-03 2007-10-10 Infineon Technologies AG Datenübertragungseinrichtung
US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
US6959372B1 (en) * 2002-02-19 2005-10-25 Cogent Chipware Inc. Processor cluster architecture and associated parallel processing methods
US7107408B2 (en) * 2002-03-22 2006-09-12 Newisys, Inc. Methods and apparatus for speculative probing with early completion and early request
US7107409B2 (en) * 2002-03-22 2006-09-12 Newisys, Inc. Methods and apparatus for speculative probing at a request cluster
US7103725B2 (en) * 2002-03-22 2006-09-05 Newisys, Inc. Methods and apparatus for speculative probing with early completion and delayed request
US7395379B2 (en) * 2002-05-13 2008-07-01 Newisys, Inc. Methods and apparatus for responding to a request cluster
US7653790B2 (en) * 2002-05-13 2010-01-26 Glasco David B Methods and apparatus for responding to a request cluster
US7266587B2 (en) * 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
US7003631B2 (en) * 2002-05-15 2006-02-21 Broadcom Corporation System having address-based intranode coherency and data-based internode coherency
US6965973B2 (en) * 2002-05-15 2005-11-15 Broadcom Corporation Remote line directory which covers subset of shareable CC-NUMA memory space
US6993631B2 (en) * 2002-05-15 2006-01-31 Broadcom Corporation L2 cache maintaining local ownership of remote coherency blocks
US7155525B2 (en) * 2002-05-28 2006-12-26 Newisys, Inc. Transaction management in systems having multiple multi-processor clusters
US7281055B2 (en) * 2002-05-28 2007-10-09 Newisys, Inc. Routing mechanisms in systems having multiple multi-processor clusters
US7251698B2 (en) * 2002-05-28 2007-07-31 Newisys, Inc. Address space management in systems having multiple multi-processor clusters
US7103636B2 (en) * 2002-05-28 2006-09-05 Newisys, Inc. Methods and apparatus for speculative probing of a remote cluster
US6865595B2 (en) * 2002-05-28 2005-03-08 Newisys, Inc. Methods and apparatus for speculative probing of a remote cluster
US6959364B2 (en) * 2002-06-28 2005-10-25 Intel Corporation Partially inclusive snoop filter
US7003633B2 (en) * 2002-11-04 2006-02-21 Newisys, Inc. Methods and apparatus for managing probe requests
US7346744B1 (en) 2002-11-04 2008-03-18 Newisys, Inc. Methods and apparatus for maintaining remote cluster state information
US7296121B2 (en) * 2002-11-04 2007-11-13 Newisys, Inc. Reducing probe traffic in multiprocessor systems
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7577755B2 (en) * 2002-11-19 2009-08-18 Newisys, Inc. Methods and apparatus for distributing system management signals
EP1426866A1 (de) * 2002-12-06 2004-06-09 Sun Microsystems, Inc. Verfahren zur Verminderung der Speicherlatenzzeit mittels zweistufiger Spekulation
US7111128B2 (en) 2002-12-19 2006-09-19 Intel Corporation Hierarchical virtual model of a cache hierarchy in a multiprocessor system
US7917646B2 (en) * 2002-12-19 2011-03-29 Intel Corporation Speculative distributed conflict resolution for a cache coherency protocol
US7334089B2 (en) * 2003-05-20 2008-02-19 Newisys, Inc. Methods and apparatus for providing cache state information
US7386626B2 (en) * 2003-06-23 2008-06-10 Newisys, Inc. Bandwidth, framing and error detection in communications between multi-processor clusters of multi-cluster computer systems
US7577727B2 (en) * 2003-06-27 2009-08-18 Newisys, Inc. Dynamic multiple cluster system reconfiguration
US7337279B2 (en) * 2003-06-27 2008-02-26 Newisys, Inc. Methods and apparatus for sending targeted probes
US7159137B2 (en) * 2003-08-05 2007-01-02 Newisys, Inc. Synchronized communication between multi-processor clusters of multi-cluster computer systems
US7395347B2 (en) * 2003-08-05 2008-07-01 Newisys, Inc, Communication between and within multi-processor clusters of multi-cluster computer systems
US7117419B2 (en) * 2003-08-05 2006-10-03 Newisys, Inc. Reliable communication between multi-processor clusters of multi-cluster computer systems
US7103823B2 (en) 2003-08-05 2006-09-05 Newisys, Inc. Communication between multi-processor clusters of multi-cluster computer systems
US20050240734A1 (en) * 2004-04-27 2005-10-27 Batson Brannon J Cache coherence protocol
US20050262250A1 (en) * 2004-04-27 2005-11-24 Batson Brannon J Messaging protocol
US7822929B2 (en) * 2004-04-27 2010-10-26 Intel Corporation Two-hop cache coherency protocol
US7395381B2 (en) * 2005-03-18 2008-07-01 Intel Corporation Method and an apparatus to reduce network utilization in a multiprocessor system
US8037465B2 (en) * 2005-09-30 2011-10-11 Intel Corporation Thread-data affinity optimization using compiler
US20110004732A1 (en) * 2007-06-06 2011-01-06 3Leaf Networks, Inc. DMA in Distributed Shared Memory System
US8725931B1 (en) 2010-03-26 2014-05-13 Western Digital Technologies, Inc. System and method for managing the execution of memory commands in a solid-state memory
US8782327B1 (en) 2010-05-11 2014-07-15 Western Digital Technologies, Inc. System and method for managing execution of internal commands and host commands in a solid-state memory
US9026716B2 (en) 2010-05-12 2015-05-05 Western Digital Technologies, Inc. System and method for managing garbage collection in solid-state memory
WO2012029163A1 (ja) * 2010-09-02 2012-03-08 富士通株式会社 ノードコントローラ、ノードコントローラの制御方法及びコンピュータシステム
US8635412B1 (en) 2010-09-09 2014-01-21 Western Digital Technologies, Inc. Inter-processor communication
US9164886B1 (en) 2010-09-21 2015-10-20 Western Digital Technologies, Inc. System and method for multistage processing in a memory storage subsystem
US9021192B1 (en) 2010-09-21 2015-04-28 Western Digital Technologies, Inc. System and method for enhancing processing of memory access requests
US9158670B1 (en) 2011-06-30 2015-10-13 Western Digital Technologies, Inc. System and method for dynamically adjusting garbage collection policies in solid-state memory
WO2012149812A1 (zh) * 2011-10-27 2012-11-08 华为技术有限公司 一种防止节点控制器死锁的方法及节点控制器
US9619303B2 (en) 2012-04-11 2017-04-11 Hewlett Packard Enterprise Development Lp Prioritized conflict handling in a system
US9465740B2 (en) 2013-04-11 2016-10-11 Apple Inc. Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers
US9925492B2 (en) * 2014-03-24 2018-03-27 Mellanox Technologies, Ltd. Remote transactional memory
FR3021773B1 (fr) * 2014-05-27 2017-10-06 Bull Sas Interrogation speculative en memoire centrale d'un systeme multiprocesseur
US9658963B2 (en) * 2014-12-23 2017-05-23 Intel Corporation Speculative reads in buffered memory
US10642780B2 (en) 2016-03-07 2020-05-05 Mellanox Technologies, Ltd. Atomic access to object pool over RDMA transport network
US10552367B2 (en) 2017-07-26 2020-02-04 Mellanox Technologies, Ltd. Network data transactions using posted and non-posted operations
US10613980B2 (en) * 2017-12-19 2020-04-07 International Business Machines Corporation Coherence protocol providing speculative coherence response to directory probe
US10579527B2 (en) 2018-01-17 2020-03-03 International Business Machines Corporation Remote node broadcast of requests in a multinode data processing system
US10713169B2 (en) 2018-01-17 2020-07-14 International Business Machines Corporation Remote node broadcast of requests in a multinode data processing system
US10387310B2 (en) 2018-01-17 2019-08-20 International Business Machines Corporation Remote node broadcast of requests in a multinode data processing system
GR20180100189A (el) * 2018-05-03 2020-01-22 Arm Limited Δικτυο επεξεργασιας δεδομενων με συμπυκνωση ροης για μεταφορα δεδομενων μεσω streaming
US11068407B2 (en) 2018-10-26 2021-07-20 International Business Machines Corporation Synchronized access to data in shared memory by protecting the load target address of a load-reserve instruction
US10884740B2 (en) 2018-11-08 2021-01-05 International Business Machines Corporation Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads
US11119781B2 (en) 2018-12-11 2021-09-14 International Business Machines Corporation Synchronized access to data in shared memory by protecting the load target address of a fronting load
US11106608B1 (en) 2020-06-22 2021-08-31 International Business Machines Corporation Synchronizing access to shared memory by extending protection for a target address of a store-conditional request
US11693776B2 (en) 2021-06-18 2023-07-04 International Business Machines Corporation Variable protection window extension for a target address of a store-conditional request

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02205963A (ja) 1989-01-27 1990-08-15 Digital Equip Corp <Dec> 読取中断処理
JPH06282528A (ja) 1993-01-29 1994-10-07 Internatl Business Mach Corp <Ibm> データ転送方法及びそのシステム
US5878268A (en) 1996-07-01 1999-03-02 Sun Microsystems, Inc. Multiprocessing system configured to store coherency state within multiple subnodes of a processing node
US5958019A (en) * 1996-07-01 1999-09-28 Sun Microsystems, Inc. Multiprocessing system configured to perform synchronization operations
US5950226A (en) * 1996-07-01 1999-09-07 Sun Microsystems, Inc. Multiprocessing system employing a three-hop communication protocol
US5892970A (en) * 1996-07-01 1999-04-06 Sun Microsystems, Inc. Multiprocessing system configured to perform efficient block copy operations
US5754877A (en) * 1996-07-02 1998-05-19 Sun Microsystems, Inc. Extended symmetrical multiprocessor architecture

Also Published As

Publication number Publication date
HUP0104577A2 (hu) 2002-03-28
WO2000036514A1 (en) 2000-06-22
DE69906585T2 (de) 2004-02-12
RU2220444C2 (ru) 2003-12-27
CN1330783A (zh) 2002-01-09
EP1153349B1 (de) 2003-04-02
AU1672500A (en) 2000-07-03
ES2196893T3 (es) 2003-12-16
KR20010101193A (ko) 2001-11-14
KR100465583B1 (ko) 2005-01-13
CZ20012153A3 (cs) 2001-09-12
PL348859A1 (en) 2002-06-17
ATE236431T1 (de) 2003-04-15
CN1157659C (zh) 2004-07-14
CA2349569A1 (en) 2000-06-22
EP1153349A1 (de) 2001-11-14
IL142265A0 (en) 2002-03-10
CA2349569C (en) 2005-04-05
TW446883B (en) 2001-07-21
US6338122B1 (en) 2002-01-08
HUP0104577A3 (en) 2003-11-28
IL142265A (en) 2007-06-03

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Representative=s name: DUSCHER, R., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 7