AU9604598A - Apparatus and method for device timing compensation - Google Patents

Apparatus and method for device timing compensation

Info

Publication number
AU9604598A
AU9604598A AU96045/98A AU9604598A AU9604598A AU 9604598 A AU9604598 A AU 9604598A AU 96045/98 A AU96045/98 A AU 96045/98A AU 9604598 A AU9604598 A AU 9604598A AU 9604598 A AU9604598 A AU 9604598A
Authority
AU
Australia
Prior art keywords
memory core
timing
memory
timing signals
commands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU96045/98A
Other languages
English (en)
Inventor
Abhijit M. Abhyankar
Richard M Barth
Craig E. Hampel
Donald C. Stark
Ely K. Tsern
Frederick A Ware
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22038016&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=AU9604598(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Rambus Inc filed Critical Rambus Inc
Publication of AU9604598A publication Critical patent/AU9604598A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Landscapes

  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
  • Paper (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Static Random-Access Memory (AREA)
  • Optical Recording Or Reproduction (AREA)
  • Optical Communication System (AREA)
AU96045/98A 1997-10-10 1998-10-09 Apparatus and method for device timing compensation Abandoned AU9604598A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US6176997P 1997-10-10 1997-10-10
US60061769 1997-10-10
PCT/US1998/021491 WO1999019876A1 (en) 1997-10-10 1998-10-09 Apparatus and method for device timing compensation

Publications (1)

Publication Number Publication Date
AU9604598A true AU9604598A (en) 1999-05-03

Family

ID=22038016

Family Applications (1)

Application Number Title Priority Date Filing Date
AU96045/98A Abandoned AU9604598A (en) 1997-10-10 1998-10-09 Apparatus and method for device timing compensation

Country Status (8)

Country Link
US (1) US6226754B1 (enExample)
EP (1) EP1019911B1 (enExample)
JP (3) JP4578676B2 (enExample)
KR (1) KR100618242B1 (enExample)
AT (1) ATE245303T1 (enExample)
AU (1) AU9604598A (enExample)
DE (1) DE69816464T2 (enExample)
WO (1) WO1999019876A1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6154821A (en) * 1998-03-10 2000-11-28 Rambus Inc. Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
US6646953B1 (en) 2000-07-06 2003-11-11 Rambus Inc. Single-clock, strobeless signaling system
US6643787B1 (en) 1999-10-19 2003-11-04 Rambus Inc. Bus system optimization
US6584576B1 (en) * 1999-11-12 2003-06-24 Kingston Technology Corporation Memory system using complementary delay elements to reduce rambus module timing skew
US6516396B1 (en) * 1999-12-22 2003-02-04 Intel Corporation Means to extend tTR range of RDRAMS via the RDRAM memory controller
US6658523B2 (en) * 2001-03-13 2003-12-02 Micron Technology, Inc. System latency levelization for read data
US6675272B2 (en) * 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US7698441B2 (en) * 2002-10-03 2010-04-13 International Business Machines Corporation Intelligent use of user data to pre-emptively prevent execution of a query violating access controls
DE10345550B3 (de) * 2003-09-30 2005-02-10 Infineon Technologies Ag Speicheranordnung mit mehreren RAM-Bausteinen
DE102004016337A1 (de) * 2004-04-02 2005-10-27 Siemens Ag Empfangsschaltung
US7669027B2 (en) * 2004-08-19 2010-02-23 Micron Technology, Inc. Memory command delay balancing in a daisy-chained memory topology
US7248511B2 (en) * 2005-02-24 2007-07-24 Infineon Technologies Ag Random access memory including selective activation of select line
US8327104B2 (en) * 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US7940545B2 (en) * 2008-06-24 2011-05-10 Freescale Semiconductor, Inc. Low power read scheme for read only memory (ROM)
US10566040B2 (en) 2016-07-29 2020-02-18 Micron Technology, Inc. Variable page size architecture
US10892007B2 (en) 2018-08-31 2021-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Variable delay word line enable
DE102018128927B4 (de) * 2018-08-31 2024-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Wortleitungsaktivierung für eine variable Verzögerung
JP6986127B1 (ja) * 2020-10-21 2021-12-22 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. メモリシステムおよびその操作方法
US12267996B2 (en) * 2022-05-04 2025-04-01 Atomera Incorporated DRAM sense amplifier architecture with reduced power consumption and related methods
US12635122B2 (en) 2022-11-16 2026-05-19 Atomera Incorporated Multi-chip memory system including DRAM chips with integrated comparator arrays and method of operating same

Family Cites Families (23)

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Publication number Priority date Publication date Assignee Title
KR960003526B1 (ko) * 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
JPH04147492A (ja) * 1990-10-11 1992-05-20 Hitachi Ltd 半導体メモリ
GB2250359A (en) * 1990-11-19 1992-06-03 Anamartic Ltd Addressing of chained circuit modules
JPH0567394A (ja) * 1991-09-09 1993-03-19 Seiko Epson Corp 半導体記憶装置
US5608896A (en) 1992-05-28 1997-03-04 Texas Instruments Incorporated Time skewing arrangement for operating memory devices in synchronism with a data processor
JPH0645892A (ja) * 1992-08-24 1994-02-18 Yamaha Corp 信号遅延回路
JPH06124230A (ja) * 1992-10-09 1994-05-06 Casio Electron Mfg Co Ltd ダイナミックｒａｍアクセス制御装置
JPH06273478A (ja) * 1993-03-20 1994-09-30 Hitachi Ltd クロックスキュー補正回路、及び半導体集積回路
JPH0745068A (ja) * 1993-08-02 1995-02-14 Mitsubishi Electric Corp 同期型半導体記憶装置
JPH0784863A (ja) * 1993-09-20 1995-03-31 Hitachi Ltd 情報処理装置およびそれに適した半導体記憶装置
EP0660329B1 (en) * 1993-12-16 2003-04-09 Mosaid Technologies Incorporated Variable latency, output buffer and synchronizer for synchronous memory
JP2991023B2 (ja) * 1993-12-28 1999-12-20 株式会社日立製作所 データ送信装置、データ送受信装置及びシステム
JPH08123717A (ja) * 1994-10-25 1996-05-17 Oki Electric Ind Co Ltd 半導体記憶装置
JPH08130448A (ja) * 1994-10-31 1996-05-21 Sanyo Electric Co Ltd 可変遅延回路
KR0146530B1 (ko) 1995-05-25 1998-09-15 김광호 단속제어회로를 구비한 반도체 메모리 장치와 제어방법
US5600605A (en) * 1995-06-07 1997-02-04 Micron Technology, Inc. Auto-activate on synchronous dynamic random access memory
JPH09139074A (ja) * 1995-11-10 1997-05-27 Hitachi Ltd ダイナミック型ｒａｍ
JP2000502204A (ja) * 1995-12-15 2000-02-22 ユニシス・コーポレイション 遅延回路および遅延回路を使用するメモリ
US6043684A (en) * 1995-12-20 2000-03-28 Cypress Semiconductor Corp. Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit
JP3986578B2 (ja) * 1996-01-17 2007-10-03 三菱電機株式会社 同期型半導体記憶装置
JPH10340222A (ja) * 1997-06-09 1998-12-22 Nec Corp メモリ装置の入力回路及び出力回路
US5936977A (en) * 1997-09-17 1999-08-10 Cypress Semiconductor Corp. Scan path circuitry including a programmable delay circuit

Also Published As

Publication number Publication date
JP2001520431A (ja) 2001-10-30
KR20010031040A (ko) 2001-04-16
EP1019911B1 (en) 2003-07-16
EP1019911A1 (en) 2000-07-19
JP2008210502A (ja) 2008-09-11
JP2008305537A (ja) 2008-12-18
KR100618242B1 (ko) 2006-09-04
JP4578676B2 (ja) 2010-11-10
WO1999019876A1 (en) 1999-04-22
DE69816464T2 (de) 2004-04-15
ATE245303T1 (de) 2003-08-15
US6226754B1 (en) 2001-05-01
JP4579304B2 (ja) 2010-11-10
DE69816464D1 (de) 2003-08-21
JP4870122B2 (ja) 2012-02-08

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase