DE69432455T2 - Ausgangpuffer mit variabler Latenz und Synchronisiereinrichtung für synchronen Speicher - Google Patents

Ausgangpuffer mit variabler Latenz und Synchronisiereinrichtung für synchronen Speicher

Info

Publication number
DE69432455T2
DE69432455T2 DE69432455T DE69432455T DE69432455T2 DE 69432455 T2 DE69432455 T2 DE 69432455T2 DE 69432455 T DE69432455 T DE 69432455T DE 69432455 T DE69432455 T DE 69432455T DE 69432455 T2 DE69432455 T2 DE 69432455T2
Authority
DE
Germany
Prior art keywords
synchronizer
output buffer
synchronous memory
variable latency
latency output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69432455T
Other languages
English (en)
Other versions
DE69432455D1 (de
Inventor
Tomasz Wojcicki
Graham Allan
Francis Larochelle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Fujitsu Semiconductor Ltd
Original Assignee
Mosaid Technologies Inc
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/167,044 external-priority patent/US5424983A/en
Priority claimed from US08/167,489 external-priority patent/US5402388A/en
Application filed by Mosaid Technologies Inc, Fujitsu Ltd filed Critical Mosaid Technologies Inc
Publication of DE69432455D1 publication Critical patent/DE69432455D1/de
Application granted granted Critical
Publication of DE69432455T2 publication Critical patent/DE69432455T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE69432455T 1993-12-16 1994-12-09 Ausgangpuffer mit variabler Latenz und Synchronisiereinrichtung für synchronen Speicher Expired - Lifetime DE69432455T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/167,044 US5424983A (en) 1993-12-16 1993-12-16 Output buffer and synchronizer
US08/167,489 US5402388A (en) 1993-12-16 1993-12-16 Variable latency scheme for synchronous memory

Publications (2)

Publication Number Publication Date
DE69432455D1 DE69432455D1 (de) 2003-05-15
DE69432455T2 true DE69432455T2 (de) 2003-11-20

Family

ID=26862809

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69432455T Expired - Lifetime DE69432455T2 (de) 1993-12-16 1994-12-09 Ausgangpuffer mit variabler Latenz und Synchronisiereinrichtung für synchronen Speicher

Country Status (4)

Country Link
EP (1) EP0660329B1 (de)
JP (1) JP3812959B2 (de)
KR (1) KR100221915B1 (de)
DE (1) DE69432455T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960004567B1 (ko) * 1994-02-04 1996-04-09 삼성전자주식회사 반도체 메모리 장치의 데이타 출력 버퍼
JP2616567B2 (ja) * 1994-09-28 1997-06-04 日本電気株式会社 半導体記憶装置
JP3183321B2 (ja) * 1995-11-10 2001-07-09 日本電気株式会社 半導体記憶装置
DE69816464T2 (de) 1997-10-10 2004-04-15 Rambus Inc., Los Altos Vorrichtung und verfahren zum zeitverzögerungsausgleich von einrichtungen
US6205062B1 (en) * 1998-11-13 2001-03-20 Hyundai Electronics Industries Co. Ltd. CAS latency control circuit
US6356987B1 (en) * 1999-03-10 2002-03-12 Atmel Corporation Microprocessing device having programmable wait states
KR100529397B1 (ko) * 2002-04-27 2005-11-17 주식회사 하이닉스반도체 반도체 장치의 출력 버퍼
DE102005013238B4 (de) * 2005-03-22 2015-07-16 Infineon Technologies Ag Verfahren und Einrichtung zum Übertragen von Justierinformation für Datenschnittstellen-Treiber eines RAM-Bausteins
US8266471B2 (en) * 2010-02-09 2012-09-11 Mosys, Inc. Memory device including a memory block having a fixed latency data output
US9727395B2 (en) 2015-07-01 2017-08-08 International Business Machines Corporation Robust and adaptable management of event counters

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3100622B2 (ja) * 1990-11-20 2000-10-16 沖電気工業株式会社 同期型ダイナミックｒａｍ
TW198135B (de) * 1990-11-20 1993-01-11 Oki Electric Ind Co Ltd

Also Published As

Publication number Publication date
KR100221915B1 (ko) 1999-10-01
JP3812959B2 (ja) 2006-08-23
JPH07226080A (ja) 1995-08-22
DE69432455D1 (de) 2003-05-15
KR950020730A (ko) 1995-07-24
EP0660329A2 (de) 1995-06-28
EP0660329B1 (de) 2003-04-09
EP0660329A3 (de) 1996-01-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

Owner name: MOSAID TECHNOLOGIES INCORPORATED, KANATA, ONTA, CA

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

Owner name: MOSAID TECHNOLOGIES INC., OTTAWA, ONTARIO, CA

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

Owner name: MOSAID TECHNOLOGIES INC., OTTAWA, ONTARIO, CA

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE