IT1238313B - Memoria tampone in tandem - Google Patents
Memoria tampone in tandemInfo
- Publication number
- IT1238313B IT1238313B IT01909190A IT1909190A IT1238313B IT 1238313 B IT1238313 B IT 1238313B IT 01909190 A IT01909190 A IT 01909190A IT 1909190 A IT1909190 A IT 1909190A IT 1238313 B IT1238313 B IT 1238313B
- Authority
- IT
- Italy
- Prior art keywords
- buffer memory
- tandem buffer
- tandem
- memory
- buffer
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
- G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT01909190A IT1238313B (it) | 1990-01-18 | 1990-01-18 | Memoria tampone in tandem |
EP90122942A EP0437712B1 (en) | 1990-01-18 | 1990-11-30 | Tandem cache memory |
DE69030368T DE69030368T2 (de) | 1990-01-18 | 1990-11-30 | Tandem-Cache-Speicher |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT01909190A IT1238313B (it) | 1990-01-18 | 1990-01-18 | Memoria tampone in tandem |
Publications (2)
Publication Number | Publication Date |
---|---|
IT9019091A1 IT9019091A1 (it) | 1991-07-19 |
IT1238313B true IT1238313B (it) | 1993-07-12 |
Family
ID=11154455
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT01909190A IT1238313B (it) | 1990-01-18 | 1990-01-18 | Memoria tampone in tandem |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0437712B1 (it) |
DE (1) | DE69030368T2 (it) |
IT (1) | IT1238313B (it) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0612013A1 (en) * | 1993-01-21 | 1994-08-24 | Advanced Micro Devices, Inc. | Combination prefetch buffer and instruction cache cross references to related applications |
US5603004A (en) * | 1994-02-14 | 1997-02-11 | Hewlett-Packard Company | Method for decreasing time penalty resulting from a cache miss in a multi-level cache system |
FR2755523B1 (fr) * | 1996-11-05 | 1998-12-04 | Bull Sa | Circuit electrique pour echanger des donnees entre un microprocesseur et une memoire et calculateur comprenant un tel circuit |
GB2401967B (en) * | 1999-12-30 | 2005-01-05 | Intel Corp | Dual cache system |
US6829680B1 (en) | 2000-01-05 | 2004-12-07 | Sun Microsystems, Inc. | Method for employing a page prefetch cache for database applications |
AU2472601A (en) * | 2000-01-05 | 2001-07-16 | Sun Microsystems, Inc. | A method for employing a page prefetch cache for database applications |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4442488A (en) * | 1980-05-05 | 1984-04-10 | Floating Point Systems, Inc. | Instruction cache memory system |
JPS6154547A (ja) * | 1984-08-24 | 1986-03-18 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 3レベルの階層メモリを備えたデ−タ処理システム |
IT1215539B (it) * | 1987-06-03 | 1990-02-14 | Honeywell Inf Systems | Memoria tampone trasparente. |
-
1990
- 1990-01-18 IT IT01909190A patent/IT1238313B/it active IP Right Grant
- 1990-11-30 DE DE69030368T patent/DE69030368T2/de not_active Expired - Fee Related
- 1990-11-30 EP EP90122942A patent/EP0437712B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69030368T2 (de) | 1997-07-17 |
DE69030368D1 (de) | 1997-05-07 |
IT9019091A1 (it) | 1991-07-19 |
EP0437712B1 (en) | 1997-04-02 |
EP0437712A3 (en) | 1991-11-13 |
EP0437712A2 (en) | 1991-07-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted |