ATE43028T1 - Verfahren zum herstellen einer schichtstruktur. - Google Patents

Verfahren zum herstellen einer schichtstruktur.

Info

Publication number
ATE43028T1
ATE43028T1 AT84303936T AT84303936T ATE43028T1 AT E43028 T1 ATE43028 T1 AT E43028T1 AT 84303936 T AT84303936 T AT 84303936T AT 84303936 T AT84303936 T AT 84303936T AT E43028 T1 ATE43028 T1 AT E43028T1
Authority
AT
Austria
Prior art keywords
metal layer
layer
layered structure
etching
making
Prior art date
Application number
AT84303936T
Other languages
English (en)
Inventor
Stephen James Rhodes
Raymond Edward Oakley
Original Assignee
Plessey Overseas
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Overseas filed Critical Plessey Overseas
Application granted granted Critical
Publication of ATE43028T1 publication Critical patent/ATE43028T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H10W20/0693—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs by forming self-aligned vias

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Glass Compositions (AREA)
  • Laminated Bodies (AREA)
AT84303936T 1983-06-16 1984-06-11 Verfahren zum herstellen einer schichtstruktur. ATE43028T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB838316476A GB8316476D0 (en) 1983-06-16 1983-06-16 Producing layered structure
EP84303936A EP0129389B1 (de) 1983-06-16 1984-06-11 Verfahren zum Herstellen einer Schichtstruktur

Publications (1)

Publication Number Publication Date
ATE43028T1 true ATE43028T1 (de) 1989-05-15

Family

ID=10544350

Family Applications (1)

Application Number Title Priority Date Filing Date
AT84303936T ATE43028T1 (de) 1983-06-16 1984-06-11 Verfahren zum herstellen einer schichtstruktur.

Country Status (6)

Country Link
US (1) US4536951A (de)
EP (1) EP0129389B1 (de)
JP (1) JPS6057650A (de)
AT (1) ATE43028T1 (de)
DE (1) DE3478171D1 (de)
GB (1) GB8316476D0 (de)

Families Citing this family (57)

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GB8316477D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
US4670091A (en) * 1984-08-23 1987-06-02 Fairchild Semiconductor Corporation Process for forming vias on integrated circuits
DE3571723D1 (en) * 1984-08-23 1989-08-24 Fairchild Semiconductor A process for forming vias on integrated circuits
IT1213261B (it) * 1984-12-20 1989-12-14 Sgs Thomson Microelectronics Dispositivo a semiconduttore con metallizzazione a piu' spessori eprocedimento per la sua fabbricazione.
JPS61258453A (ja) * 1985-05-13 1986-11-15 Toshiba Corp 半導体装置の製造方法
GB8518231D0 (en) * 1985-07-19 1985-08-29 Plessey Co Plc Producing layered structures
US4954423A (en) * 1985-08-06 1990-09-04 Texas Instruments Incorporated Planar metal interconnection for a VLSI device
JPS6269642A (ja) * 1985-09-24 1987-03-30 Toshiba Corp 半導体装置の製造方法
US4926236A (en) * 1986-02-12 1990-05-15 General Electric Company Multilayer interconnect and method of forming same
US4786962A (en) * 1986-06-06 1988-11-22 Hewlett-Packard Company Process for fabricating multilevel metal integrated circuits and structures produced thereby
JPS62291138A (ja) * 1986-06-11 1987-12-17 Toshiba Corp 半導体装置およびその製造方法
NL8701032A (nl) * 1987-05-01 1988-12-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met interconnecties die zowel boven een halfgeleidergebied als boven een daaraan grenzend isolatiegebied liggen.
US4878770A (en) * 1987-09-09 1989-11-07 Analog Devices, Inc. IC chips with self-aligned thin film resistors
EP0317770A1 (de) * 1987-11-23 1989-05-31 Texas Instruments Incorporated Selbstausrichtende ebene Metallverbindungen für ein VLSI-Bauelement
US5132775A (en) * 1987-12-11 1992-07-21 Texas Instruments Incorporated Methods for and products having self-aligned conductive pillars on interconnects
US5025303A (en) * 1988-02-26 1991-06-18 Texas Instruments Incorporated Product of pillar alignment and formation process
IT1225618B (it) * 1988-09-14 1990-11-22 Sgs Thomson Microelectronics Formazione di contatti sub-micrometrici mediante pilastri conduttori preformati sul wafer e planarizzati
JPH02265243A (ja) * 1989-04-05 1990-10-30 Nec Corp 多層配線およびその形成方法
DE69031357T2 (de) * 1989-04-21 1998-04-02 Nippon Electric Co Halbleiteranordnung mit Mehrschichtleiter
US4933045A (en) * 1989-06-02 1990-06-12 International Business Machines Corporation Thin film multilayer laminate interconnection board assembly method
US5285099A (en) * 1992-12-15 1994-02-08 International Business Machines Corporation SiCr microfuses
JP2727909B2 (ja) * 1993-03-26 1998-03-18 松下電器産業株式会社 金属配線の形成方法
JPH06314687A (ja) * 1993-04-30 1994-11-08 Sony Corp 多層配線構造の半導体装置およびその製造方法
KR0134108B1 (ko) * 1994-06-30 1998-04-20 김주용 반도체 소자의 제조방법
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5512514A (en) * 1994-11-08 1996-04-30 Spider Systems, Inc. Self-aligned via and contact interconnect manufacturing method
US5736457A (en) * 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization
US6191484B1 (en) * 1995-07-28 2001-02-20 Stmicroelectronics, Inc. Method of forming planarized multilevel metallization in an integrated circuit
US5593919A (en) * 1995-09-05 1997-01-14 Motorola Inc. Process for forming a semiconductor device including conductive members
US5539255A (en) * 1995-09-07 1996-07-23 International Business Machines Corporation Semiconductor structure having self-aligned interconnection metallization formed from a single layer of metal
US5693568A (en) * 1995-12-14 1997-12-02 Advanced Micro Devices, Inc. Reverse damascene via structures
US6004874A (en) * 1996-06-26 1999-12-21 Cypress Semiconductor Corporation Method for forming an interconnect
US5858254A (en) * 1997-01-28 1999-01-12 International Business Machines Corporation Multilayered circuitized substrate and method of fabrication
US6133635A (en) * 1997-06-30 2000-10-17 Philips Electronics North America Corp. Process for making self-aligned conductive via structures
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
US6295721B1 (en) * 1999-12-28 2001-10-02 Taiwan Semiconductor Manufacturing Company Metal fuse in copper dual damascene
US20020155693A1 (en) * 2001-04-23 2002-10-24 Chartered Semiconductor Manufacturing Ltd. Method to form self-aligned anti-via interconnects
US20030082906A1 (en) * 2001-10-30 2003-05-01 Lammert Michael D. Via formation in polymers
US7358116B2 (en) * 2002-04-29 2008-04-15 Intel Corporation Substrate conductive post formation
JP2004031439A (ja) * 2002-06-21 2004-01-29 Renesas Technology Corp 半導体集積回路装置およびその製造方法
US6887395B2 (en) * 2003-02-10 2005-05-03 Intel Corporation Method of forming sub-micron-size structures over a substrate
US20090160019A1 (en) * 2007-12-20 2009-06-25 Mediatek Inc. Semiconductor capacitor
US10692759B2 (en) * 2018-07-17 2020-06-23 Applied Materials, Inc. Methods for manufacturing an interconnect structure for semiconductor devices
US10950493B1 (en) 2019-09-19 2021-03-16 International Business Machines Corporation Interconnects having air gap spacers
US11177171B2 (en) 2019-10-01 2021-11-16 International Business Machines Corporation Encapsulated top via interconnects
US11508617B2 (en) * 2019-10-24 2022-11-22 Applied Materials, Inc. Method of forming interconnect for semiconductor device
CN110993583A (zh) * 2019-12-06 2020-04-10 中国科学院微电子研究所 金属化叠层及其制造方法及包括金属化叠层的电子设备
US11205591B2 (en) 2020-01-09 2021-12-21 International Business Machines Corporation Top via interconnect with self-aligned barrier layer
US11164774B2 (en) 2020-01-16 2021-11-02 International Business Machines Corporation Interconnects with spacer structure for forming air-gaps
US11257677B2 (en) 2020-01-24 2022-02-22 Applied Materials, Inc. Methods and devices for subtractive self-alignment
US11709553B2 (en) 2021-02-25 2023-07-25 International Business Machines Corporation Automated prediction of a location of an object using machine learning
KR102907017B1 (ko) 2021-07-07 2026-01-05 삼성전자주식회사 반도체 장치
US11923246B2 (en) 2021-09-15 2024-03-05 International Business Machines Corporation Via CD controllable top via structure
US12402329B2 (en) 2021-11-03 2025-08-26 International Business Machines Corporation Top via containing random-access memory cross-bar array
US12538785B2 (en) 2021-11-03 2026-01-27 International Business Machines Corporation Fully-aligned and dielectric damage-less top via interconnect structure
US12062609B2 (en) 2021-11-05 2024-08-13 International Business Machines Corporation Electronic fuse structure embedded in top via
US12550708B2 (en) 2022-02-21 2026-02-10 International Business Machines Corporation Top via interconnect with an embedded antifuse

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US4029562A (en) * 1976-04-29 1977-06-14 Ibm Corporation Forming feedthrough connections for multi-level interconnections metallurgy systems
US4289834A (en) * 1977-10-20 1981-09-15 Ibm Corporation Dense dry etched multi-level metallurgy with non-overlapped vias
CA1120611A (en) * 1978-12-29 1982-03-23 Hormazdyar M. Dalal Forming interconnections for multilevel interconnection metallurgy systems
JPS5595340A (en) * 1979-01-10 1980-07-19 Chiyou Lsi Gijutsu Kenkyu Kumiai Preparation of semiconductor device
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
US4392298A (en) * 1981-07-27 1983-07-12 Bell Telephone Laboratories, Incorporated Integrated circuit device connection process
JPS5967649A (ja) * 1982-10-12 1984-04-17 Hitachi Ltd 多層配線の製造方法

Also Published As

Publication number Publication date
EP0129389A2 (de) 1984-12-27
JPS6057650A (ja) 1985-04-03
GB8316476D0 (en) 1983-07-20
DE3478171D1 (en) 1989-06-15
EP0129389B1 (de) 1989-05-10
US4536951A (en) 1985-08-27
EP0129389A3 (en) 1986-10-22

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
EEIH Change in the person of patent owner
REN Ceased due to non-payment of the annual fee