JPS568834A - Manufacture of projection for substrate conductor layer - Google Patents

Manufacture of projection for substrate conductor layer

Info

Publication number
JPS568834A
JPS568834A JP8374279A JP8374279A JPS568834A JP S568834 A JPS568834 A JP S568834A JP 8374279 A JP8374279 A JP 8374279A JP 8374279 A JP8374279 A JP 8374279A JP S568834 A JPS568834 A JP S568834A
Authority
JP
Japan
Prior art keywords
layer
projection
conductor layer
resist
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8374279A
Other languages
Japanese (ja)
Other versions
JPS628945B2 (en
Inventor
Kazuyoshi Haniwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP8374279A priority Critical patent/JPS568834A/en
Publication of JPS568834A publication Critical patent/JPS568834A/en
Publication of JPS628945B2 publication Critical patent/JPS628945B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

PURPOSE:To shorten the steps of forming a projection made of a conductor layer for electrically connecting with the semiconductor element on a tape carrier and eliminate the isolation of a surface resist by executing the surface resist coating step after a back surface patterning step when forming the projection thereon. CONSTITUTION:Conductor layers 20 are coated and etched on a region of an insulating tape carrier 1 provided with conveying sprocket holes 5 at both side edges to form a connecting terminal 22 as below. That is, a conductor layer 20 made of copper foil or the like is coated on the respective regions of the carrier 1, a resist layer is formed on the back surface thereof, is patterned to form a mask 4 of the resist layer through the opening of the carrier 1. Thereafter, a protective resist layer 30 is coated on the surface of the conductor layer 20, is etched from the back surface to form a projection 21 on the layer 20. Thereafter, the layer 30 is modified to a resist layer 31 having predetermined pattern, the protective resist layer 60 is buried in the opening, is etched from the surface, the conductor layer 20 is retained as a connecting terminal 22 containing the projection 21, and the layer 60 is removed.
JP8374279A 1979-07-02 1979-07-02 Manufacture of projection for substrate conductor layer Granted JPS568834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8374279A JPS568834A (en) 1979-07-02 1979-07-02 Manufacture of projection for substrate conductor layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8374279A JPS568834A (en) 1979-07-02 1979-07-02 Manufacture of projection for substrate conductor layer

Publications (2)

Publication Number Publication Date
JPS568834A true JPS568834A (en) 1981-01-29
JPS628945B2 JPS628945B2 (en) 1987-02-25

Family

ID=13810970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8374279A Granted JPS568834A (en) 1979-07-02 1979-07-02 Manufacture of projection for substrate conductor layer

Country Status (1)

Country Link
JP (1) JPS568834A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57204157A (en) * 1981-06-11 1982-12-14 Shindo Denshi Kogyo Kk Manufacture of wiring section for mounting chip
JPS57204158A (en) * 1981-06-11 1982-12-14 Shindo Denshi Kogyo Kk Manufacture of wiring section for mounting chip
US6740148B2 (en) 1999-09-24 2004-05-25 Nasa Auto Exhaust gas cleaner

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS546775A (en) * 1977-06-17 1979-01-19 Nec Corp Semiconductor device featuring stepped electrode structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS546775A (en) * 1977-06-17 1979-01-19 Nec Corp Semiconductor device featuring stepped electrode structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57204157A (en) * 1981-06-11 1982-12-14 Shindo Denshi Kogyo Kk Manufacture of wiring section for mounting chip
JPS57204158A (en) * 1981-06-11 1982-12-14 Shindo Denshi Kogyo Kk Manufacture of wiring section for mounting chip
US6740148B2 (en) 1999-09-24 2004-05-25 Nasa Auto Exhaust gas cleaner

Also Published As

Publication number Publication date
JPS628945B2 (en) 1987-02-25

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