JPS57188846A - Forming method for buried wiring - Google Patents

Forming method for buried wiring

Info

Publication number
JPS57188846A
JPS57188846A JP7232981A JP7232981A JPS57188846A JP S57188846 A JPS57188846 A JP S57188846A JP 7232981 A JP7232981 A JP 7232981A JP 7232981 A JP7232981 A JP 7232981A JP S57188846 A JPS57188846 A JP S57188846A
Authority
JP
Japan
Prior art keywords
wiring
shaped
layers
layer
whole surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7232981A
Other languages
Japanese (ja)
Inventor
Eiichi Yamamoto
Hiroaki Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP7232981A priority Critical patent/JPS57188846A/en
Publication of JPS57188846A publication Critical patent/JPS57188846A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form and laminate flat wiring layers through nonselective ion etching by coating the wiring layers shaped onto an insulating layer patterned with resists and flatly forming the layers. CONSTITUTION:The insulating layer 2 on a semiconductor substate 1 is patterned, contact holes, etc. are shaped, and an Al conductor layer 3 is formed onto the whole surface. The resist layer 4 is flatly shaped onto the whole surface through an application method, and the whole surface is etched through nonselective etching such as reactive ion etching to form the flat wiring surface. Multilayer wiring can be shaped without generating disconnection by also forming each wiring 6 after the second layer, insulating layers 5, etc. similarly.
JP7232981A 1981-05-15 1981-05-15 Forming method for buried wiring Pending JPS57188846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7232981A JPS57188846A (en) 1981-05-15 1981-05-15 Forming method for buried wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7232981A JPS57188846A (en) 1981-05-15 1981-05-15 Forming method for buried wiring

Publications (1)

Publication Number Publication Date
JPS57188846A true JPS57188846A (en) 1982-11-19

Family

ID=13486133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7232981A Pending JPS57188846A (en) 1981-05-15 1981-05-15 Forming method for buried wiring

Country Status (1)

Country Link
JP (1) JPS57188846A (en)

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