JPS5759356A - Structure of multilayer wiring - Google Patents

Structure of multilayer wiring

Info

Publication number
JPS5759356A
JPS5759356A JP13442080A JP13442080A JPS5759356A JP S5759356 A JPS5759356 A JP S5759356A JP 13442080 A JP13442080 A JP 13442080A JP 13442080 A JP13442080 A JP 13442080A JP S5759356 A JPS5759356 A JP S5759356A
Authority
JP
Japan
Prior art keywords
etching
layer wiring
lower layer
mask
contact hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13442080A
Other languages
Japanese (ja)
Inventor
Shinji Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13442080A priority Critical patent/JPS5759356A/en
Publication of JPS5759356A publication Critical patent/JPS5759356A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the generation of disconnection by obviating the simultaneous etching of lower layer wiring at a contact hole section, etc. of a layer insulating film due to the displacement of a mask at the time of etching the upper layer wiring of the multilayer wiring formed onto a semiconductor substrate. CONSTITUTION:A conductive etching preventive film in Mo, etc., which are not eroded by an etching liquid of aluminum, is shaped onto the lower layer wiring 13 in aluminum, etc. formed on an insulating layer 2 coating the semiconductor substrate. When etching the upper layer wiring 5 connected to the lower layer wiring through the contact hole 6 shaped to the insulating film 4 while using a photoresist 7 as a mask, the lower layer wiring 13 is not etched because of the existence of the etching preventive film 10 even when one part of the lower layer wiring is exposed due to the displacement of the mask. The etching preventive film may be formed onto the insulating film 4 after shaping the contact hole.
JP13442080A 1980-09-29 1980-09-29 Structure of multilayer wiring Pending JPS5759356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13442080A JPS5759356A (en) 1980-09-29 1980-09-29 Structure of multilayer wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13442080A JPS5759356A (en) 1980-09-29 1980-09-29 Structure of multilayer wiring

Publications (1)

Publication Number Publication Date
JPS5759356A true JPS5759356A (en) 1982-04-09

Family

ID=15127965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13442080A Pending JPS5759356A (en) 1980-09-29 1980-09-29 Structure of multilayer wiring

Country Status (1)

Country Link
JP (1) JPS5759356A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08115980A (en) * 1994-10-14 1996-05-07 Nec Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08115980A (en) * 1994-10-14 1996-05-07 Nec Corp Manufacture of semiconductor device

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