JPS57153447A - Forming method for multilayer wiring - Google Patents

Forming method for multilayer wiring

Info

Publication number
JPS57153447A
JPS57153447A JP3846981A JP3846981A JPS57153447A JP S57153447 A JPS57153447 A JP S57153447A JP 3846981 A JP3846981 A JP 3846981A JP 3846981 A JP3846981 A JP 3846981A JP S57153447 A JPS57153447 A JP S57153447A
Authority
JP
Japan
Prior art keywords
wiring
etched
sio2
substrate
connecting hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3846981A
Other languages
Japanese (ja)
Inventor
Ryuichiro Yamamoto
Yoichi Aono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3846981A priority Critical patent/JPS57153447A/en
Publication of JPS57153447A publication Critical patent/JPS57153447A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the reduction of the thickness of the wiring film of a crossing section and the side surface of a connecting hole, and to obviate disconnection by forming wiring onto a substrate by utilizing a reactive sputtering method and an ion depositing method. CONSTITUTION:When a resist mask 13 is formed onto SiO2 12 on the Si substrate 11 and reactive sputtering is conducted, the surface is etched in an anisotropic shape, and the side surface is not etched. When Al 14 is ion-deposited in the same thickness as the film 12, Al does not adhere on the side surface 13a of a wiring pattern. When the resist 13 is removed, the first wiring layer 15 buries completely the groove of the SiO2 12, and the surface of the substrate is flat. When SiO2 16 is stacked, a resist mask 17 is shaped and the connecting hole is formed through reactive sputtering, the side surface of the film 16 is not etched. Al 18 Is deposited through ion depositing, the resist 17 is removed, and the second wiring layer 19 is shaped. Disconnection is not generated in the solid crossing section or the connecting hole section according to this constitution, wiring is thickened, and resistance can be reduced.
JP3846981A 1981-03-17 1981-03-17 Forming method for multilayer wiring Pending JPS57153447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3846981A JPS57153447A (en) 1981-03-17 1981-03-17 Forming method for multilayer wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3846981A JPS57153447A (en) 1981-03-17 1981-03-17 Forming method for multilayer wiring

Publications (1)

Publication Number Publication Date
JPS57153447A true JPS57153447A (en) 1982-09-22

Family

ID=12526093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3846981A Pending JPS57153447A (en) 1981-03-17 1981-03-17 Forming method for multilayer wiring

Country Status (1)

Country Link
JP (1) JPS57153447A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0124181A2 (en) * 1983-05-02 1984-11-07 Koninklijke Philips Electronics N.V. Semiconductor device comprising a semiconductor body on which conductive tracks are disposed which are interconnected through a window in an insulating layer and method manufacturing same
JPS60225446A (en) * 1984-04-23 1985-11-09 Mitsubishi Electric Corp Manufacture of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5493971A (en) * 1978-01-06 1979-07-25 Nec Corp Production of semiconductor device
JPS5538061A (en) * 1978-09-11 1980-03-17 Fujitsu Ltd Bridging wiring method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5493971A (en) * 1978-01-06 1979-07-25 Nec Corp Production of semiconductor device
JPS5538061A (en) * 1978-09-11 1980-03-17 Fujitsu Ltd Bridging wiring method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0124181A2 (en) * 1983-05-02 1984-11-07 Koninklijke Philips Electronics N.V. Semiconductor device comprising a semiconductor body on which conductive tracks are disposed which are interconnected through a window in an insulating layer and method manufacturing same
JPS60225446A (en) * 1984-04-23 1985-11-09 Mitsubishi Electric Corp Manufacture of semiconductor device

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