JPS6445141A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6445141A
JPS6445141A JP62202548A JP20254887A JPS6445141A JP S6445141 A JPS6445141 A JP S6445141A JP 62202548 A JP62202548 A JP 62202548A JP 20254887 A JP20254887 A JP 20254887A JP S6445141 A JPS6445141 A JP S6445141A
Authority
JP
Japan
Prior art keywords
layer
wiring
wiring layer
pattern
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62202548A
Other languages
Japanese (ja)
Inventor
Toshimichi Iwamori
Yasushi Sakata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP62202548A priority Critical patent/JPS6445141A/en
Publication of JPS6445141A publication Critical patent/JPS6445141A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To unnecessitate a margin of the width of a wiring to be fitted to a connection hole by a method wherein a via wiring layer is provided in advance at a part where a connection hole will be formed on a first wiring layer, and a pattern which becomes a second wiring layer is formed on an interlayer insulating film. CONSTITUTION:The first layer of wiring layer 2 is provided on the whole surface of a semiconductor substrate 1, and after the conductive film of three-layer structure, consisting of said layer 2, an intermediate conductive this film 3 and other wiring layer 4', has been formed, the three-layer structured conductive film is etched in conformity with the first layer of wiring pattern. Then, the resist pattern of a VIA part (VIA part and connected part) 4' is formed, the upper layer of wiring layer only is etched, a state in which only the conductor of the VIA part is left is formed, and sucessively, after an interlayer insulating film 6 has been flatly provided, the interlayer insulating film 6 corresponded to the second layer wiring is removed, and the wiring layer 4 of the VIA part is exposed in the same manner as above. A conductive layer 8' which becomes the second layer of wiring layer is formed on the semiconductor substrate 1 including the part of said wiring layer 4, and the second layer of wiring 8 is formed in the groove. As a result, the matching margin for the connection hole to be provide in the width of the wiring layer is unnecessitated, and the microscopic formation of the wiring pattern can be achieved.
JP62202548A 1987-08-13 1987-08-13 Manufacture of semiconductor device Pending JPS6445141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62202548A JPS6445141A (en) 1987-08-13 1987-08-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62202548A JPS6445141A (en) 1987-08-13 1987-08-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6445141A true JPS6445141A (en) 1989-02-17

Family

ID=16459325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62202548A Pending JPS6445141A (en) 1987-08-13 1987-08-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6445141A (en)

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