JPS57162449A - Formation of multilayer wiring - Google Patents

Formation of multilayer wiring

Info

Publication number
JPS57162449A
JPS57162449A JP4747381A JP4747381A JPS57162449A JP S57162449 A JPS57162449 A JP S57162449A JP 4747381 A JP4747381 A JP 4747381A JP 4747381 A JP4747381 A JP 4747381A JP S57162449 A JPS57162449 A JP S57162449A
Authority
JP
Japan
Prior art keywords
wiring
layer
plasma
covered
lower layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4747381A
Other languages
Japanese (ja)
Other versions
JPS6349901B2 (en
Inventor
Moritaka Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4747381A priority Critical patent/JPS57162449A/en
Publication of JPS57162449A publication Critical patent/JPS57162449A/en
Publication of JPS6349901B2 publication Critical patent/JPS6349901B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent reduction of the sectional area and disconnection of the lower layer wiring even when slipping of position is generated between the upper layer wiring and a connecting hole when patterning of the upper layer Al wiring is to be performed by a method wherein the upper face of the lower layer Al wiring is covered with a plasma Si film. CONSTITUTION:An Si substrate formed with the prescribed element region is covered with PSG19, and a connecting window is formed. The lower layer Al layers 20' are formed selectively, the surface thereof is covered with an interlayer insulating film 22 of PSG, and a connecting window 23 is formed. After the reflow treatment is performed on the window 23, the amorphous plasma Si layer 24 is piled up, and an Al layer 24 is laminated. When etching is performed using a resist mask 26 to form the upper layer Al wirings 25', the plasma Si film 24 prevents etching and removal of the lower layer Al wirings 20' completely, and reduction of quality of the lower layer wiring is not generated. When plasma etching is performed in CF4+O2 gas to form an opening 23 in the film 24, Al is scarcely etched. Finally, the resist mask 26 is removed and is covered with PSG27, heat treatment is performed in Ar gas, the plasma Si layer 24 is made to be diffused in the Al layers 25', 20', and the upper and the lower wiring layers are connected with low resistance to complete the multilayer wiring.
JP4747381A 1981-03-31 1981-03-31 Formation of multilayer wiring Granted JPS57162449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4747381A JPS57162449A (en) 1981-03-31 1981-03-31 Formation of multilayer wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4747381A JPS57162449A (en) 1981-03-31 1981-03-31 Formation of multilayer wiring

Publications (2)

Publication Number Publication Date
JPS57162449A true JPS57162449A (en) 1982-10-06
JPS6349901B2 JPS6349901B2 (en) 1988-10-06

Family

ID=12776106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4747381A Granted JPS57162449A (en) 1981-03-31 1981-03-31 Formation of multilayer wiring

Country Status (1)

Country Link
JP (1) JPS57162449A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62165345A (en) * 1986-01-16 1987-07-21 Fuji Electric Co Ltd Formation of electrode wiring for semiconductor device
JPH03155133A (en) * 1989-11-13 1991-07-03 Nec Corp Method of filling contact hole

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4984788A (en) * 1972-11-29 1974-08-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4984788A (en) * 1972-11-29 1974-08-14

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62165345A (en) * 1986-01-16 1987-07-21 Fuji Electric Co Ltd Formation of electrode wiring for semiconductor device
JPH03155133A (en) * 1989-11-13 1991-07-03 Nec Corp Method of filling contact hole

Also Published As

Publication number Publication date
JPS6349901B2 (en) 1988-10-06

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