JPS5693342A - Formation of multilayer interconnection structure - Google Patents

Formation of multilayer interconnection structure

Info

Publication number
JPS5693342A
JPS5693342A JP16724479A JP16724479A JPS5693342A JP S5693342 A JPS5693342 A JP S5693342A JP 16724479 A JP16724479 A JP 16724479A JP 16724479 A JP16724479 A JP 16724479A JP S5693342 A JPS5693342 A JP S5693342A
Authority
JP
Japan
Prior art keywords
layer
polycrystalline
interconnection
sio
cut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16724479A
Other languages
Japanese (ja)
Other versions
JPS6035827B2 (en
Inventor
Masao Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16724479A priority Critical patent/JPS6035827B2/en
Publication of JPS5693342A publication Critical patent/JPS5693342A/en
Publication of JPS6035827B2 publication Critical patent/JPS6035827B2/en
Expired legal-status Critical Current

Links

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To prevent the interlayer short-circuit of the multilayer interconnection structure by a method wherein an insulating film is selectively removed between the adjoining patterns of upper interconnection layers crossing through the insulating film on a lower interconnection layer, and after an insulating film is provided on the surface of the lower interconnection layer, the upper interconnection layer are provided.
CONSTITUTION: An SiO2 layer 2, a polycrystalline Si lower interconnection layer 3, an SiO2 layer 4 are piled up on an Si substrate 1. A resist mask is applied on it and etching is performed to form a cut off part 8 at the middle part between the upper interconnection layers 7, 7'. The films 4, 3 are etched applying a resist mask 11 to generate a penthouse part. The mask 11 is removed and an SiO2 layer 12 is formed on the exposed polycrystalline Si layer 4. When an upper polycrystalline Si layer 13 is formed on it, the polycrystalline Si layer is not remained on the outside of the SiO2 layer 12 covering the end face of the lower polycrystalline Si layer 3 at the cut off part 8, and the remaining polycrystalline Si layer 6 under the penthouse part of the film 4 is cut apart at the cut off part 8. Accordingly the interlayer short-circuit of the polycrystalline Si multilayer interconnection can be prevented, and the withstand voltage is elevated.
COPYRIGHT: (C)1981,JPO&Japio
JP16724479A 1979-12-22 1979-12-22 Method for forming multilayer wiring structure Expired JPS6035827B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16724479A JPS6035827B2 (en) 1979-12-22 1979-12-22 Method for forming multilayer wiring structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16724479A JPS6035827B2 (en) 1979-12-22 1979-12-22 Method for forming multilayer wiring structure

Publications (2)

Publication Number Publication Date
JPS5693342A true JPS5693342A (en) 1981-07-28
JPS6035827B2 JPS6035827B2 (en) 1985-08-16

Family

ID=15846125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16724479A Expired JPS6035827B2 (en) 1979-12-22 1979-12-22 Method for forming multilayer wiring structure

Country Status (1)

Country Link
JP (1) JPS6035827B2 (en)

Also Published As

Publication number Publication date
JPS6035827B2 (en) 1985-08-16

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