JPS57106146A - Forming method for multilayer wire - Google Patents

Forming method for multilayer wire

Info

Publication number
JPS57106146A
JPS57106146A JP18346080A JP18346080A JPS57106146A JP S57106146 A JPS57106146 A JP S57106146A JP 18346080 A JP18346080 A JP 18346080A JP 18346080 A JP18346080 A JP 18346080A JP S57106146 A JPS57106146 A JP S57106146A
Authority
JP
Japan
Prior art keywords
wire
layer
cutting
hole
forming method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18346080A
Other languages
Japanese (ja)
Inventor
Kazunari Shirai
Masataka Shinguu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18346080A priority Critical patent/JPS57106146A/en
Publication of JPS57106146A publication Critical patent/JPS57106146A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

Abstract

PURPOSE:To simplify the design of a wiring pattern by opening in advance a hole for cutting the first layer wire at an insulating film between a plurality of upper and lower layers and cutting the lower layer wire in the step of patterning the second layer wire. CONSTITUTION:The first layer aluminum wire is formed on a substrate 1. An interlayer insulating film 3 is formed on the wire. A resist layer 4 is patterned, and is etched. Then, the resist is removed to form a wire coupling and cutting hole. The second aluminum wire layer 5 is formed on the overall surface, and the second layer is patterned eventually. Thus, the first and second layer wires 2, 12 are coupled at A, and the first and second wires 2'', 12' are contacted at B, but are not connected to anywhere through the wire 12'. They are disconnected at C. A cutting hole is opened at D, but the second layer wire 2'' is not cut, but can remain.
JP18346080A 1980-12-24 1980-12-24 Forming method for multilayer wire Pending JPS57106146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18346080A JPS57106146A (en) 1980-12-24 1980-12-24 Forming method for multilayer wire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18346080A JPS57106146A (en) 1980-12-24 1980-12-24 Forming method for multilayer wire

Publications (1)

Publication Number Publication Date
JPS57106146A true JPS57106146A (en) 1982-07-01

Family

ID=16136160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18346080A Pending JPS57106146A (en) 1980-12-24 1980-12-24 Forming method for multilayer wire

Country Status (1)

Country Link
JP (1) JPS57106146A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413739A (en) * 1987-04-05 1989-01-18 Oobachi Zubui Manufacture of order-made integrated circuit
US5164339A (en) * 1988-09-30 1992-11-17 Siemens-Bendix Automotive Electronics L.P. Fabrication of oxynitride frontside microstructures

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413739A (en) * 1987-04-05 1989-01-18 Oobachi Zubui Manufacture of order-made integrated circuit
US5164339A (en) * 1988-09-30 1992-11-17 Siemens-Bendix Automotive Electronics L.P. Fabrication of oxynitride frontside microstructures

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