JPS5550667A - Method of fabricating double gate mos-type integrated circuit - Google Patents
Method of fabricating double gate mos-type integrated circuitInfo
- Publication number
- JPS5550667A JPS5550667A JP12437378A JP12437378A JPS5550667A JP S5550667 A JPS5550667 A JP S5550667A JP 12437378 A JP12437378 A JP 12437378A JP 12437378 A JP12437378 A JP 12437378A JP S5550667 A JPS5550667 A JP S5550667A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- pattern
- integrated circuit
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000012856 packing Methods 0.000 abstract 1
- 238000001020 plasma etching Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000001039 wet etching Methods 0.000 abstract 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE: To improve the packing density of a double gate MOS-type integrated circuit by growing double layers of polycrystalline silicon layer on a semiconductor substrate and employing a wet etching process for the upper layer and a plasma etching for the lower layer when the upper layer is formed to a control gate and the lower layer is formed to a floating gate.
CONSTITUTION: A SiO2 film 2 is coated on a p-type silicon substrate 1, not doped polycrystalline silicon layer 3 is grown thereon, and not doped polycrystalline silicon layer 5 is further accumulated again through a SiO2 film 4 thereon. Then, a pattern 6 of resist film is provided on the predetermined region thereon, with the pattern as a mask it is wet etched to thereby retain a control gate 15 of the layer 5 only under the pattern 6. Then, with the pattern 6 and the gate 15 as masks it is plasma etched to remove the exposed portion of the layer 3 so as to form a floating gate 13 of the layer 3 at the lower side of the gate 15.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12437378A JPS5550667A (en) | 1978-10-09 | 1978-10-09 | Method of fabricating double gate mos-type integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12437378A JPS5550667A (en) | 1978-10-09 | 1978-10-09 | Method of fabricating double gate mos-type integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5550667A true JPS5550667A (en) | 1980-04-12 |
Family
ID=14883784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12437378A Pending JPS5550667A (en) | 1978-10-09 | 1978-10-09 | Method of fabricating double gate mos-type integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5550667A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5047362A (en) * | 1988-08-11 | 1991-09-10 | Sgs-Thomson Microelectronics S.A. | Method of making large-scale EPROM memory with a checker board pattern and an improved coupling factor |
| JPH09162314A (en) * | 1995-12-12 | 1997-06-20 | Nec Corp | Non-volatile semiconductor memory device and string method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5159281A (en) * | 1974-11-20 | 1976-05-24 | Mitsubishi Electric Corp | Handotaisochino seizoho |
| JPS5259585A (en) * | 1975-10-29 | 1977-05-17 | Intel Corp | Method of producing mos polycrystalline ic |
-
1978
- 1978-10-09 JP JP12437378A patent/JPS5550667A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5159281A (en) * | 1974-11-20 | 1976-05-24 | Mitsubishi Electric Corp | Handotaisochino seizoho |
| JPS5259585A (en) * | 1975-10-29 | 1977-05-17 | Intel Corp | Method of producing mos polycrystalline ic |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5047362A (en) * | 1988-08-11 | 1991-09-10 | Sgs-Thomson Microelectronics S.A. | Method of making large-scale EPROM memory with a checker board pattern and an improved coupling factor |
| JPH09162314A (en) * | 1995-12-12 | 1997-06-20 | Nec Corp | Non-volatile semiconductor memory device and string method |
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