JPS5753964A - Multilayer wiring method - Google Patents
Multilayer wiring methodInfo
- Publication number
- JPS5753964A JPS5753964A JP12880080A JP12880080A JPS5753964A JP S5753964 A JPS5753964 A JP S5753964A JP 12880080 A JP12880080 A JP 12880080A JP 12880080 A JP12880080 A JP 12880080A JP S5753964 A JPS5753964 A JP S5753964A
- Authority
- JP
- Japan
- Prior art keywords
- film
- sio2
- resist
- sio2 film
- wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To enable to remove the stepped section on an insulating film caused by underlayer wirings as well as to prevent the breaking of wire by a method wherein damage is formed on the surface of the interlayer insulating film located between the upperlayer and the lowerlayer wirings. CONSTITUTION:An Mo wiring layer 1 and an SiO2 film 3, having the prescribed pattern, are provided on a substrate 2. The damage is given on the surface of the SiO2 film by exposing the surface to the plasma of SiF4, a resist 5 is formed on the film with the pattern reverse to the Mo 1, and the SiO2 on a certain part of the Mo only is exposed. The resist 5 is slightly superposed on the Mo 1. The SiO2 film 3 is etched approximately in the same degree as the Mo 1. As the surface of the SiO2 film 3 is damaged, it has a poor adhesive property, it is etched from the interface also and the taper angle alpha is turned to approximately 20 degrees. When the resist film 5 is removed, the SiO2 film 3 having almost flat surface appears. If an Al layer 4 is formed on the film 3, a multilayer wiring wherein no breaking of wire is generated will be obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12880080A JPS5753964A (en) | 1980-09-17 | 1980-09-17 | Multilayer wiring method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12880080A JPS5753964A (en) | 1980-09-17 | 1980-09-17 | Multilayer wiring method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5753964A true JPS5753964A (en) | 1982-03-31 |
Family
ID=14993738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12880080A Pending JPS5753964A (en) | 1980-09-17 | 1980-09-17 | Multilayer wiring method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5753964A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6221237A (en) * | 1985-07-22 | 1987-01-29 | Ulvac Corp | Table for wafer positioning |
| US6583156B1 (en) | 1998-09-04 | 2003-06-24 | Vernalis Research Limited | 4-Quinolinemethanol derivatives as purine receptor antagonists (1) |
-
1980
- 1980-09-17 JP JP12880080A patent/JPS5753964A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6221237A (en) * | 1985-07-22 | 1987-01-29 | Ulvac Corp | Table for wafer positioning |
| US6583156B1 (en) | 1998-09-04 | 2003-06-24 | Vernalis Research Limited | 4-Quinolinemethanol derivatives as purine receptor antagonists (1) |
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