JPS5617042A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5617042A
JPS5617042A JP9253279A JP9253279A JPS5617042A JP S5617042 A JPS5617042 A JP S5617042A JP 9253279 A JP9253279 A JP 9253279A JP 9253279 A JP9253279 A JP 9253279A JP S5617042 A JPS5617042 A JP S5617042A
Authority
JP
Japan
Prior art keywords
wire
psg
film
flat
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9253279A
Other languages
Japanese (ja)
Other versions
JPS6033307B2 (en
Inventor
Kazuo Tokitomo
Ryoji Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9253279A priority Critical patent/JPS6033307B2/en
Priority to DE8080302457T priority patent/DE3072040D1/en
Priority to IE150580A priority patent/IE52971B1/en
Priority to EP80302457A priority patent/EP0023146B1/en
Publication of JPS5617042A publication Critical patent/JPS5617042A/en
Publication of JPS6033307B2 publication Critical patent/JPS6033307B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent disconnection of wire in a semiconductor device by forming a flat resin coating on an interlaye insulating film, selecting a mixture ratio of C2F6 with O2 to etch both films at an equal speed to form the interlayer insulating film having flat surface, and eliminating the step of multilayer wiring structure. CONSTITUTION:A condition of equalizing both etching speeds of an interlayer insulating film PSG and a negative type resist by selecting the mixture ratio of C2F6 with O2 is determined for the film PSG and the resist. An SiO2 film 13 and an Al wire 14 are formed on an Si substrate 11 and a diffused layer 12, a PSG 15 is superimposed thickner than the Al wire, and the negative type resist 16 is laminated so that the surface may become flat. Mixture gas is flowed under predetermined conditions to plasma etch it and stop the etching when the surface of the film 15 becomes flat. When superimposing second wire 17 and PSG 18 thereon, there can be obtained a multilayer wiring architecture having no step at the wire.
JP9253279A 1979-07-23 1979-07-23 Manufacturing method of semiconductor device Expired JPS6033307B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP9253279A JPS6033307B2 (en) 1979-07-23 1979-07-23 Manufacturing method of semiconductor device
DE8080302457T DE3072040D1 (en) 1979-07-23 1980-07-21 Method of manufacturing a semiconductor device wherein first and second layers are formed
IE150580A IE52971B1 (en) 1979-07-23 1980-07-21 Method of manufacturing a semiconductor device wherein first and second layers are formed
EP80302457A EP0023146B1 (en) 1979-07-23 1980-07-21 Method of manufacturing a semiconductor device wherein first and second layers are formed

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9253279A JPS6033307B2 (en) 1979-07-23 1979-07-23 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5617042A true JPS5617042A (en) 1981-02-18
JPS6033307B2 JPS6033307B2 (en) 1985-08-02

Family

ID=14056961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9253279A Expired JPS6033307B2 (en) 1979-07-23 1979-07-23 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6033307B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182833A (en) * 1982-04-19 1983-10-25 ミテル・コ−ポレ−シヨン Method of flattening integrated circuit
JPS59114824A (en) * 1982-12-21 1984-07-03 Agency Of Ind Science & Technol Flattening method of semiconductor device
JPS60165722A (en) * 1984-01-30 1985-08-28 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Etching method
JPS6118155A (en) * 1984-07-04 1986-01-27 Mitsubishi Electric Corp Manufacture of semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182833A (en) * 1982-04-19 1983-10-25 ミテル・コ−ポレ−シヨン Method of flattening integrated circuit
JPS59114824A (en) * 1982-12-21 1984-07-03 Agency Of Ind Science & Technol Flattening method of semiconductor device
JPH0322690B2 (en) * 1982-12-21 1991-03-27 Kogyo Gijutsuin
JPS60165722A (en) * 1984-01-30 1985-08-28 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Etching method
JPH0426540B2 (en) * 1984-01-30 1992-05-07 Intaanashonaru Bijinesu Mashiinzu Corp
JPS6118155A (en) * 1984-07-04 1986-01-27 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH0426212B2 (en) * 1984-07-04 1992-05-06 Mitsubishi Electric Corp

Also Published As

Publication number Publication date
JPS6033307B2 (en) 1985-08-02

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