JPS568833A - Manufacture of projection for substrate conductor layer - Google Patents

Manufacture of projection for substrate conductor layer

Info

Publication number
JPS568833A
JPS568833A JP8374179A JP8374179A JPS568833A JP S568833 A JPS568833 A JP S568833A JP 8374179 A JP8374179 A JP 8374179A JP 8374179 A JP8374179 A JP 8374179A JP S568833 A JPS568833 A JP S568833A
Authority
JP
Japan
Prior art keywords
projection
layer
resist
carrier
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8374179A
Other languages
Japanese (ja)
Other versions
JPS5917981B2 (en
Inventor
Kazuyoshi Haniwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP54083741A priority Critical patent/JPS5917981B2/en
Publication of JPS568833A publication Critical patent/JPS568833A/en
Publication of JPS5917981B2 publication Critical patent/JPS5917981B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a stable pattern of a semiconductor element even if the resist on the surface thereof is isolated by conducting twice coating of the resist and isolating thereof when forming a projection made of a conductive layer for electrically connecting with the semiconductor element on a tape carrier. CONSTITUTION:Conductor layers 20 are coated and etched on a region of an insulating tape carrier 1 provided with conveying sprocket holes 5 at both side edges to form a connecting terminal 22 as below. That is, a conductor layer 20 made of copper foil or the like is initially coated on the respective regions of the carrier 1, resist layers 4 of predetermined pattern are formed by utilizing the protective resist layer 61 on the surface thereof and the openings of the carrier 1 on the back surface thereof, are etched to form a projection 21 only on the back surface of the layer 20. Thereafter, the layer 61 is removed, a pattern of the resist layer 31 is formed corresponding to the position of the projection 21 newly, the portion excent the terminal for connection including the projection 21 is etched, and the opening of the carrier 1 is then buried with the protective resist layer 60.
JP54083741A 1979-07-02 1979-07-02 Method for manufacturing protrusions on substrate conductor layer Expired JPS5917981B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54083741A JPS5917981B2 (en) 1979-07-02 1979-07-02 Method for manufacturing protrusions on substrate conductor layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54083741A JPS5917981B2 (en) 1979-07-02 1979-07-02 Method for manufacturing protrusions on substrate conductor layer

Publications (2)

Publication Number Publication Date
JPS568833A true JPS568833A (en) 1981-01-29
JPS5917981B2 JPS5917981B2 (en) 1984-04-24

Family

ID=13810941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54083741A Expired JPS5917981B2 (en) 1979-07-02 1979-07-02 Method for manufacturing protrusions on substrate conductor layer

Country Status (1)

Country Link
JP (1) JPS5917981B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4784972A (en) * 1984-08-18 1988-11-15 Matsushita Electric Industrial Co. Ltd. Method of joining beam leads with projections to device electrodes
JPH04277640A (en) * 1991-02-14 1992-10-02 Internatl Business Mach Corp <Ibm> Protective lower-part coating for tape- automated bonding device use

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4784972A (en) * 1984-08-18 1988-11-15 Matsushita Electric Industrial Co. Ltd. Method of joining beam leads with projections to device electrodes
JPH04277640A (en) * 1991-02-14 1992-10-02 Internatl Business Mach Corp <Ibm> Protective lower-part coating for tape- automated bonding device use
JPH06101494B2 (en) * 1991-02-14 1994-12-12 インターナショナル・ビジネス・マシーンズ・コーポレイション Protective undercoat for tape automated bonding devices

Also Published As

Publication number Publication date
JPS5917981B2 (en) 1984-04-24

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