JPS5917981B2 - Method for manufacturing protrusions on substrate conductor layer - Google Patents
Method for manufacturing protrusions on substrate conductor layerInfo
- Publication number
- JPS5917981B2 JPS5917981B2 JP54083741A JP8374179A JPS5917981B2 JP S5917981 B2 JPS5917981 B2 JP S5917981B2 JP 54083741 A JP54083741 A JP 54083741A JP 8374179 A JP8374179 A JP 8374179A JP S5917981 B2 JPS5917981 B2 JP S5917981B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- photoresist
- resist
- etching
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、半導体素子などの電子部品素子の電極と外部
基板との電気的接続を得るために使用する基板への電気
的接続用突起の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a protrusion for electrical connection to a substrate, which is used to obtain an electrical connection between an electrode of an electronic component element such as a semiconductor device and an external substrate.
従来、たとえば、第３図に示すような時計用のテープキ
ャリア基板への電気的接続用突起の製造方法としては、
第１図に示す如く、導体層２０表面にフォトレジスト３
０を塗布する第１の工程（１）と前記導体層２０裏面に
フォトレジスト４の塗布。露光、現像、食刻からなる写
真食刻をする第２の工程２と前記導体層２０の表面に露
光、現像からなるパターニングをする第３の工程（３）
と前記導体層２０の裏面に保護レジスト６０を塗布する
第４の工程（４）と前記導体層２０表面の食刻をする第
５０の工程（５）と第１の工程（１）で塗布したフォト
レジスト３０と第２の工程（２）で塗布したフォトレジ
スト４と第４の工程（４）で塗布した保護レジスト６０
を剥離する第６の工程（６）により導体層２０の裏面に
突起２１を製造していた。しかしこの工程におい５ て
は、導体層２０表面へのフォトレジスト３０塗布を第１
の工程（１）でおこなラ為、導体層２０表面のパターニ
ングまでに時間的なギャップがある為。フォトレジスト
３０の劣化、剥離があり、良好なパターン形成が困難で
あつた。又、剥離されたフ２０オトレジストが処理液・
処理装置に混入しトラブルの原因となつていた。更に工
程上導体層２０裏面のパターン形成が、従来行なわれて
いた導体層２０表面のみのパターン形成工程の途中に入
る為。従来の基板製造装置の改造が必要である。本発明
２５はかかる欠点を除去する為になされたものである。
本発明の一実施例を第３図に示すような時計用のテープ
キャリア基板の応用を例に、第２図について説明すると
（１）は、導体層２０表面に食刻保護の為の保護レジス
ト６１を塗布する第１の工程で３０ある。１はたとえば
フレキシブルなテープ状の絶縁層、２０は銅等の金属箔
からなる導体層、６１は導体層２０表面に塗布された保
護レジスト、５は基板搬送用のスプロケットホールであ
る。Conventionally, for example, as a method of manufacturing a protrusion for electrical connection to a watch tape carrier board as shown in FIG.
As shown in FIG. 1, a photoresist 3 is applied to the surface of the conductor layer 20.
The first step (1) is to apply a photoresist 4 to the back surface of the conductor layer 20. A second step 2 of photo-etching consisting of exposure, development, and etching; and a third step (3) of patterning the surface of the conductor layer 20, consisting of exposure and development.
and a fourth step (4) of applying a protective resist 60 to the back surface of the conductor layer 20, a fiftieth step (5) of etching the surface of the conductor layer 20, and a first step (1). Photoresist 30, photoresist 4 applied in the second step (2), and protective resist 60 applied in the fourth step (4)
The protrusions 21 were produced on the back surface of the conductor layer 20 by the sixth step (6) of peeling off the conductor layer 20. However, in this step 5, the photoresist 30 is applied to the surface of the conductor layer 20 first.
This is because there is a time gap until the patterning of the surface of the conductor layer 20 is carried out in step (1). The photoresist 30 deteriorated and peeled off, making it difficult to form a good pattern. In addition, the peeled film 20 photoresist is treated with the processing solution.
It was getting into the processing equipment and causing trouble. Furthermore, due to the process, pattern formation on the back side of the conductor layer 20 is performed in the middle of the conventional pattern formation process only on the front side of the conductor layer 20. Requires modification of conventional board manufacturing equipment. The present invention 25 has been made to eliminate this drawback.
One embodiment of the present invention will be explained with reference to FIG. 2, taking as an example the application of a watch tape carrier substrate as shown in FIG. There are 30 in the first step of applying 61. 1 is a flexible tape-shaped insulating layer, 20 is a conductor layer made of metal foil such as copper, 61 is a protective resist coated on the surface of the conductor layer 20, and 5 is a sprocket hole for board transportation.
（２）は第１図で説明したと同様の導体層２０裏面にポ
ジ３５タイプフォトレジスト４塗布、露光、現像、食刻
からなる写真食刻をする第２の工程である。４は。(2) is a second step of photo-etching, which consists of applying a positive 35 type photoresist 4 to the back surface of the conductor layer 20, exposing it to light, developing it, and etching it, similar to that explained in FIG. 4 is.
導体層２０裏面に塗布され、写真食刻により残されたポ
ジタイプフオトレジストの突起部レジスト・パターン、
２１は６写真食刻により形成された突起である。塗布方
法は通常は第６図に示すような特殊ロールコーターによ
り行なわれる。１１は押付ローラー １２はテープキヤ
リア基板，．１３は転写ローラーである。a positive type photoresist protrusion resist pattern applied to the back surface of the conductor layer 20 and left by photolithography;
21 is a protrusion formed by 6 photo etchings. The coating method is usually carried out using a special roll coater as shown in FIG. 11 is a pressing roller, 12 is a tape carrier substrate, . 13 is a transfer roller.
送りローラー１４により矢印１９で示す送り方向に搬送
されているテープキヤリア基板１２の下面に転写ローラ
ー１３によ勺かき上げられてきたフオトレジスト３４が
転写される。しかし本発明の第１の工程（１）で塗布す
るレジストは．第２の工程（２）の食刻保護用として．
必要な為．現像液、食刻液に耐えれ、後で剥離すること
の可能なものなら何んでもよい。その為、フオトレジス
トに替わる安価な薬品を使える。又、パターニングにも
使わない為、レジスト厚が均一でなくとも良く６前記ロ
ールコーターによらなくても、第５図に示すようなスプ
レー，第７図に示すようなスキージによ勺塗布すること
ができる。９はスプレーで，窒素ガス１０によりフオト
レジスト３３が噴射される。The photoresist 34 that has been scraped up by the transfer roller 13 is transferred onto the lower surface of the tape carrier substrate 12, which is being conveyed by the feed roller 14 in the feed direction shown by the arrow 19. However, the resist applied in the first step (1) of the present invention is... For etching protection in the second step (2).
Because it is necessary. Any material may be used as long as it can withstand developer and etching solution and can be peeled off later. Therefore, cheaper chemicals can be used instead of photoresists. In addition, since it is not used for patterning, the resist thickness does not need to be uniform. 6 Instead of using the roll coater described above, it can be applied by spraying as shown in Figure 5 or with a squeegee as shown in Figure 7. I can do it. A spray 9 sprays the photoresist 33 with nitrogen gas 10.
又，１５は滴下装置６１６はスキージ．１７はテープキ
ヤリア基板である。送りローラー１８により矢印１９で
示す送り方向に搬送されているテーブキャリア基板１７
上に滴下装置１５より滴下したフオトレジスト３５が，
スキージ１６によ勺拡散し塗布される。スキージ１６の
種類としては、ナイフエツジ状ゴム１６０，多孔質ゴム
１６１６ゴムローラー１６２．エアーナイフ１６３等が
ある。１００は窒素ガスである。Further, 15 is a dropping device 616 which is a squeegee. 17 is a tape carrier board. The tape carrier substrate 17 is being transported in the feeding direction shown by the arrow 19 by the feeding roller 18
The photoresist 35 dropped from the dropping device 15 is
It is spread and applied using a squeegee 16. Types of the squeegee 16 include knife edge rubber 160, porous rubber 1616, rubber roller 162. There is an air knife 163, etc. 100 is nitrogen gas.
導体層２０裏面へのポジタイプフオトレジスト４塗布は
第５図に示すようなスプレーを基板に対しほぼ垂直に取
付け、噴射には窒素ガスを用い，圧力０．５〜１．５ｋ
ｇ／ＣＬ塗布時間０．３〜１．０秒で行なつている。こ
の場合レジスト粘度は５０ｃｐ以下が望ましい。露光は
１／１プロジエクシヨン露光法によｆ！）１現像は希釈
アルカリ溶液を用い数分間デイツピングさせて行なつて
いる。食刻は３０〜７０℃に加熱した化学研摩液或いは
塩化第２鉄液の入つた槽を用い．デイツピングにより行
なう。シヤワ一によ勺食刻を行なつた場合は６食刻量の
コントロールが難かしく．導体層２０を半分程度均一に
食刻するということが困難である。又６できあがつた突
起２１を第４図の如く電気部品素子の電極との間で位置
出しをし熱圧着する場合，突起２１部の形状がサイドエ
ツヂにより先細となつている方が位置が出しやすい為、
デイツピングによりサイドエツジを多くするようにして
いる。第２図（３）は、第１の工程（１）で塗布した導
体層２０表面の保護レジスト６１と第２の工程（２）で
塗布した導体層２０裏面のポジタイプフオトレジスト４
を剥離する第３の工程である。（４）は導体層２０表面
にポジタイプフオトレジスト３０塗布、露光６現像から
なるパターニングをする第４の工程である。ポジタイプ
フオトレジスト３０塗布から現像までが連続処理される
為前記レジスト３０の劣化、剥離の問題がなく良好な回
路レジストパターン３１を得ることができの。前記レジ
スト３０は、第６図に示すようなロールコーターにより
塗布する。又、露光、現像は第２の工程（２）で説明し
たのと同様の露光．現像方法によ勺行なう。（５）は．
次の工程（６）で導体層２０裏面が食刻されない為の保
護レジスト６０のコーテイングの第５の工程である。保
護レジストとしては．ポジタイプフオトレジスト，エツ
チングレジスト等を用いる。塗布方法は、第７図に示す
ようなスキージ方法６第５図に示すようなスプレー方法
等による。第２図（６）は、導体層２０表面の食刻をす
る第６の工程である。食刻液は、３０〜７０℃位に加熱
した塩化第２鉄液を用い，スプレーを用いたシャワ一槽
によ勺行なう。第３図（１）に示すような表面パターン
形成では、食刻量が多い上、食刻スピードを速める為、
又、サイドエツヂを少なくする為にシヤワ一により行な
う。（７）は，第４，５工程で塗布されたポジタイプフ
オトレジスト、保護レジストの剥離を行なう第７の工程
である。以上の工程により作られた電気的接続用突起の
ついた接続用端子の形成されたテープキヤリアに図示し
ないＡｕメツキ等の所定工程を加え６第４図に示す如く
．半導体素子の電極との間で位置出しをし、熱圧着をす
れば、半導体素子と外部基板との電気的接続ができる。To apply the positive type photoresist 4 to the back surface of the conductor layer 20, attach a sprayer as shown in FIG.
g/CL coating time is 0.3 to 1.0 seconds. In this case, the resist viscosity is preferably 50 cp or less. Exposure was done using the 1/1 projection exposure method. )1 Development is carried out by dipping for several minutes using a dilute alkaline solution. For etching, a bath containing a chemical polishing solution or ferric chloride solution heated to 30-70°C is used. This is done by date ping. If you carve the grains one by one, it will be difficult to control the amount of grains to be chopped. It is difficult to uniformly etch about half of the conductor layer 20. In addition, when positioning the protrusion 21 that has been completed in 6 between the electrode of the electrical component element and thermocompression bonding as shown in Fig. 4, the position will be better if the protrusion 21 has a tapered shape due to the side edges. Because it is easy,
I try to increase the side edge by day pinging. FIG. 2 (3) shows a protective resist 61 on the surface of the conductor layer 20 coated in the first step (1) and a positive type photoresist 4 on the back surface of the conductor layer 20 coated in the second step (2).
This is the third step of peeling off. (4) is a fourth step of patterning the surface of the conductor layer 20 by applying a positive type photoresist 30, exposing and developing. Since the process from coating to developing the positive type photoresist 30 is carried out continuously, there is no problem of deterioration or peeling of the resist 30, and a good circuit resist pattern 31 can be obtained. The resist 30 is applied using a roll coater as shown in FIG. Further, exposure and development were carried out in the same manner as explained in the second step (2). Depends on the developing method. (5) is.
This is the fifth step of coating the protective resist 60 to prevent the back surface of the conductor layer 20 from being etched in the next step (6). As a protection resist. Use positive type photoresist, etching resist, etc. The coating method includes a squeegee method as shown in FIG. 7, a spray method as shown in FIG. 5, and the like. FIG. 2(6) shows the sixth step of etching the surface of the conductor layer 20. The etching solution is a ferric chloride solution heated to about 30 to 70 DEG C., and is applied in a shower bath using a sprayer. In surface pattern formation as shown in FIG. 3 (1), in addition to the large amount of etching, in order to increase the etching speed,
Also, in order to reduce side edges, use a single sheer. (7) is a seventh step in which the positive type photoresist and protective resist applied in the fourth and fifth steps are removed. A predetermined process such as Au plating (not shown) is applied to the tape carrier on which connection terminals with electrical connection protrusions have been formed through the above steps, as shown in FIG. 4. By positioning it with the electrode of the semiconductor element and performing thermocompression bonding, the semiconductor element and the external substrate can be electrically connected.
このような工程によりテーブキヤリア基板へ電気的接続
用突起を形成することによｌ！）．．表面フオトレジス
トの剥離、劣化がなくなｌ）１パターン歩留ま勺が向上
する。By forming electrical connection protrusions on the table carrier substrate through such a process, l! ). ．． There is no peeling or deterioration of the surface photoresist, and l) one-pattern yield is improved.
又．−処理液．処理装置の維持管理の手間が省ける。更
に、本発明の第４〜第７の工程は、従来の導体層表面の
みのパターン形成工程である為，導体層裏面のパターン
形成工程の第１〜第３の工程の装置を追加する形ででき
る為．従来の装置を改造する必要がない。以上の説明に
おいては、電子部品素子として．半導体素子について説
明したが、能動素子ばか９でなく、抵抗、コンデンサ等
の受動素子に応用することもできる。or. - Processing liquid. The effort of maintaining and managing the processing equipment can be saved. Furthermore, since the fourth to seventh steps of the present invention are conventional pattern forming steps only on the surface of the conductor layer, it is necessary to add equipment for the first to third steps of the pattern forming step on the back surface of the conductor layer. Because I can. There is no need to modify conventional equipment. In the above explanation, the electronic component element is used. Although the semiconductor device has been described, the present invention can be applied not only to active devices but also to passive devices such as resistors and capacitors.
又，時計用のテープキヤリア基板への製造方法として説
明したが，電卓，カメラ等で使つているプリント基板等
に応用することもできる。又．導体層裏面へのポジタイ
プフオトレジストの塗布方法としてスプレーを用いて行
なつたと説明したが．第６図に示すようなロールコータ
ー，第７図に示すようなスキージ方法等によジ行なうこ
ともできる。又．スプレーを用いて塗布する場合の条件
として、角度、窒素圧力．塗布時間．レジスト粘度につ
いて説明したが．これは使用レジストの種類によ勺異な
るものであＶ）．．この条件に限定されるものではない
。又，裏面の食刻を導体層厚みの半分程度すると説明し
たが、これは、導体層厚み、相手の部品等により異なる
ものであＶ）．この食刻量に限定されるものでぱない。
以上の如く、本発明によれば、導体層表面へのレジスト
塗布を２度行ない，剥離を２度行なうことによ！）．工
数的には増加するが、表面フオトレジストが剥離されて
も問題にならず安定した良好なパターン形成ができ歩留
りが向上する。又、処理液の劣化もなくなシ、処理装置
のトラブルもなくなｖ安定稼働ができる。更に、従来の
テープキャリア基板製造装置に改造を加えることなく使
用できる為．装置を止めたＶ），．改造に要す費用を削
減することができる。Furthermore, although the method has been described as a manufacturing method for tape carrier boards for watches, it can also be applied to printed circuit boards used in calculators, cameras, etc. or. It was explained that spraying was used to apply the positive type photoresist to the back side of the conductor layer. The coating can also be carried out using a roll coater as shown in FIG. 6, a squeegee method as shown in FIG. 7, or the like. or. When applying using a spray, the conditions include angle, nitrogen pressure, etc. Application time. I explained about resist viscosity. This varies depending on the type of resist used.V). ．． It is not limited to this condition. Also, it was explained that the etching on the back side is about half the thickness of the conductor layer, but this varies depending on the thickness of the conductor layer, the mating component, etc.V). It is not limited to this amount of chopped food.
As described above, according to the present invention, the resist is applied to the surface of the conductor layer twice and the resist is peeled off twice! ). Although the number of man-hours increases, peeling of the surface photoresist does not pose a problem, and stable and good pattern formation can be achieved, resulting in an improvement in yield. In addition, there is no deterioration of the processing liquid, and there is no trouble with the processing equipment, allowing stable operation. Furthermore, it can be used without modification to conventional tape carrier substrate manufacturing equipment. The device was stopped V), . The cost required for remodeling can be reduced.
第１図は、従来のテープキヤリア基板への電気的接続用
突起製造方法を示す工程図。
第２図は本発明による突起製造方法の一実施例を示す工
程図。第３図は６本発明の応用の一実施例を示す時計用
テープキヤリア基板の説明図で．（１）は表面図，（２
）は裏面図。第４図は、本発明によ勺形成された突起と
半導体素子の圧着状態説明図。第５図は本発明で裏面フ
オトレジスト塗布に使用したスプレーの説明図。第６図
は，ロールコーター概念図。第７図は、裏面フオトレジ
スト塗布方法の他の実施例の説明図である。１・・・・
・・絶縁層．２０・・・・・・導体層．２１・・・・・
・突起、２２・・・・・・接続用端子、３０・・・・・
・フオトレジスト、４，３１・・・・・・フオトレジス
トパターン． ５・・・・・・スプロケツトホール、６
０，６１・・・・・・保護レジスト、７・・・・・・導
体層素子の電極６８・・・・・・半導体素子。FIG. 1 is a process diagram showing a conventional method for manufacturing electrical connection protrusions on a tape carrier substrate. FIG. 2 is a process diagram showing an embodiment of the protrusion manufacturing method according to the present invention. Figure 3 is an explanatory diagram of a watch tape carrier board showing one embodiment of the application of the present invention. (1) is a surface view, (2
) is the back view. FIG. 4 is an explanatory diagram of a state in which a protrusion formed by the present invention and a semiconductor element are pressed together. FIG. 5 is an explanatory diagram of the spray used for coating the backside photoresist in the present invention. Figure 6 is a conceptual diagram of a roll coater. FIG. 7 is an explanatory diagram of another embodiment of the backside photoresist coating method. 1...
...Insulating layer. 20... Conductor layer. 21...
・Protrusion, 22... Connection terminal, 30...
・Photoresist, 4, 31... Photoresist pattern. 5... Sprocket hole, 6
0, 61... Protective resist, 7... Electrode 68 of conductor layer element... Semiconductor element.
Claims (1)
れた絶縁層と前記開孔部を覆うように前記絶縁層上に被
着された銅等の金属箔からなる導体層とを具備して電子
部品素子と外部基板との電気的接続を行なう基板におい
て、前記導体層の前記電子部品素子の電極と接続される
部分への突起製造方法として、前記導体層表面に保護レ
ジスト塗布をする第１の工程と前記導体層裏面にフォト
レジスト塗布、露光、現像、食刻からなる写真食刻をす
る第２の工程と、前記導体層表・裏面のレジストを剥離
する第３の工程と前記導体層表面にフォトレジスト塗布
、露光、現像からなるパターニングをする第４の工程と
前記導体層の裏面に保護レジストを塗布する第５の工程
と前記導体層の表面の食刻をする第６の工程と前記導体
層の表・裏面のフォトレジスト及び保護レジストを剥離
する第７の工程を有することを特徴とする基板導体層へ
の突起製造方法。1. An insulating layer made of a resin material having an opening into which an electronic component element can be inserted, and a conductive layer made of a metal foil such as copper deposited on the insulating layer so as to cover the opening. In a substrate for making an electrical connection between an electronic component element and an external substrate, a method for manufacturing a protrusion on a portion of the conductor layer to be connected to an electrode of the electronic component element includes a step of coating a surface of the conductor layer with a protective resist. 1 step, a second step of photo-etching consisting of photoresist coating, exposure, development, and etching on the back side of the conductor layer; a third step of peeling off the resist on the front and back sides of the conductor layer; and a third step of removing the resist on the front and back sides of the conductor layer. A fourth step of patterning the surface of the layer by applying a photoresist, exposure, and development; a fifth step of applying a protective resist to the back surface of the conductor layer; and a sixth step of etching the surface of the conductor layer. and a seventh step of peeling off the photoresist and protective resist on the front and back surfaces of the conductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54083741A JPS5917981B2 (en) | 1979-07-02 | 1979-07-02 | Method for manufacturing protrusions on substrate conductor layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54083741A JPS5917981B2 (en) | 1979-07-02 | 1979-07-02 | Method for manufacturing protrusions on substrate conductor layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS568833A JPS568833A (en) | 1981-01-29 |
| JPS5917981B2 true JPS5917981B2 (en) | 1984-04-24 |
Family
ID=13810941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54083741A Expired JPS5917981B2 (en) | 1979-07-02 | 1979-07-02 | Method for manufacturing protrusions on substrate conductor layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5917981B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6149432A (en) * | 1984-08-18 | 1986-03-11 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH06101494B2 (en) * | 1991-02-14 | 1994-12-12 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Protective undercoat for tape automated bonding devices |
-
1979
- 1979-07-02 JP JP54083741A patent/JPS5917981B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS568833A (en) | 1981-01-29 |
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