JPS628946B2 - - Google Patents
Info
- Publication number
- JPS628946B2 JPS628946B2 JP54087841A JP8784179A JPS628946B2 JP S628946 B2 JPS628946 B2 JP S628946B2 JP 54087841 A JP54087841 A JP 54087841A JP 8784179 A JP8784179 A JP 8784179A JP S628946 B2 JPS628946 B2 JP S628946B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- etching
- resist
- photoresist
- printing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 20
- 238000007639 printing Methods 0.000 claims description 14
- 230000001681 protective effect Effects 0.000 claims description 8
- 238000011161 development Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 239000011888 foil Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 22
- 239000000758 substrate Substances 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 9
- 238000012546 transfer Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000000576 coating method Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 241000238413 Octopus Species 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Description
【発明の詳細な説明】
本発明は、半導体素子などの電子部品素子の電
極と外部基板との電気的接続を得るために使用す
る基板への電気的接続用突起の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a protrusion for electrical connection to a substrate, which is used to obtain an electrical connection between an electrode of an electronic component element such as a semiconductor device and an external substrate.
従来、たとえば第３図に示すような時計用のテ
ープキヤリア基板への電気的接続用突起の製造方
法としては、第１図に示す如く、導体層２０表面
にフオトレジスト３０塗布をする第１の工程(1)と
前記導体層２０裏面にフオトレジスト４塗布、露
光、現像、食刻からなる写真食刻をする第２の工
程(2)と前記導体層２０の表面に露光、現像からな
るパターニングをする第３の工程(3)と前記導体層
２０の裏面に保護レジスト６０を塗布する第４の
工程(4)と前記導体層２０表面の食刻をする第５の
工程(5)と第１の工程(1)で塗布したフオトレジスト
３０と第２の工程(2)で塗布したフオトレジスト４
と第４の工程(4)で塗布した保護レジスト６０を剥
離する第６の工程(6)により導体層２０の裏面に突
起２１を製造していた。しかしこの工程において
は、導体層２０裏面処理工程で、レジストにフオ
トレジストを使う為、露光、現像からなるパター
ニングが必要であり、現像までやらないとパター
ンの良否判定ができない。又、導体層２０表面と
裏面について２度現像処理をする為、現像液の劣
化が早まり、液の維持管理に要する工数が増え
る。更に、導体層２０表面の食刻を１度にやる
為、食刻量が多く、食刻時間を多く要す。更に、
導体層２０表面に塗布するフオトレジスト３０と
裏面に塗布するフオトレジスト４は塗布方法が異
なる為、粘度を変えねばならない。更に、フオト
レジストを導体層２０表、裏面の両面に塗布する
為、多量のレジストを必要としコストアツプにな
る。更に、導体層２０表面へのフオトレジスト３
０塗布を第１の工程でやる為、導体層２０裏面の
処理工程中に前記レジスト３０が劣化したり剥離
することがある。更に、フオトレジストは、特殊
光下でないと使用できず、専用の暗室を必要とす
る。本発明はかかる欠点を除去する為になされた
ものである。 Conventionally, as shown in FIG. 3, for example, a method for manufacturing an electrical connection protrusion on a watch tape carrier substrate includes a first method of coating a photoresist 30 on the surface of a conductor layer 20, as shown in FIG. Step (1) and photo-etching consisting of applying a photoresist 4 on the back surface of the conductor layer 20, exposing it to light, developing it, and etching it; and patterning the surface of the conductor layer 20 consisting of exposing it to light and developing it. a third step (3) of applying a protective resist 60 to the back surface of the conductor layer 20; a fifth step (5) of etching the surface of the conductor layer 20; Photoresist 30 applied in step 1 (1) and photoresist 4 applied in step 2 (2)
Then, in a sixth step (6) of peeling off the protective resist 60 applied in the fourth step (4), protrusions 21 were manufactured on the back surface of the conductor layer 20. However, in this process, since a photoresist is used as a resist in the process of treating the back surface of the conductor layer 20, patterning consisting of exposure and development is required, and the quality of the pattern cannot be determined unless development is performed. Furthermore, since the front and back surfaces of the conductor layer 20 are developed twice, the developer deteriorates more quickly and the number of man-hours required to maintain and manage the solution increases. Furthermore, since the surface of the conductor layer 20 is etched at one time, the amount of etching is large and a long etching time is required. Furthermore,
The photoresist 30 applied to the front surface of the conductor layer 20 and the photoresist 4 applied to the back surface have different coating methods, so their viscosity must be changed. Furthermore, since photoresist is applied to both the front and back surfaces of the conductor layer 20, a large amount of resist is required, which increases costs. Furthermore, a photoresist 3 is applied to the surface of the conductor layer 20.
Since zero coating is performed in the first step, the resist 30 may deteriorate or peel off during the processing step for the back surface of the conductor layer 20. Furthermore, photoresists can only be used under special light and require a dedicated darkroom. The present invention has been made to eliminate such drawbacks.
本発明の一実施例を第３図に示すような時計用
のテープキヤリア基板への応用を例に、第２図に
ついて説明すると、(1)は、導体層２０裏面にエツ
チングレジスト４４を印刷する第１の工程であ
る。１はたとえばフレキシブルな樹脂材からなる
絶縁層、２０は銅等の金属箔からなる導体層、５
は搬送の為のスプロケツトホール、４４は突起パ
ターンに印刷されたエツチングレジストである。
印刷は第５図に示すようなタコ印刷機により行な
う。９は、テープキヤリア基板１１セツト用案内
板、１１は、テープキヤリア基板、１５は印刷原
版、１６は図示してない左右動力、１７は球凸面
状転写ゴム、１８は図示してない上下動力、４２
はエツチングレジスト、４３は印刷原版１５に掘
り込まれた突起パターンである。印刷原版１５上
にエツチングレジスト４２をおき、ナイフ状のブ
レードでスキージし、突起パターン４３に前記レ
ジスト４２を充填する。次に転写ゴム１７を動力
１８により下げ突起パターンの前記レジスト４２
を転写ゴム１７に転写する。そして動力１６によ
り転写ゴム１７を１７′の位置に移動し、動力１
８により押し下げ、テープキヤリア基板１１に再
転写する。(2)は、導体層２０表面にポジタイプフ
オトレジスト３０を塗布する第２の工程である。
３０はポジタイプフオトレジストである。塗布は
数ミクロンの厚まで均一に塗布されなければなら
ない為、第６図に示すようなロールコータにより
行なつている。３２はポジタイプフオトレジス
ト、２５は転写ローラー、２６は押付ローラー、
１２はテープキヤリア基板、２７は搬送ローラ
ー、２８は前記基板１２の送り方向を示す矢印で
ある。搬送ローラー２７により、矢印２８の方向
に送られている前記基板１２の下面に、転写ロー
ラー２５によりかき上げられたポジタイプフオト
レジスト３２が転写される。前記レジスト３２の
塗布厚は、転写ローラー２５と押付ローラー２６
の間隙を調整して行なう。(3)は、導体層２０表面
に露光、現像からなるパターニングをする第３の
工程である。露光は１／１プロジエクシヨン露光
法により、回路パターンの露光を行なう。又、現
像は、所定現像液の入つたデイツピング槽に、テ
ープキヤリア基板を浸漬して行なう。３１は、第
３の工程で形成された回路レジストパターンであ
る。(4)は、導体層２０表面、裏面の約半分を同時
に食刻する第４の工程である。片面10ミクロン程
度で、導体層２０を10数ミクロン残した状態まで
食刻する。食刻は、30〜70℃位に加熱した化学研
摩液或いは塩化第２鉄液の入つた槽を用い、デイ
ツピングにより行なう。シヤワーで食刻した場合
は、食刻量のコントロールがむずかしく、導体層
２０を半分程度均一に食刻するということが困難
である。又、できあがつた突起２１を第４図に示
す如く、半導体素子８の電極７との間で位置出し
をし熱圧着する場合、突起２１部の形状がサイド
エツヂにより先細となつている方が都合がよい
為、デイツピングによりサイドエツヂを多くする
ようにしている。(5)は、次の工程(6)で導体層２０
裏面が食刻されない為の保護レジスト６０の塗布
をする第５の工程である。保護レジスト６０とし
ては、ポジタイプフオトレジスト、エツチングレ
ジスト等を用い、塗布方法は、スキージ、スプレ
ー等による。(6)は、導体層２０表面の食刻をする
第６の工程である。食刻液は、30〜70℃位に加熱
した塩化第２鉄液を用い、スプレーを用いたシヤ
ワー槽により行なう。第４の工程で、半分程度の
食刻をしている為、第６の工程では従来の1/2程
度の食刻時間で済む。(7)は、第１、２、５工程で
印刷或いは塗布されたエツチングレジスト４４、
ポジタイプフオトレジスト３０及び保護レジスト
６０を剥離する第７の工程である。 One embodiment of the present invention will be explained with reference to FIG. 2, taking as an example the application of the present invention to a tape carrier board for a watch as shown in FIG. This is the first step. 1 is an insulating layer made of a flexible resin material, 20 is a conductor layer made of metal foil such as copper, and 5
44 is a sprocket hole for conveyance, and an etching resist printed with a protrusion pattern.
Printing is performed using an octopus printing machine as shown in FIG. 9 is a guide plate for setting the tape carrier substrate 11, 11 is a tape carrier substrate, 15 is a printing original plate, 16 is a horizontal power not shown, 17 is a spherical convex transfer rubber, 18 is a vertical power not shown, 42
43 is an etching resist, and 43 is a protrusion pattern etched into the original printing plate 15. An etching resist 42 is placed on the printing original plate 15, and is squeegeeed with a knife-like blade to fill the protrusion pattern 43 with the resist 42. Next, the transfer rubber 17 is lowered by the power 18 and the resist 42 of the projection pattern is lowered.
is transferred onto the transfer rubber 17. Then, the transfer rubber 17 is moved to the position 17' by the power 16, and the power 16 is moved to the position 17'.
8 to retransfer onto the tape carrier substrate 11. (2) is a second step of applying a positive type photoresist 30 to the surface of the conductor layer 20.
30 is a positive type photoresist. Since the coating must be uniform to a thickness of several microns, it is carried out using a roll coater as shown in FIG. 32 is a positive type photoresist, 25 is a transfer roller, 26 is a pressing roller,
12 is a tape carrier substrate, 27 is a conveyance roller, and 28 is an arrow indicating the feeding direction of the substrate 12. The positive type photoresist 32 scraped up by the transfer roller 25 is transferred by the transport roller 27 onto the lower surface of the substrate 12 that is being fed in the direction of the arrow 28 . The coating thickness of the resist 32 is determined by the thickness of the transfer roller 25 and the pressing roller 26.
Adjust the gap. (3) is the third step of patterning the surface of the conductor layer 20 by exposure and development. Exposure of the circuit pattern is performed using a 1/1 projection exposure method. Further, development is carried out by immersing the tape carrier substrate in a dipping tank containing a predetermined developing solution. 31 is a circuit resist pattern formed in the third step. (4) is a fourth step in which approximately half of the front and back surfaces of the conductor layer 20 are etched at the same time. The conductor layer 20 is etched by about 10 microns on one side, leaving about 10 microns of the conductor layer 20. Etching is carried out by dipping using a bath containing a chemical polishing solution or ferric chloride solution heated to about 30 to 70°C. When etching is performed using a shower, it is difficult to control the amount of etching, and it is difficult to uniformly etch about half of the conductor layer 20. Furthermore, when the completed protrusion 21 is positioned between the electrode 7 of the semiconductor element 8 and bonded by thermocompression, as shown in FIG. Because it is convenient, I try to increase the side edge by day ping. (5) is the conductor layer 20 in the next step (6).
The fifth step is to apply a protective resist 60 to prevent the back surface from being etched. As the protective resist 60, a positive type photoresist, an etching resist, or the like is used, and the application method is a squeegee, spray, or the like. (6) is the sixth step of etching the surface of the conductor layer 20. The etching solution is a ferric chloride solution heated to about 30 to 70°C, and is carried out in a shower tank using a spray. In the fourth step, about half of the etching is done, so the sixth step takes about half the etching time of the conventional method. (7) is the etching resist 44 printed or applied in the first, second, and fifth steps;
This is a seventh step in which the positive type photoresist 30 and the protective resist 60 are removed.
以上の工程により作られた電気的接続用突起の
ついた接続用端子２２の形成されたテープキヤリ
ア基板に図示してないAuメツキ等の所定工程を
加え、第４図に示す如く、半導体素子の電極との
間で位置出しをし、熱圧着をすれば、半導体素子
と外部基板との電気的接続ができる。 A predetermined process such as Au plating (not shown) is added to the tape carrier substrate on which the connection terminals 22 with the electrical connection protrusions formed by the above process are applied, and as shown in FIG. 4, a semiconductor element is formed. By positioning the semiconductor element and the electrode and performing thermocompression bonding, electrical connection between the semiconductor element and the external substrate can be established.
以上の説明においては、電子部品素子として半
導体素子について説明したが、能動素子ばかりで
なく、抵抗、コンデンサ等の受動素子に応用する
こともできる。又、時計用のテープキヤリア基板
への製造方法として説明したが、電卓、カメラ等
で使つているプリント基板等に応用することもで
きる。又、導体層裏面の印刷にエツチングレジス
トを使うと説明したが、現像液、食刻液に浸され
ず、最終工程で剥離できるものであれば、他のレ
ジストでもかまわない。又、前述の印刷にタコ印
刷機を用いると説明したが、スクリーン印刷等を
用してもよく、この方法に限定されるものではな
い。又、導体層表面のフオトレジスト塗布にロー
ルコーターを使用すると説明したが、スプレー、
スキージ等で塗布してもよい。又、導体層表面、
裏面の同時食刻において、食刻量について説明し
てあるが、これは、導体層厚み、相手の部品等に
より異なるものであり、この食刻量に限定される
ものではない。 In the above description, a semiconductor element has been described as an electronic component element, but the present invention can be applied not only to active elements but also to passive elements such as resistors and capacitors. Further, although the method has been described as a manufacturing method for a tape carrier board for a watch, it can also be applied to printed circuit boards used in calculators, cameras, etc. Further, although it has been explained that an etching resist is used for printing on the back side of the conductor layer, other resists may be used as long as they are not immersed in developer or etching solution and can be peeled off in the final process. Further, although it has been explained that a tacho printing machine is used for the printing described above, screen printing or the like may also be used, and the method is not limited to this method. Also, although it was explained that a roll coater is used to apply the photoresist on the surface of the conductor layer, spraying,
It may also be applied with a squeegee or the like. In addition, the surface of the conductor layer,
In the simultaneous etching of the back surface, the amount of etching has been described, but this varies depending on the thickness of the conductor layer, the mating component, etc., and is not limited to this amount.
以上の如く、本発明によれば、裏面処理用のレ
ジストを印刷技術を用いてパターニングすること
により、裏面の露光、現像処理が不要となり、工
数ダウンとなる。又、パターンの良否がすぐ判定
できるため、治具等の位置出し等の工数が減る。
更に、現像処理が一度で済む為、現像液の寿命も
伸び、液の維持管理の手間が省ける。更に第５の
工程の導体層表面の食刻において食刻量が従来の
1/2程度で済む為、食刻時間が短縮され工数の減
少ができる。更に、フオトレジスト塗布が表面だ
けでよい為、一種類のフオトレジストだけでよ
く、且つ量も従来の1/2でよい為、コストダウン
となる。更に、表面フオトレジスト塗布をして、
すぐにパターニングをする為、前記レジストの劣
化、剥離がなくなり、パターン歩留りが向上す
る。更に、裏面印刷用レジストは、昼光下で使用
できる部材が使える為、裏面処理工程には、専用
暗室が不要となり、設備面の合理化もできる。 As described above, according to the present invention, by patterning a resist for back side processing using printing technology, exposure and development processes on the back side are no longer necessary, resulting in a reduction in man-hours. In addition, since the quality of the pattern can be determined immediately, the number of man-hours required for positioning jigs and the like is reduced.
Furthermore, since the development process only needs to be done once, the life of the developer is extended, and the trouble of maintaining and managing the solution can be saved. Furthermore, in the fifth step of etching the surface of the conductor layer, the amount of etching is different from that of the conventional method.
Since it only takes about 1/2, the etching time is shortened and the number of man-hours can be reduced. Furthermore, since the photoresist only needs to be applied to the surface, only one type of photoresist is required, and the amount can be halved compared to conventional methods, resulting in cost reduction. Furthermore, the surface is coated with photoresist,
Since patterning is performed immediately, there is no deterioration or peeling of the resist, and the pattern yield is improved. Furthermore, since the resist for back side printing can use materials that can be used in daylight, a dedicated darkroom is not required for the back side processing process, and equipment can be rationalized.
第１図は、従来の突起製造方法を示す工程図。
第２図は、本発明による突起製造方法の一実施例
を示す工程図。第３図は、本発明の応用の一実施
例を示す時計用テープキヤリア基板の説明図で、
(1)は表面図、(2)は裏面図。第４図は、本発明によ
り形成された突起と半導体素子の圧着状態説明
図。第５図は、本発明で裏面印刷に使用したタコ
印刷機の説明図。第６図は、ロールコーター概念
図である。
１……絶縁層、２０……導体層、２１……突
起、２２……接続用端子、３０……フオトレジス
ト、３１……フオトレジストパターン、５……ス
プロケツトホール、６０……保護レジスト、７…
…半導体素子の電極、８……半導体素子、４４…
…エツチングレジストパターン、１１，１２……
テープキヤリア基板。
FIG. 1 is a process diagram showing a conventional protrusion manufacturing method.
FIG. 2 is a process diagram showing an embodiment of the protrusion manufacturing method according to the present invention. FIG. 3 is an explanatory diagram of a watch tape carrier board showing one embodiment of the application of the present invention.
(1) is the front view, (2) is the back view. FIG. 4 is an explanatory diagram of a state in which a protrusion formed according to the present invention and a semiconductor element are pressed together. FIG. 5 is an explanatory diagram of the octopus printing machine used for backside printing in the present invention. FIG. 6 is a conceptual diagram of a roll coater. DESCRIPTION OF SYMBOLS 1... Insulating layer, 20... Conductor layer, 21... Protrusion, 22... Connection terminal, 30... Photoresist, 31... Photoresist pattern, 5... Sprocket hole, 60... Protective resist, 7...
...Electrode of semiconductor element, 8...Semiconductor element, 44...
...Etching resist pattern, 11, 12...
Tape carrier board.
Claims (1)
構成された絶縁層と前記開口部を覆うように前記
絶縁層上に被着された銅等の金属箔からなる導体
層とを具備した基板における電子部品素子の電極
と接続される前記導体層への突起製造方法におい
て、前記導体層の裏面に印刷法を用い、所定パタ
ーン形状にエツチングレジストを印刷する第１の
工程と、前記導体層の表面に感光部材を塗布する
第２の工程と、前記導体層の表面に露光・現像か
らなるパターニングをする第３の工程と、前記導
体層の表、裏面を同時に前記導体層の半分程度食
刻する第４の工程と、前記導体層の裏面に保護レ
ジストを塗布する第５の工程と、前記導体層の表
面を食刻する第６の工程と、前記導体層の表、裏
面の前記エツチングレジスト、感光部材、保護レ
ジストを剥離する第７の工程とを有することを特
徴とする導体層への突起製造方法。1. In a board comprising an insulating layer made of a resin material having an opening into which an electronic component element is inserted, and a conductor layer made of metal foil such as copper deposited on the insulating layer so as to cover the opening. The method for manufacturing a protrusion on the conductor layer to be connected to an electrode of an electronic component element includes a first step of printing an etching resist in a predetermined pattern shape on the back surface of the conductor layer using a printing method, and a surface of the conductor layer. a second step of applying a photosensitive material to the surface of the conductor layer, a third step of patterning the surface of the conductor layer by exposure and development, and simultaneously etching the front and back surfaces of the conductor layer by about half of the conductor layer. a fourth step, a fifth step of applying a protective resist to the back surface of the conductor layer, a sixth step of etching the surface of the conductor layer, and the etching resist on the front and back surfaces of the conductor layer; 1. A method for manufacturing protrusions on a conductor layer, comprising a seventh step of peeling off a photosensitive member and a protective resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8784179A JPS5612743A (en) | 1979-07-11 | 1979-07-11 | Processing method of projection for conductive layer of substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8784179A JPS5612743A (en) | 1979-07-11 | 1979-07-11 | Processing method of projection for conductive layer of substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5612743A JPS5612743A (en) | 1981-02-07 |
| JPS628946B2 true JPS628946B2 (en) | 1987-02-25 |
Family
ID=13926127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8784179A Granted JPS5612743A (en) | 1979-07-11 | 1979-07-11 | Processing method of projection for conductive layer of substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5612743A (en) |
-
1979
- 1979-07-11 JP JP8784179A patent/JPS5612743A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5612743A (en) | 1981-02-07 |
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