US4536951A - Method of producing a layered structure - Google Patents

Method of producing a layered structure Download PDF

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Publication number
US4536951A
US4536951A US06/621,187 US62118784A US4536951A US 4536951 A US4536951 A US 4536951A US 62118784 A US62118784 A US 62118784A US 4536951 A US4536951 A US 4536951A
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metal layer
metal
layer
masking pattern
depositing
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US06/621,187
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Stephen J. Rhodes
Raymond E. Oakley
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Plessey Semiconductors Ltd
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Plessey Overseas Ltd
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Assigned to CANADIAN IMPERIAL BANK OF COMMERCE, AS SECURED PARTY reassignment CANADIAN IMPERIAL BANK OF COMMERCE, AS SECURED PARTY SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MITEL CORPORATION, A CORPORATION UNDER THE LAWS OF CANADA
Assigned to CANADIAN IMPERIAL BANK OF COMMERCE, AS SECURED PARTY reassignment CANADIAN IMPERIAL BANK OF COMMERCE, AS SECURED PARTY RE-RECORD TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 9445 FRAME 0299. Assignors: MITEL SEMICONDUCTOR LIMITED
Assigned to MITEL SEMICONDUCTOR, LIMITED, MITEL TELCOM LIMITED CORPORATION, MITEL SEMICONDUCTOR AMERICAS, INC., A DELAWARE CORPORATION, MITEL SEMICONDUCTOR, INC., A DELAWARE CORPORATION, MITEL, INC., A DELAWARE CORPORATION, MITEL CORPORATION reassignment MITEL SEMICONDUCTOR, LIMITED RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: CANADIAN IMPERIAL BANK OF COMMERCE
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a layered structure, which method comprises depositing a first metal layer on a substrate, depositing a barrier layer on the first metal layer, depositing a second metal layer on the barrier layer, forming a first masking pattern on the second metal layer, etching the first and second metal layers and the barrier layer in accordance with the first masking pattern, removing the first masking pattern, forming a second masking pattern on the second metal layer, etching the second metal layer in accordance with the second masking pattern, removing the second masking pattern, depositing a dielectric layer having a thickness sufficient to cover the second metal layer, etching the dielectric layer to expose the second metal layer, and depositing on the etched dielectric layer and exposed second metal layer a further metal layer to contact the exposed second metal layer.

Description

This invention relates to a method of producing a layered structure, which layered structure may be used for forming electrical interconnections in an integrated circuit.

Integrated circuits and especially one micron feature size integrated cicuits require the formation of layered structures comprising various levels of metal defining between them vias, that is, metal to metal connections.

A current method of forming vias in a two level metal scheme is to form a first metal layer, consisting of metal tracks in a dielectric material, and then to deposit a layer of dielectric over the first metal layer. Via holes are then formed in the dielectric layer where it is required to form interconnections between the metal layers. The second metal layer, also consisting of metal tracks in a dielectric material is then formed and the interconnections with the first metal layer are made through the via holes. The via holes are delineated in the dielectric layer so that, in the resulting layered structure, each via is provided with a metal surround in both metal layers. The width of the metal surround must be sufficient to ensure that, allowing for extremes of alignment tolerances and metal track dimensions, the via always lies within the metal tracks in both metal layers. This type of via is known as a nested via and it is evident that the need to provide the via surround greatly increases via pitch and hence reduces packing density in the resultant structure.

It is possible to reduce via pitch by forming non-nested vias, that is vias which are not provided with a metal surround. However, non-nested vias can give rise to defects in the resulting layered structure. As there is no metal surround the dielectric in which the metal tracks in the first metal layer are formed may be etched during the etching process used to form the via holes in the overlying dielectric layer. This produces very deep via holes in which it is difficult to deposit the second metal layer with constant thickness. Often, the second metal layer contains portions of very shallow thickness and micro-cracks, giving rise to circuit defects, can frequently occur. Furthermore, the first metal layer may become exposed during the etch process to form the metal tracks in the second metal layer. Hence, the first metal layer will also be etched, forming portions of reduced thickness in the metal tracks of the first metal layer. These portions of reduced thickness can lead to premature failure of the layered structure in use.

It is an aim of the present invention to provide a method of producing a layered structure having metal track widths and metal to metal gaps of one micron or less on both first and second metal layers, and also to provide a via within the same metal pitch.

A feature of the present invention is the method by which the interconnections between the layers of metal are formed, which method obviates the need for via holes with subsequent metal filling. In the present method a pillar of metal is formed where a via is required and an insulating layer of dielectric material is deposited around the pillars. In this way a subsequent metal layer will only connect with the pillars of metal, the subsequent metal layer being isolated from an underlying metal layer by the insulating layer of dielectric material.

According to the present invention there is provided a method of forming a layered structure, which method comprises depositing a first metal layer on a substrate, depositing a barrier layer on the first metal layer, depositing a second metal layer on the barrier layer, forming a first masking pattern on the second metal layer, etching the first and second metal layers and the barrier layer in accordance with the first masking pattern, removing the first masking pattern, forming a second masking pattern on the second metal layer, etching the second metal layer in accordance with the second masking pattern, removing the second masking pattern, depositing a dielectric layer having a thickness sufficient to cover the second metal layer, etching the dielectric layer to expose the second metal layer, and depositing on the etched dielectric layer and exposed second metal layer a further metal layer to contact the exposed second metal layer.

Layered structure having several layers of metallisation may be fabricated by repeating the above method until the further metal layer is the final metal layer in the required layered structure.

Preferably, etching of the various layers is achieved by anisotropic plasma etching. The anisotropic plasma etching used to etch the metal layers and the dielectric layers may comprise carbon tetrachloride plasma eteching.

An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings in which:

FIG. 1 illustrates a structure having first and second layers of metal sandwiching a barrier layer of etch barrier material;

FIG. 2 illustrates the structure of FIG. 1 after etching in accordance with a first masking pattern.

FIG. 3 illustrates the structure of FIG. 2 after the second metal layer has been etched in accordance with a second masking pattern;

FIG. 4 illustrates the structure of FIG. 3 after a layer of dielectric has been deposited and etched to expose the surface of the second metal layer; and

FIG. 5 illustrates a further metal layer, after etching, deposited on the structure shown in FIG. 4.

Referring to the drawings, a first metal layer 2 is deposited on a substrate 4, such as a silicon substrate. A barrier layer 6 of etch barrier material, such as chromium, is then deposited on the first metal layer 2. A second metal layer 8 is then deposited on the barrier layer 6 to give the structure shown in FIG. 1. The metal layers 2 and 8 are, preferably, 1 micron layers of aluminium. The aluminium may be pure aluminium or aluminium doped with silicon and/or copper.

A first masking pattern, not shown, is formed on the surface of the second metal layer 8. The first masking pattern delineates the interconnect pattern required in the first level metallisation in the resulting layered structure. The structure shown in FIG. 1 is then etched by anisotropic plasma etching to produce the structure shown in FIG. 2. It can be seen that the structure shown in FIG. 2 does not contain any undercuts.

The first and second metal layers 2 and 8 may be etched using carbon tetrachloride plasma etching. However, in order to etch the barrier layer 6, it is necessary to modify the plasma chemistry. This may be achieved by introducing oxygen into the plasma whilst the barrier layer 6 is etched. The plasma chemistry can then revert to carbon tetrachloride plasma to etch the underlying first metal layer 2.

A polyimide may now be spun onto the surface of the second metal layer 8 in order to achieve a planar surface. This stage of planarisation is not essential and may be omitted. The metal pillars 10, shown in FIG. 3, which form the vias in the final structure are now fabricated. This is achieved by depositing a second masking pattern on the structure shown in FIG. 2. The second masking pattern delineates the areas of the second metal layer 8 where the metal pillars 10 are required. The masking pattern, being any known photo-resist material has a rather poor image and will to some extent extend beyond the defined areas of the second metal layer 8 but will not extend between adjacent metal tracks defined in the second metal layer 8 after etching in accordance with the first masking pattern. This overlap in the masking pattern does not adversely affect the formation of the metal pillars 10 as each metal pillar 10 is defined in a portion of the second metal layer 8 which underlies the masking pattern.

The second metal layer 8 is plasma etched in accordance with the second masking pattern down to the barrier layer 6 to produce the structure shown in FIG. 3 with the metal pillars 10 extending from and accurately aligned to the metallisation pattern in the first metal layer 2. The metal pillars 10 are accurately aligned as they are partly formed during the etch used to form the metallisation pattern in the first metal layer 2.

In etching the second metal layer 8 in accordance with the second masking pattern, the effect of the barrier layer 6 is twofold. Firstly, the plasma used to etch the second metal layer 8 does not affect the barrier layer 6 and hence, the pillars 10, which form the vias in the resulting layered structure, are of controlled substantially uniform height. Secondly, the thickness of the first metal layer in the final structure can be accurately defined as the first metal layer 2 is not etched during the second etch of the second metal layer 8 because of the presence of the barrier layer 6.

A dielectric layer 12 is now deposited over the structure shown in FIG. 3 by, for example, successive spin coatings and cure operations. The dielectric layer is deposited to a thickness sufficient to encase the structure of FIG. 3 so that the pillars 10 are surrounded and covered by the material of the dielectric layer so as to provide a planar surface over the metal pillars 10. The dielectric layer 12 is, preferably, formed from a polyimide material such as that sold under the trade name PIQ by Hitachi.

The dielectric layer is then plasma etched to expose the top surfaces of the metal pillars 10. The dielectric layer 12 may be etched using carbon tetrachloride plasma and suitable means may be included in the plasma chamber to ensure that the etch process is terminated as soon as the surfaces of the metal pillars 10 are exposed. The resulting structure is shown in FIG. 4 and the exposed surfaces of the metal pillars 10 form the connections to the next metal layer.

A further metal layer 14 is then deposited on the structure shown in FIG. 4. The metal layer 14 will contact the surfaces of the pillars 10 exposed in the dielectric layer 12. It will now be seen that the metal pillars 10, consisting of the remaining portions of the second metal layer 8, form the metal to metal connections between the first metal layer 2 and the metal layer 14, that is, the pillars 10 form the vias between the metal layers 2 and 14.

If only two level metallisation is required in the layered structure, the further metal layer 14 will be the final metal layer of the structure.

A final masking pattern may be formed on the metal layer 14 and the metal layer 14 may be etched in accordance with the final masking pattern to remove unwanted metal from the field regions in the second level metallisation.

If more than two level metallisation is required a barrier layer and a subsequent metal layer, similar to the barrier layer 6 and second metal layer 8, may be deposited on the further metal layer 14. The sequence of operations can then be repeated until the desired multi-level metallisation structure is formed, the final metal layer being etched to remove unwanted metal in the field regions as described above for the further metal layer 14 in connection with a two level metallisation structure.

As the method of the present invention provides vias, in the form of the metal pillars 10, which are aligned accurately to the metallisation in the first metal layer 2, maximum via size in the minimum space available is achieved.

It is to be appreciated that the embodiment of the present invention described above with reference to the accompanying drawings has been given by way of example only and that modifications can be effected. Thus, for example, materials other than aluminium may be used for the metal layers and one such material is tungsten. Similarly, although the etch barrier material has been described as chromium, other materials, such as titanium may be employed.

Claims (10)

We claim:
1. A method of forming a layered structure, which method comprises depositing a first metal layer on a substrate, depositing a barrier layer on the first metal layer, depositing a second metal layer on the barrier layer, forming a first masking pattern on the second metal layer, etching the first and second metal layers and the barrier layer in accordance with the first masking pattern, removing the first masking pattern, forming a second masking pattern on the second metal layer, etching the second metal layer in accordance with the second masking pattern, removing the second masking pattern, depositing a dielectric layer having a thickness sufficient to cover the second metal layer, etching the dielectric layer to expose the second metal layer, and depositing on the etched dielectric layer and exposed second metal layer a further metal layer to contact the exposed second metal layer.
2. A method according to claim 1 wherein the method is selectively repeated until the further metal layer comprises the final metal layer of the layered structure.
3. A method according to claim 1 wherein the further metal layer comprises the final metal layer of the layered structure.
4. A method according to claim 2 wherein a final masking pattern is formed on the final metal layer and the final metal layer is etched in accordance with the final masking pattern to remove unwanted metal therefrom.
5. A method according to claim 4 wherein the layers are etched by anisotropic plasma etching.
6. A method according to claim 5 wherein the metal layers are etched by carbon tetrachloride plasma etching.
7. A method according to claim 5 wherein the barrier layer is etched by carbon tetrachloride and oxygen plasma etching.
8. A method according to claim 4 wherein the metal layers comprise aluminium.
9. A method according to claim 4 wherein the dielectric comprises polyimide.
10. A method according to claim 4 wherein the barrier layer comprises chromium.
US06/621,187 1983-06-16 1984-06-15 Method of producing a layered structure Expired - Lifetime US4536951A (en)

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GB838316476A GB8316476D0 (en) 1983-06-16 1983-06-16 Producing layered structure
GB8316476 1983-06-16

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EP (1) EP0129389B1 (en)
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Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698125A (en) * 1983-06-16 1987-10-06 Plessey Overseas Limited Method of producing a layered structure
US4718977A (en) * 1984-12-20 1988-01-12 Sgs Microelettronica S.P.A. Process for forming semiconductor device having multi-thickness metallization
US4914056A (en) * 1985-05-13 1990-04-03 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device having tapered pillars
US4926236A (en) * 1986-02-12 1990-05-15 General Electric Company Multilayer interconnect and method of forming same
US4933045A (en) * 1989-06-02 1990-06-12 International Business Machines Corporation Thin film multilayer laminate interconnection board assembly method
US4954423A (en) * 1985-08-06 1990-09-04 Texas Instruments Incorporated Planar metal interconnection for a VLSI device
US4973562A (en) * 1987-05-01 1990-11-27 U.S. Philips Corporation Method of manufacturing a semiconductor device having interconnections located both above a semiconductor region and above an isolation region adjoining it
US5043295A (en) * 1987-09-09 1991-08-27 Ruggerio Paul A Method of forming an IC chip with self-aligned thin film resistors
US5132775A (en) * 1987-12-11 1992-07-21 Texas Instruments Incorporated Methods for and products having self-aligned conductive pillars on interconnects
US5340775A (en) * 1992-12-15 1994-08-23 International Business Machines Corporation Structure and fabrication of SiCr microfuses
US5385867A (en) * 1993-03-26 1995-01-31 Matsushita Electric Industrial Co., Ltd. Method for forming a multi-layer metallic wiring structure
US5391921A (en) * 1989-04-21 1995-02-21 Nec Corporation Semiconductor device having multi-level wiring
US5512514A (en) * 1994-11-08 1996-04-30 Spider Systems, Inc. Self-aligned via and contact interconnect manufacturing method
US5539255A (en) * 1995-09-07 1996-07-23 International Business Machines Corporation Semiconductor structure having self-aligned interconnection metallization formed from a single layer of metal
US5593919A (en) * 1995-09-05 1997-01-14 Motorola Inc. Process for forming a semiconductor device including conductive members
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5665642A (en) * 1993-04-30 1997-09-09 Sony Corporation Process of making a semiconductor device with a multilayer wiring and pillar formation
US5693568A (en) * 1995-12-14 1997-12-02 Advanced Micro Devices, Inc. Reverse damascene via structures
US5736457A (en) * 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization
US5783499A (en) * 1994-06-30 1998-07-21 Hyundai Electronics Industries Co., Ltd. Method for the fabrication of a semiconductor device
US5858254A (en) * 1997-01-28 1999-01-12 International Business Machines Corporation Multilayered circuitized substrate and method of fabrication
US6004874A (en) * 1996-06-26 1999-12-21 Cypress Semiconductor Corporation Method for forming an interconnect
US6133635A (en) * 1997-06-30 2000-10-17 Philips Electronics North America Corp. Process for making self-aligned conductive via structures
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
US6180509B1 (en) * 1995-07-28 2001-01-30 Stmicroelectronics, Inc. Method for forming planarized multilevel metallization in an integrated circuit
US6295721B1 (en) * 1999-12-28 2001-10-02 Taiwan Semiconductor Manufacturing Company Metal fuse in copper dual damascene
US20020155693A1 (en) * 2001-04-23 2002-10-24 Chartered Semiconductor Manufacturing Ltd. Method to form self-aligned anti-via interconnects
US20030082906A1 (en) * 2001-10-30 2003-05-01 Lammert Michael D. Via formation in polymers
US20040155011A1 (en) * 2003-02-10 2004-08-12 Hareland Scott A. Method of forming sub-micron-size structures over a substrate
US20060027928A1 (en) * 2002-06-21 2006-02-09 Takako Funakoshi Semiconductor integrated circuit device
US7358116B2 (en) * 2002-04-29 2008-04-15 Intel Corporation Substrate conductive post formation
US20130249055A1 (en) * 2007-12-20 2013-09-26 Mediatek Inc. Semiconductor capacitor
WO2020018236A1 (en) * 2018-07-17 2020-01-23 Applied Materials, Inc. Methods for manufacturing an interconnect structure for semiconductor devices

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JPS6269642A (en) * 1985-09-24 1987-03-30 Toshiba Corp Manufacture of semiconductor device
US4786962A (en) * 1986-06-06 1988-11-22 Hewlett-Packard Company Process for fabricating multilevel metal integrated circuits and structures produced thereby
JPS62291138A (en) * 1986-06-11 1987-12-17 Toshiba Corp Semiconductor device and manufacture thereof
EP0317770A1 (en) * 1987-11-23 1989-05-31 Texas Instruments Incorporated Self aligned planar metal interconnection for a VLSI device
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Cited By (46)

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Publication number Priority date Publication date Assignee Title
US4698125A (en) * 1983-06-16 1987-10-06 Plessey Overseas Limited Method of producing a layered structure
US4718977A (en) * 1984-12-20 1988-01-12 Sgs Microelettronica S.P.A. Process for forming semiconductor device having multi-thickness metallization
US4914056A (en) * 1985-05-13 1990-04-03 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device having tapered pillars
US4954423A (en) * 1985-08-06 1990-09-04 Texas Instruments Incorporated Planar metal interconnection for a VLSI device
US4926236A (en) * 1986-02-12 1990-05-15 General Electric Company Multilayer interconnect and method of forming same
US4973562A (en) * 1987-05-01 1990-11-27 U.S. Philips Corporation Method of manufacturing a semiconductor device having interconnections located both above a semiconductor region and above an isolation region adjoining it
US5043295A (en) * 1987-09-09 1991-08-27 Ruggerio Paul A Method of forming an IC chip with self-aligned thin film resistors
US5132775A (en) * 1987-12-11 1992-07-21 Texas Instruments Incorporated Methods for and products having self-aligned conductive pillars on interconnects
US5391921A (en) * 1989-04-21 1995-02-21 Nec Corporation Semiconductor device having multi-level wiring
US4933045A (en) * 1989-06-02 1990-06-12 International Business Machines Corporation Thin film multilayer laminate interconnection board assembly method
US5340775A (en) * 1992-12-15 1994-08-23 International Business Machines Corporation Structure and fabrication of SiCr microfuses
US5385867A (en) * 1993-03-26 1995-01-31 Matsushita Electric Industrial Co., Ltd. Method for forming a multi-layer metallic wiring structure
US5665642A (en) * 1993-04-30 1997-09-09 Sony Corporation Process of making a semiconductor device with a multilayer wiring and pillar formation
US5783499A (en) * 1994-06-30 1998-07-21 Hyundai Electronics Industries Co., Ltd. Method for the fabrication of a semiconductor device
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5512514A (en) * 1994-11-08 1996-04-30 Spider Systems, Inc. Self-aligned via and contact interconnect manufacturing method
WO1997039478A1 (en) * 1994-11-08 1997-10-23 Spider Systems, Inc. Self-aligned via and contact interconnect manufacturing method
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US6180509B1 (en) * 1995-07-28 2001-01-30 Stmicroelectronics, Inc. Method for forming planarized multilevel metallization in an integrated circuit
US5593919A (en) * 1995-09-05 1997-01-14 Motorola Inc. Process for forming a semiconductor device including conductive members
US5539255A (en) * 1995-09-07 1996-07-23 International Business Machines Corporation Semiconductor structure having self-aligned interconnection metallization formed from a single layer of metal
US5663101A (en) * 1995-09-07 1997-09-02 International Business Machines Corporation Semiconductor structure having multiple levels of self-aligned interconnection metallization, and methods for its preparation
US5960254A (en) * 1995-09-07 1999-09-28 International Business Machines Corporation Methods for the preparation of a semiconductor structure having multiple levels of self-aligned interconnection metallization
US5693568A (en) * 1995-12-14 1997-12-02 Advanced Micro Devices, Inc. Reverse damascene via structures
US6004874A (en) * 1996-06-26 1999-12-21 Cypress Semiconductor Corporation Method for forming an interconnect
US5858254A (en) * 1997-01-28 1999-01-12 International Business Machines Corporation Multilayered circuitized substrate and method of fabrication
US6133635A (en) * 1997-06-30 2000-10-17 Philips Electronics North America Corp. Process for making self-aligned conductive via structures
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
US6295721B1 (en) * 1999-12-28 2001-10-02 Taiwan Semiconductor Manufacturing Company Metal fuse in copper dual damascene
US20020155693A1 (en) * 2001-04-23 2002-10-24 Chartered Semiconductor Manufacturing Ltd. Method to form self-aligned anti-via interconnects
US20030082906A1 (en) * 2001-10-30 2003-05-01 Lammert Michael D. Via formation in polymers
US7358116B2 (en) * 2002-04-29 2008-04-15 Intel Corporation Substrate conductive post formation
US8093723B2 (en) 2002-06-21 2012-01-10 Renesas Electronics Corporation Method of manufacturing a semiconductor integrated circuit device
US20060027928A1 (en) * 2002-06-21 2006-02-09 Takako Funakoshi Semiconductor integrated circuit device
US20110204486A1 (en) * 2002-06-21 2011-08-25 Takako Funakoshi Method of manufacturing a semiconductor integrated circuit device
US7411301B2 (en) * 2002-06-21 2008-08-12 Renesas Technology Corp. Semiconductor integrated circuit device
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DE3478171D1 (en) 1989-06-15
AT43028T (en) 1989-05-15
GB8316476D0 (en) 1983-07-20
JPS6057650A (en) 1985-04-03
EP0129389B1 (en) 1989-05-10
EP0129389A2 (en) 1984-12-27
EP0129389A3 (en) 1986-10-22

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