ATE268943T1 - Soi substrat - Google Patents

Soi substrat

Info

Publication number
ATE268943T1
ATE268943T1 AT99300620T AT99300620T ATE268943T1 AT E268943 T1 ATE268943 T1 AT E268943T1 AT 99300620 T AT99300620 T AT 99300620T AT 99300620 T AT99300620 T AT 99300620T AT E268943 T1 ATE268943 T1 AT E268943T1
Authority
AT
Austria
Prior art keywords
outer peripheral
semiconductor
insulation layer
soi substrate
layer
Prior art date
Application number
AT99300620T
Other languages
English (en)
Inventor
Yutaka Akino
Tadashi Atoji
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Kk filed Critical Canon Kk
Application granted granted Critical
Publication of ATE268943T1 publication Critical patent/ATE268943T1/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10Methods of surface bonding and/or assembly therefor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10Methods of surface bonding and/or assembly therefor
    • Y10T156/1002Methods of surface bonding and/or assembly therefor with permanent bending or reshaping or surface deformation of self sustaining lamina
    • Y10T156/1043Subsequent to assembly
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10Methods of surface bonding and/or assembly therefor
    • Y10T156/1052Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Thin Film Transistor (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Photovoltaic Devices (AREA)
AT99300620T 1998-02-04 1999-01-28 Soi substrat ATE268943T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2306698 1998-02-04
JP37031698 1998-12-25

Publications (1)

Publication Number Publication Date
ATE268943T1 true ATE268943T1 (de) 2004-06-15

Family

ID=26360364

Family Applications (1)

Application Number Title Priority Date Filing Date
AT99300620T ATE268943T1 (de) 1998-02-04 1999-01-28 Soi substrat

Country Status (8)

Country Link
US (3) US6417108B1 (de)
EP (1) EP0935280B1 (de)
KR (1) KR100360979B1 (de)
CN (1) CN1145200C (de)
AT (1) ATE268943T1 (de)
DE (1) DE69917819T2 (de)
SG (1) SG78332A1 (de)
TW (1) TW454244B (de)

Families Citing this family (253)

* Cited by examiner, † Cited by third party
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CN1145200C (zh) 2004-04-07
US7245002B2 (en) 2007-07-17
TW454244B (en) 2001-09-11
US20020132451A1 (en) 2002-09-19
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US6417108B1 (en) 2002-07-09

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