ATE244931T1 - Ätzlösung für das ätzen von porösem silizium, ätzmethode unter verwendung der ätzlösung und verfahren zur vorbereitung einer halbleiteranordnung unter verwendung der ätzlösung - Google Patents

Ätzlösung für das ätzen von porösem silizium, ätzmethode unter verwendung der ätzlösung und verfahren zur vorbereitung einer halbleiteranordnung unter verwendung der ätzlösung

Info

Publication number
ATE244931T1
ATE244931T1 AT92301252T AT92301252T ATE244931T1 AT E244931 T1 ATE244931 T1 AT E244931T1 AT 92301252 T AT92301252 T AT 92301252T AT 92301252 T AT92301252 T AT 92301252T AT E244931 T1 ATE244931 T1 AT E244931T1
Authority
AT
Austria
Prior art keywords
etching
etching solution
porous silicon
solution
preparing
Prior art date
Application number
AT92301252T
Other languages
German (de)
English (en)
Inventor
Kiyofumi Sakaguchi
Takao Yonehara
Nobuhiko Sato
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP3148164A external-priority patent/JPH04346418A/ja
Priority claimed from JP3149297A external-priority patent/JPH04349621A/ja
Application filed by Canon Kk filed Critical Canon Kk
Application granted granted Critical
Publication of ATE244931T1 publication Critical patent/ATE244931T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/0203—Making porous regions on the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
AT92301252T 1991-02-15 1992-02-14 Ätzlösung für das ätzen von porösem silizium, ätzmethode unter verwendung der ätzlösung und verfahren zur vorbereitung einer halbleiteranordnung unter verwendung der ätzlösung ATE244931T1 (de)

Applications Claiming Priority (49)

Application Number Priority Date Filing Date Title
JP4221291 1991-02-15
JP4221391 1991-02-15
JP5561391 1991-02-28
JP5560191 1991-02-28
JP5561291 1991-02-28
JP5560391 1991-02-28
JP5560491 1991-02-28
JP5561091 1991-02-28
JP5561491 1991-02-28
JP5560591 1991-02-28
JP5560991 1991-02-28
JP5560291 1991-02-28
JP5561191 1991-02-28
JP5560691 1991-02-28
JP5560891 1991-02-28
JP5560791 1991-02-28
JP8575591 1991-03-27
JP3148164A JPH04346418A (ja) 1991-05-24 1991-05-24 半導体基材の作製方法
JP14816391 1991-05-24
JP14816091 1991-05-24
JP14816191 1991-05-24
JP14930991 1991-05-27
JP3149297A JPH04349621A (ja) 1991-05-27 1991-05-27 半導体基材の作製方法
JP14930891 1991-05-27
JP14930691 1991-05-27
JP14930791 1991-05-27
JP14930191 1991-05-27
JP14930291 1991-05-27
JP14929991 1991-05-27
JP14929891 1991-05-27
JP14931191 1991-05-27
JP14931091 1991-05-27
JP14930091 1991-05-27
JP15098391 1991-05-28
JP15098091 1991-05-28
JP15099491 1991-05-28
JP15098491 1991-05-28
JP15098291 1991-05-28
JP15098191 1991-05-28
JP15099291 1991-05-28
JP15099091 1991-05-28
JP15098991 1991-05-28
JP15099391 1991-05-28
JP15099191 1991-05-28
JP15098591 1991-05-28
JP15224891 1991-05-29
JP15224991 1991-05-29
JP15225091 1991-05-29
JP15225191 1991-05-29

Publications (1)

Publication Number Publication Date
ATE244931T1 true ATE244931T1 (de) 2003-07-15

Family

ID=27586982

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92301252T ATE244931T1 (de) 1991-02-15 1992-02-14 Ätzlösung für das ätzen von porösem silizium, ätzmethode unter verwendung der ätzlösung und verfahren zur vorbereitung einer halbleiteranordnung unter verwendung der ätzlösung

Country Status (8)

Country Link
US (1) US5767020A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (2) EP0499488B9 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR960007640B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CN (1) CN1099905A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AT (1) ATE244931T1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA2061264C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
MY (1) MY114349A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
SG (2) SG47089A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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Also Published As

Publication number Publication date
EP1347505A2 (en) 2003-09-24
EP0499488B9 (en) 2004-01-28
CA2061264A1 (en) 1992-08-16
CA2061264C (en) 1999-11-16
KR960007640B1 (en) 1996-06-07
CN1099905A (zh) 1995-03-08
MY114349A (en) 2002-10-31
SG93197A1 (en) 2002-12-17
US5767020A (en) 1998-06-16
EP0499488B1 (en) 2003-07-09
EP1347505A3 (en) 2004-10-20
EP0499488A3 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1995-03-01
SG47089A1 (en) 1998-03-20
EP0499488A2 (en) 1992-08-19

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