DE3585115D1 - Verfahren zur herstellung und einstellung von eingegrabenen schichten. - Google Patents
Verfahren zur herstellung und einstellung von eingegrabenen schichten.Info
- Publication number
- DE3585115D1 DE3585115D1 DE8585901701T DE3585115T DE3585115D1 DE 3585115 D1 DE3585115 D1 DE 3585115D1 DE 8585901701 T DE8585901701 T DE 8585901701T DE 3585115 T DE3585115 T DE 3585115T DE 3585115 D1 DE3585115 D1 DE 3585115D1
- Authority
- DE
- Germany
- Prior art keywords
- substrate
- recesses
- epitaxial layer
- adjusting
- producing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 5
- 230000015572 biosynthetic process Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/975—Substrate or mask aligning feature
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Glass Compositions (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/590,678 US4487653A (en) | 1984-03-19 | 1984-03-19 | Process for forming and locating buried layers |
PCT/US1985/000355 WO1985004134A1 (en) | 1984-03-19 | 1985-03-04 | Process for forming and locating buried layers |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3585115D1 true DE3585115D1 (de) | 1992-02-20 |
Family
ID=24363228
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585901701T Expired - Lifetime DE3585115D1 (de) | 1984-03-19 | 1985-03-04 | Verfahren zur herstellung und einstellung von eingegrabenen schichten. |
Country Status (6)
Country | Link |
---|---|
US (1) | US4487653A (de) |
EP (1) | EP0174986B1 (de) |
JP (1) | JPS61501483A (de) |
AT (1) | ATE71476T1 (de) |
DE (1) | DE3585115D1 (de) |
WO (1) | WO1985004134A1 (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4632724A (en) * | 1985-08-19 | 1986-12-30 | International Business Machines Corporation | Visibility enhancement of first order alignment marks |
US4737468A (en) * | 1987-04-13 | 1988-04-12 | Motorola Inc. | Process for developing implanted buried layer and/or key locators |
JP2897248B2 (ja) * | 1989-04-18 | 1999-05-31 | 富士通株式会社 | 半導体装置の製造方法 |
US5249016A (en) * | 1989-12-15 | 1993-09-28 | Canon Kabushiki Kaisha | Semiconductor device manufacturing system |
US6171966B1 (en) * | 1996-08-15 | 2001-01-09 | Applied Materials, Inc. | Delineation pattern for epitaxial depositions |
US6207966B1 (en) | 1998-12-04 | 2001-03-27 | Advanced Micro Devices, Inc | Mark protection with transparent film |
US6576529B1 (en) * | 1999-12-07 | 2003-06-10 | Agere Systems Inc. | Method of forming an alignment feature in or on a multilayered semiconductor structure |
US6573151B1 (en) * | 2000-08-22 | 2003-06-03 | Advanced Micro Devices, Inc. | Method of forming zero marks |
DE10047152B4 (de) * | 2000-09-22 | 2006-07-06 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG | Hochvolt-Diode und Verfahren zu deren Herstellung |
US7247952B2 (en) * | 2003-10-30 | 2007-07-24 | Hewlett-Packard Development Company, L.P. | Optical targets |
KR101001875B1 (ko) | 2006-09-30 | 2010-12-17 | 엘지이노텍 주식회사 | 등방성 에칭을 이용한 미세 패턴 형성방법 및 이를 이용하여 제조된 미세패턴이 형성된 반도체 기판 면상 부재 |
CN101852985B (zh) * | 2009-03-30 | 2013-01-09 | 鸿富锦精密工业(深圳)有限公司 | 一种基板对位标记的制作方法 |
US8628677B2 (en) * | 2011-03-31 | 2014-01-14 | Fujifilm Corporation | Forming curved features using a shadow mask |
CN113540040B (zh) * | 2021-07-15 | 2023-04-11 | 长江存储科技有限责任公司 | 一种半导体结构的制造方法及其测试方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3600241A (en) * | 1968-09-09 | 1971-08-17 | Ibm | Method of fabricating semiconductor devices by diffusion |
JPS51147179A (en) * | 1975-06-12 | 1976-12-17 | Fujitsu Ltd | Method of munufacturing of semiconductor device |
GB1520925A (en) * | 1975-10-06 | 1978-08-09 | Mullard Ltd | Semiconductor device manufacture |
US4170501A (en) * | 1978-02-15 | 1979-10-09 | Rca Corporation | Method of making a semiconductor integrated circuit device utilizing simultaneous outdiffusion and autodoping during epitaxial deposition |
JPS5534442A (en) * | 1978-08-31 | 1980-03-11 | Fujitsu Ltd | Preparation of semiconductor device |
US4251300A (en) * | 1979-05-14 | 1981-02-17 | Fairchild Camera And Instrument Corporation | Method for forming shaped buried layers in semiconductor devices utilizing etching, epitaxial deposition and oxide formation |
JPS5645294A (en) * | 1979-09-19 | 1981-04-24 | Toshiba Corp | End cock welding method for covering tube of atomic fuel |
US4309813A (en) * | 1979-12-26 | 1982-01-12 | Harris Corporation | Mask alignment scheme for laterally and totally dielectrically isolated integrated circuits |
US4351892A (en) * | 1981-05-04 | 1982-09-28 | Fairchild Camera & Instrument Corp. | Alignment target for electron-beam write system |
-
1984
- 1984-03-19 US US06/590,678 patent/US4487653A/en not_active Expired - Lifetime
-
1985
- 1985-03-04 JP JP60501272A patent/JPS61501483A/ja active Pending
- 1985-03-04 WO PCT/US1985/000355 patent/WO1985004134A1/en active IP Right Grant
- 1985-03-04 EP EP85901701A patent/EP0174986B1/de not_active Expired - Lifetime
- 1985-03-04 DE DE8585901701T patent/DE3585115D1/de not_active Expired - Lifetime
- 1985-03-04 AT AT85901701T patent/ATE71476T1/de active
Also Published As
Publication number | Publication date |
---|---|
EP0174986A1 (de) | 1986-03-26 |
JPS61501483A (ja) | 1986-07-17 |
EP0174986B1 (de) | 1992-01-08 |
WO1985004134A1 (en) | 1985-09-26 |
EP0174986A4 (de) | 1989-06-14 |
ATE71476T1 (de) | 1992-01-15 |
US4487653A (en) | 1984-12-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |