ATE171814T1 - Verfahren zur herstellung einer höckerkontaktstruktur auf einer halbleiteranordnung - Google Patents

Verfahren zur herstellung einer höckerkontaktstruktur auf einer halbleiteranordnung

Info

Publication number
ATE171814T1
ATE171814T1 AT93300480T AT93300480T ATE171814T1 AT E171814 T1 ATE171814 T1 AT E171814T1 AT 93300480 T AT93300480 T AT 93300480T AT 93300480 T AT93300480 T AT 93300480T AT E171814 T1 ATE171814 T1 AT E171814T1
Authority
AT
Austria
Prior art keywords
passivation layer
bump
stem
margins
producing
Prior art date
Application number
AT93300480T
Other languages
English (en)
Inventor
George Erdos
Original Assignee
Gennum Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gennum Corp filed Critical Gennum Corp
Application granted granted Critical
Publication of ATE171814T1 publication Critical patent/ATE171814T1/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01022—Titanium [Ti]
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    • H01L2924/01023—Vanadium [V]
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    • H01L2924/01027—Cobalt [Co]
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01—Chemical elements
    • H01L2924/01056—Barium [Ba]
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    • H01L2924/01074—Tungsten [W]
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    • H01L2924/01082—Lead [Pb]
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    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AT93300480T 1992-01-27 1993-01-22 Verfahren zur herstellung einer höckerkontaktstruktur auf einer halbleiteranordnung ATE171814T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA002075462A CA2075462C (en) 1992-01-27 1992-01-27 Bump structure and method for bonding to a semi-conductor device
US07/836,580 US5293071A (en) 1992-01-27 1992-02-18 Bump structure for bonding to a semi-conductor device

Publications (1)

Publication Number Publication Date
ATE171814T1 true ATE171814T1 (de) 1998-10-15

Family

ID=25675407

Family Applications (1)

Application Number Title Priority Date Filing Date
AT93300480T ATE171814T1 (de) 1992-01-27 1993-01-22 Verfahren zur herstellung einer höckerkontaktstruktur auf einer halbleiteranordnung

Country Status (7)

Country Link
US (1) US5293071A (de)
EP (1) EP0554019B1 (de)
JP (1) JP2772606B2 (de)
AT (1) ATE171814T1 (de)
CA (1) CA2075462C (de)
DE (1) DE69321265T2 (de)
DK (1) DK0554019T3 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07231015A (ja) * 1994-02-17 1995-08-29 Sanyo Electric Co Ltd 半導体装置及びその製造方法
KR970053198A (ko) * 1995-12-30 1997-07-29 구자홍 반도체소자의 본딩장치 및 그 제조방법
US5760479A (en) * 1996-02-29 1998-06-02 Texas Instruments Incorporated Flip-chip die attachment for a high temperature die to substrate bond
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
JP2003045877A (ja) * 2001-08-01 2003-02-14 Sharp Corp 半導体装置およびその製造方法
EP1472730A4 (de) * 2002-01-16 2010-04-14 Mann Alfred E Found Scient Res Platzsparende kapselung elektronischer schaltungen
US7541275B2 (en) * 2004-04-21 2009-06-02 Texas Instruments Incorporated Method for manufacturing an interconnect
US8022544B2 (en) * 2004-07-09 2011-09-20 Megica Corporation Chip structure
CN101038441B (zh) * 2006-03-14 2010-09-08 南茂科技股份有限公司 凸块制程

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3689991A (en) * 1968-03-01 1972-09-12 Gen Electric A method of manufacturing a semiconductor device utilizing a flexible carrier
DE2028819C3 (de) * 1970-06-11 1980-05-29 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Herstellen eines Metallkontakts mit einer Kontakthöhe > 10 µ m
JPS5421165A (en) * 1977-07-18 1979-02-17 Nec Corp Semiconductor device
US4258382A (en) * 1978-07-03 1981-03-24 National Semiconductor Corporation Expanded pad structure
EP0068091B1 (de) * 1981-06-30 1988-08-10 International Business Machines Corporation Verfahren zum Verbinden eines Halbleiterchips auf einem Substrat und solche Verbindung
JPS6149819A (ja) * 1984-08-20 1986-03-11 Shokichi Hayashi 金型のガス抜き装置
JPH0194641A (ja) * 1987-10-05 1989-04-13 Nec Corp 半導体装置
JPH0233929A (ja) * 1988-07-23 1990-02-05 Nec Corp 半導体装置
JPH03198342A (ja) * 1989-12-26 1991-08-29 Nec Corp 半導体装置の製造方法
JPH047839A (ja) * 1990-04-25 1992-01-13 Seiko Epson Corp 集積回路の製造方法
JP2514291B2 (ja) * 1990-06-22 1996-07-10 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 半導体回路装置の製造方法
JPH04180231A (ja) * 1990-11-15 1992-06-26 Fuji Electric Co Ltd 微細バンプ電極を有する半導体装置の製造方法

Also Published As

Publication number Publication date
US5293071A (en) 1994-03-08
JP2772606B2 (ja) 1998-07-02
DE69321265D1 (de) 1998-11-05
DE69321265T2 (de) 1999-02-18
CA2075462C (en) 1999-05-04
JPH06224200A (ja) 1994-08-12
CA2075462A1 (en) 1993-07-28
DK0554019T3 (da) 1999-06-21
EP0554019B1 (de) 1998-09-30
EP0554019A1 (de) 1993-08-04

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