CN101038441B - 凸块制程 - Google Patents

凸块制程 Download PDF

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CN101038441B
CN101038441B CN2006100648359A CN200610064835A CN101038441B CN 101038441 B CN101038441 B CN 101038441B CN 2006100648359 A CN2006100648359 A CN 2006100648359A CN 200610064835 A CN200610064835 A CN 200610064835A CN 101038441 B CN101038441 B CN 101038441B
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CN101038441A (zh
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王俊恒
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

一种凸块制程包括下列步骤。首先提供一具有多个接点的本体。然后形成具有多个第一开口的一保护层于本体上,其中这些第一开口暴露出本体的多个接点。接着于保护层与这些接点上形成一球底金属层。之后形成具有多个第二开口的一图案化光阻层于球底金属层上,其中这些第二开口分别位于这些第一开口的上方。然后对应这些接点而形成多个凸块于第二开口内,其中这些凸块的远离保护层的表面低于图案化光阻层远离保护层的表面。接着对这些凸块进行蚀刻,以平坦化这些凸块的表面。然后移除图案化光阻层以及移除球底金属层的不为这些凸块所覆盖的部份。

Description

凸块制程
技术领域
本发明是有关于一种凸块制程,且特别是有关于一种能够制作出具有平坦表面的凸块的凸块制程。
背景技术
覆晶接合技术(flip chip interconnect technology)乃是一种将晶片(die)连接至一线路板的封装技术,其主要是在晶片的多个接点上形成多个凸块(bump)。接着将晶片翻转(flip),并利用这些凸块来将晶片的这些接点连接至线路板上的接合垫(terminal),以使得晶片可经由这些凸块而电性连接至线路板上。
图1A至图1C绘示为习知的在晶片的接点上形成凸块的制程示意图。请参照图1A,首先提供一晶片110,其中晶片110具有一主动表面112。晶片110还具有多个接点114,配置于主动表面112上。接着于主动表面112上形成一层保护层120。
请参照图1B,然后经由微影/蚀刻制程,在保护层120上形成多个开口122,其中这些开口122暴露出这些接点114。值得注意的是,由于开口122略小于接点114,因此位于开口122附近的保护层120具有一隆起部份P。接着于保护层120与接点114上形成一层球底金属材料150。然后于球底金属材料150上形成一光阻层130。之后经由微影/蚀刻制程在光阻层130上形成多个开口132,其中这些开口132暴露出球底金属材料150的相应于接点114的区域。然后,经由电镀将金形成于这些开口132内,以在晶片110上形成多个金凸块140,其中这些金凸块140经由球底金属材料150与这些接点114机械与电性连接。
请参照图1C,接着先移除光阻层130。之后以这些金凸块140为罩幕,移除不为金凸块140所覆盖的球底金属材料150,以形成一具有多个金凸块140的晶片结构100。值得注意的是,由于金凸块140所覆盖的区域包含保护层120的环形的隆起部份P,因此金凸块140亦会具有一环形的隆起部份Q,其中隆起部份Q是对应于隆起部份P。
请参照图2,其绘示为具有习知技术所制作的凸块的晶片电性连接于一线路板的示意图。习知技术可以经由一单向导电接着膜250以及已经制作完成的金凸块140,而将一线路板200电性连接于晶片110,其中单向导电接着膜250具有多个内层为导体而外层为绝缘体的颗粒252,而线路板200具有多个接合垫210。
详细地说,当线路板200经由单向导电接着膜250以及金凸块140而与晶片110电性连接时,部分的颗粒252会同时受到金凸块140的隆起部份Q以及接合垫210的压迫。此时颗粒252外层的绝缘体受到隆起部份Q以及接合垫210压迫的部位便会破裂,并且暴露出内层的导体。如此一来,颗粒252内层的导体便能够经由外层的绝缘体的破裂处而与隆起部份Q以及接合垫210电性接触,进而达成晶片110与线路板200之间的电性连接。
值得注意的是,由于金凸块140的隆起部份Q的表面积相当的细小,是以当习知技术经由单向导电接着膜250来将金凸块140电性连接于接合垫210时,这样的电性连接关系会具有较低的可靠度。
发明内容
本发明的目的就是在提供一种凸块制程,以制作出具有平坦的表面的凸块。
本发明提出一种凸块制程,此制程包括先提供一本体,并且于本体上形成多个接点。然后形成一保护层于本体上,其中本体具有多个第一开口,并且这些第一开口暴露出本体的多个接点。接着于保护层与这些接点上形成一球底金属层。之后形成一图案化光阻层于球底金属层上,其中图案化光阻层具有多个第二开口,并且这些第二开口分别位于这些第一开口的上方。之后对应这些接点而形成多个凸块于第二开口内,其中这些凸块与接点彼此电性连接,并且这些凸块的远离保护层的表面低于图案化光阻层远离保护层的表面。之后对这些凸块进行蚀刻,以平坦化这些凸块的表面。然后移除图案化光阻层。接着移除球底金属层的不为这些凸块所覆盖的部份以形成多个球底金属垫,其中这些凸块经由这些球底金属垫而与这些接点电性连接。
依照本发明的较佳实施例所述的凸块制程,在对这些凸块进行蚀刻之前,更包括以电浆对这些凸块的表面进行清洗。
依照本发明的较佳实施例所述的凸块制程,在这些第二开口内形成这些凸块的方法为电镀。
依照本发明的较佳实施例所述的凸块制程,其中这些第二开口内的这些凸块的材料为金。
本发明因在形成这些凸块后并且在移除图案化光阻层之前对这些凸块进行蚀刻,以对这些凸块的表面进行平坦化,是以相较于习知技术而言,本发明所制作的凸块与接合垫之间的电性连接关系会具有较高的可靠度。
为让本发明的上述和其他目的、特征和优点能更明显易懂,下文特举较佳实施例,并配合所附图式,作详细说明如下。
附图说明
图1A至图1C绘示为习知的在晶片的接点上形成凸块的制程示意图。
图2绘示为具有习知技术所制作的凸块的晶片电性连接于一线路板的示意图。
图3A至图3C绘示为本发明一实施例的凸块制程的流程示意图。
图4绘示为具有本实施例所制作的凸块的本体与一线路板电性连接的示意图。
110:晶片              112:主动表面
114:接点              120:保护层
122:开口              130:光阻层
132:开口              140:金凸块
200:线路板            210:接合垫
250:单向导电接着膜    252:颗粒
312:本体              314:接点
316:保护层            318:第一开口
320:图案化光阻层      320a:表面
322:第二开口          330:凸块
330a:表面             340:球底金属层
345:球底金属垫        P:隆起部份
Q:隆起部份            S:隆起部份
R:隆起部份
具体实施方式
请参照图3A至图3C,其绘示为本发明一实施例的凸块制程的流程示意图。请参照图3A,首先提供一本体312,其中本体312具有多个接点314,并且本体312例如是晶片、线路板或是其他类似的电路元件。接着于本体312上形成一保护层316,其中形成保护层316的方式例如是网版印刷、涂布或是直接将干膜型态的保护层316的材料贴附于本体312上。
然后,例如经由微影/蚀刻的方式,在保护层316上形成多个第一开口318,其中这些开口318暴露出本体312的多个接点314。接着,于保护层316与这些接点314上形成一球底金属层340。然后,例如利用涂布、电着沉积(electro deposition)、直接贴附干膜(dry-film)光阻或是其他的方式,于球底金属层340上形成一光阻材料层(未绘示)。之后,例如经由微影/蚀刻的方式将此光阻材料层(未绘示)图案化以形成一图案化光阻层320,其中图案化光阻层320具有多个第二开口322,并且这些第二开口322分别位于这些第一开口318的上方。
接着,例如利用电镀或是其他的方式,以在这些第二开口322内形成多个凸块330,其中这些凸块330的材质例如是金,并且这些凸块330与这些接点314彼此电性连接。此外,这接这些凸块330的远离保护层316的表面330a低于图案化光阻层320的远离保护层316的表面320a。值得注意的是,由于保护层316的厚度实质上为一定值,因此保护层316的邻近于第一开口318处会具有隆起部份S。是以凸块330的对应于隆起部份S处亦会具有隆起部份R。
请参照图3B,接着对这些凸块330进行蚀刻。由于蚀刻液对于凸块330的隆起部份R具有较大的蚀刻速率,是以在蚀刻的过程中,本实施例可以移除这些隆起部份R并且对这些凸块330的表面330a进行平坦化。更佳的是,在对这些凸块330进行蚀刻之前,本实施例更可以经由电浆对这些凸块330的表面330a进行清洗,以增加平坦化的效果。
请参照图3C,先移除图案化光阻层320。之后以这些凸块330为罩幕,移除球底金属层340的不为这些凸块330覆盖的区域,以形成多个球底金属垫345,其中这些凸块330分别经由这些球底金属垫345而与这些接垫314电性连接。请参照图4,其绘示为具有本实施例所制作的凸块的本体与一线路板电性连接的示意图。本实施例可以经由一单向导电接着膜250以及已经制作完成的凸块330,而将一线路板200电性连接于本体312,其中单向导电接着膜250具有多个内层为导体而外层为绝缘体的颗粒252,而线路板200具有多个接合垫210。
详细地说,当线路板200经由单向导电接着膜250以及凸块330而与本体312电性连接时,部分的颗粒252会同时受到凸块330的表面330a以及接合垫210的压迫。此时颗粒252外层的绝缘体受到表面330a以及接合垫210压迫的部位便会破裂,并且暴露出内层的导体。如此一来,颗粒252内层的导体便能够经由外层的绝缘体的破裂处而与凸块330以及接合垫210电性接触,进而达成本体312与线路板200之间的电性连接。
综上所述,由于本发明在形成凸块之后以及移除图案化光阻层之前,经由蚀刻的方式对凸块的表面进行平坦化,因此当本发明经由单向导电接着膜来将金凸块电性连接于接合垫时,本发明所制作的凸块的整个表面几乎都可以用来压迫单向导电接着膜内的颗粒。相较于习知技术而言,由于本发明所制作的凸块的整个表面几乎都可以用来压迫单向导电接着膜内的颗粒,而习知技术所制作的金凸块仅能经由其表面上的隆起部份来压迫单向导电接着膜内的颗粒,是以本发明所制作的凸块与接合垫之间的电性连接关系会具有较高的可靠度。
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何熟习此技艺者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视权利要求所界定者为准。

Claims (4)

1.一种凸块制程,其包括:
提供一本体,其具有多个接点;
形成一保护层于本体上,其中该本体具有多个第一开口,并且该些第一开口暴露出该本体的多个接点;
于该保护层与该些接点上形成一球底金属层;
形成一图案化光阻层于该球底金属层上,其中该图案化光阻层具有多个第二开口,并且该些第二开口分别位于该些第一开口的上方;
对应该些接点而形成多个凸块于第二开口内,其中该些凸块的远离该保护层的表面低于该图案化光阻层远离该保护层的表面;
对该些凸块进行蚀刻,以平坦化该些凸块的表面;
移除该图案化光阻层;以及
移除该球底金属层的不为该些凸块所覆盖的部份以形成多个球底金属垫,其中该些凸块经由该些球底金属垫而与该些接点电性连接。
2.根据权利要求1所述的凸块制程,在对该些凸块进行蚀刻之前,更包括以电浆对该些凸块的表面进行清洗。
3.根据权利要求1所述的凸块制程,其中在该些第二开口内形成该些凸块的方法为电镀。
4.根据权利要求1所述的凸块制程,其中该些第二开口内的该些凸块的材料为金。
CN2006100648359A 2006-03-14 2006-03-14 凸块制程 Expired - Fee Related CN101038441B (zh)

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US5293071A (en) * 1992-01-27 1994-03-08 Gennum Corporation Bump structure for bonding to a semi-conductor device
CN1437238A (zh) * 2002-02-04 2003-08-20 利弘科技股份有限公司 平顶金凸块的制程方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4930001A (en) * 1989-03-23 1990-05-29 Hughes Aircraft Company Alloy bonded indium bumps and methods of processing same
US5293071A (en) * 1992-01-27 1994-03-08 Gennum Corporation Bump structure for bonding to a semi-conductor device
CN1437238A (zh) * 2002-02-04 2003-08-20 利弘科技股份有限公司 平顶金凸块的制程方法

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