WO2024127945A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2024127945A1
WO2024127945A1 PCT/JP2023/042179 JP2023042179W WO2024127945A1 WO 2024127945 A1 WO2024127945 A1 WO 2024127945A1 JP 2023042179 W JP2023042179 W JP 2023042179W WO 2024127945 A1 WO2024127945 A1 WO 2024127945A1
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Prior art keywords
resin
semiconductor device
layer
metal layer
resin layer
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PCT/JP2023/042179
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English (en)
French (fr)
Japanese (ja)
Inventor
椋平 長谷川
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings

Definitions

  • This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.
  • Patent Document 1 discloses an example of a semiconductor device equipped with a semiconductor element.
  • the semiconductor device in this document includes a semiconductor element, a wiring portion, and a sealing resin.
  • the electrode pads of the semiconductor element are conductively joined to the wiring portion.
  • the wiring portion is covered with the sealing resin.
  • the crack may progress to the outside of the sealing resin. This may cause moisture to seep into the semiconductor device, for example.
  • An object of the present disclosure is to provide a semiconductor device that is an improvement over conventional semiconductor devices.
  • an object of the present disclosure is to provide a semiconductor device that can suppress peeling between the wiring portion and the sealing resin, and a method for manufacturing such a semiconductor device.
  • the semiconductor device provided by the first aspect of the present disclosure comprises a semiconductor element, a sealing resin, and a wiring portion that is conductive to the semiconductor element.
  • the sealing resin has a first resin surface facing a first side in the thickness direction and a second resin surface facing a second side.
  • the wiring portion includes a first metal layer including a through wiring portion exposed from the second resin surface, and a second metal layer including a connecting wiring portion that is conductive between the through wiring portion and the semiconductor element. At least a portion of the connecting wiring portion has an uneven shape when viewed in the thickness direction.
  • the method for manufacturing a semiconductor device includes the steps of forming a first metal layer having a plurality of through-hole wiring portions on a substrate, forming a first resin layer covering the first metal layer on the substrate, thinning the first resin layer from the side opposite the substrate to expose the plurality of through-hole wiring portions from the first resin layer, forming a mask layer having a plurality of openings on the first resin layer and the first metal layer, forming a second metal layer that is conductive to the first metal layer using the mask layer, mounting a semiconductor element on the second metal layer, forming a second resin layer covering the second metal layer and the semiconductor element on the first resin layer, and removing the substrate.
  • the step of forming the mask layer at least a portion of the openings is made uneven.
  • the above configuration makes it possible to prevent peeling between the wiring portion and the sealing resin in the semiconductor device.
  • FIG. 1 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a partial plan view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 3 is a partial enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 4 is a partial bottom view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 5 is a cross-sectional view taken along line VV in FIG.
  • FIG. 6 is a partial cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 7 is a partial cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 1 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a partial plan view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 3 is a partial enlarged plan view showing the
  • FIG. 8 is a partial cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 9 is a partial cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 10 is a partial plan view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 11 is a partial cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 12 is a partial cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 13 is a partial cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 14 is a partial cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 15 is a partial cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 16 is a partial cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 17 is a partial cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 18 is a partial cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 19 is a partial plan view showing a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 20 is a partial plan view showing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 21 is a partial plan view showing a semiconductor device according to a fourth embodiment of the present disclosure.
  • an object A is formed on an object B" and “an object A is formed on an object B” include “an object A is formed directly on an object B” and “an object A is formed on an object B with another object interposed between the object A and the object B” unless otherwise specified.
  • an object A is disposed on an object B” and “an object A is disposed on an object B” include “an object A is disposed directly on an object B” and “an object A is disposed on an object B with another object interposed between the object A and the object B" unless otherwise specified.
  • an object A is located on an object B includes “an object A is located on an object B in contact with an object B” and “an object A is located on an object B with another object interposed between the object A and the object B” unless otherwise specified.
  • an object A overlaps an object B when viewed in a certain direction includes “an object A overlaps the entire object B” and “an object A overlaps a part of an object B.”
  • a surface A faces (one side or the other side of) direction B” is not limited to the case where the angle of surface A with respect to direction B is 90 degrees, but also includes the case where surface A is tilted with respect to direction B.
  • First embodiment: 1 to 5 show a semiconductor device according to a first embodiment of the present disclosure.
  • the semiconductor device A1 of this embodiment includes a semiconductor element 1, a sealing resin 2, and a wiring portion 3.
  • FIGS. 1 and 2 are partial plan views showing semiconductor device A1.
  • FIG. 3 is a partial enlarged plan view showing semiconductor device A1.
  • FIG. 4 is a partial bottom view showing semiconductor device A1.
  • FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1.
  • a second resin layer 22 which will be described later, has been omitted from FIGS. 1 and 2.
  • the z direction is an example of a "thickness direction.”
  • the x direction is a direction that is orthogonal to the z direction.
  • the y direction is a direction that is orthogonal to the z direction and the x direction.
  • the semiconductor element 1 is an element made of a semiconductor material and performs the main electrical function of the semiconductor device A1.
  • the semiconductor element 1 is a so-called active element, and is, for example, an integrated circuit (IC) such as an LSI (Large Scale Integration), a voltage control element such as an LDO (Low Drop Out), an amplifying element such as an operational amplifier, or the like.
  • IC integrated circuit
  • LSI Large Scale Integration
  • LDO Low Drop Out
  • an amplifying element such as an operational amplifier, or the like.
  • the semiconductor element 1 of this embodiment has an element body 11 and multiple electrodes 12.
  • the element body 11 is a main body portion whose main component is a semiconductor.
  • the multiple electrodes 12 are provided on the z2 side of the element body 11 in the z direction, and are so-called pad electrodes.
  • the electrodes 12 contain, for example, Cu (copper), Al (aluminum), etc.
  • the sealing resin 2 covers the semiconductor element 1.
  • the sealing resin 2 has a first resin surface 201, a second resin surface 202, a third resin surface 203, a fourth resin surface 204, a fifth resin surface 205, and a sixth resin surface 206.
  • the first resin surface 201 is a surface facing the z1 side in the z direction.
  • the second resin surface 202 is a surface facing the z2 side in the z direction.
  • the third resin surface 203 is a surface facing the x1 side in the x direction.
  • the fourth resin surface 204 is a surface facing the x2 side in the x direction.
  • the fifth resin surface 205 is a surface facing the y1 side in the y direction.
  • the sixth resin surface 206 is a surface facing the y2 side in the y direction.
  • the fifth resin surface 205 has a recess 2051.
  • the recess 2051 is a portion of the fifth resin surface 205 located on the z2 side in the z direction, and is recessed to the y2 side in the y direction.
  • the sixth resin surface 206 has a recess 2061.
  • the recess 2061 is a portion of the sixth resin surface 206 located on the z2 side in the z direction, and is recessed to the y1 side in the y direction.
  • the sealing resin 2 has a first resin layer 21 and a second resin layer 22.
  • the first resin layer 21 is a layer located on the z2 side in the z direction.
  • the first resin layer 21 is made of, for example, a black epoxy resin.
  • the first resin layer 21 may also contain a filler (not shown).
  • the second resin surface 202 is formed of the first resin layer 21.
  • the first resin layer 21 has a seventh resin surface 207.
  • the seventh resin surface 207 is a surface facing the z1 side in the z direction.
  • the second resin layer 22 is laminated on the seventh resin surface 207 of the first resin layer 21 and covers the semiconductor element 1.
  • the second resin layer 22 is made of, for example, a black epoxy resin.
  • the first resin layer 21 may also contain a filler (not shown).
  • the first resin surface 201 is formed of the second resin layer 22.
  • the thickness of the first resin layer 21 in the z direction is thinner than the thickness of the second resin layer 22 in the z direction.
  • the thickness of the first resin layer 21 is, for example, 20 ⁇ m or more and 100 ⁇ m or less
  • the thickness of the second resin layer 22 is, for example, 400 ⁇ m or more and 1200 ⁇ m or less.
  • the wiring portion 3 constitutes a conductive path for achieving the electrical function of the semiconductor element 1.
  • the wiring portion 3 of this embodiment includes a first metal layer 31 and a second metal layer 32.
  • the first metal layer 31 is located between the second resin surface 202 and the seventh resin surface 207 in the z direction.
  • the first metal layer 31 is mainly composed of, for example, Cu (copper) and is formed by, for example, electrolytic plating.
  • the first metal layer 31 may further include a base layer and a plating layer stacked on top of each other.
  • the base layer is composed of a Ti (titanium) layer and a Cu (copper) layer stacked on top of each other, and has a thickness of about 200 nm or more and 800 nm or less.
  • the plating layer contains, for example, Cu (copper) and is set to be thicker than the base layer.
  • the first metal layer 31 of this embodiment includes a plurality of through wiring parts 310.
  • Each of the plurality of through wiring parts 310 penetrates the first resin layer 21 in the z direction and reaches the first resin surface 201 and the seventh resin surface 207.
  • the number, shape, arrangement, etc. of the plurality of through wiring parts 310 are not limited in any way.
  • the plurality of through wiring parts 310 are arranged in two rows in the x direction along the fifth resin surface 205 and the sixth resin surface 206.
  • the through wiring part 310 has a back surface 311 and an end surface 312.
  • the back surface 311 is a surface exposed from the second resin surface 202.
  • the end surface 312 faces the y1 side or y2 side in the y direction and is exposed from the fifth resin surface 205 or the sixth resin surface 206.
  • the back surface 311 is rectangular when viewed in the z direction.
  • the second metal layer 32 is located between the first resin layer 21 and the second resin layer 22, and is formed on the seventh resin surface 207.
  • the thickness of the second metal layer 32 is, for example, 10 ⁇ m or more and 60 ⁇ m or less.
  • the second metal layer 32 is mainly composed of, for example, Cu (copper).
  • the second metal layer 32 is composed of an underlayer and a plating layer stacked on each other.
  • the underlayer is composed of a Ti (titanium) layer and a Cu (copper) layer stacked on each other, and has a thickness of 200 nm or more and 800 nm or less.
  • the underlayer can be formed, for example, by sputtering.
  • the plating layer contains, for example, Cu, and is set to be thicker than the underlayer.
  • the plating layer can be formed, for example, by electrolytic plating.
  • the constituent material and the formation method of the second metal layer 32 are not limited to those described above.
  • a Ni (nickel) layer may be formed between the underlayer and the plating layer.
  • the Ni layer can be formed, for example, by electrolytic plating.
  • the area in which the second metal layer 32 is formed is not limited to the areas shown in Figures 1, 2, and 4.
  • the second metal layer 32 includes a plurality of interconnection wiring sections 320, which provide electrical continuity between the through wiring section 310 and the electrode 12 of the semiconductor element 1.
  • the interconnection wiring section 320 is in contact with the through wiring section 310.
  • the electrode 12 is electrically connected to the interconnection wiring section 320 via a conductive bonding material 39.
  • the conductive bonding material 39 is, for example, solder.
  • the interconnect wiring section 320 includes a first edge 321, a second edge 322, a pair of first sides 323, a pair of second sides 324, and a number of intermediate sides 325, 326.
  • the first edge 321 is the edge of the interconnect wiring portion 320 on the side where the electrode 12 is conductively joined.
  • the second edge 322 is the edge opposite the first edge 321. In the illustrated example, the first edge 321 is exposed from the fifth resin surface 205 or the sixth resin surface 206.
  • the pair of first sides 323 extend from both ends of the first edge 321.
  • the second sides 324 extend from both ends of the second edge 322 and overlap with the through wiring portion 310 when viewed in the z direction.
  • the multiple intermediate sides 325 and the multiple intermediate sides 326 are interposed between the pair of first sides 323 and the pair of second sides 324, and connect the pair of first sides 323 and the pair of second sides 324.
  • each of the pair of first sides 323 has an uneven shape.
  • the pitch of the uneven shape is 15 ⁇ m or more and 100 ⁇ m or less.
  • the specific shape of the uneven shape there is no limitation on the specific shape of the uneven shape, and various shapes such as a shape composed of multiple curves such as a sine wave shape, or a triangular wave shape, a rectangular wave shape, etc. are appropriately adopted.
  • the uneven shape of the first side 323 is a sine wave shape.
  • the distance between the peak and the valley is, for example, 15 ⁇ m or more and 100 ⁇ m or less.
  • the wiring portion 3 of this embodiment also includes a plurality of surface metal layers 33.
  • the surface metal layers 33 cover the rear surface 311 and the end surfaces 312.
  • the surface metal layers 33 have a structure in which, for example, a Ni (nickel) layer, a Pd (palladium) layer, and an Au (gold) layer are laminated in this order.
  • the surface metal layer 33 is not limited to this, and may be a Ni (nickel) layer and an Au (gold) layer laminated in this order, or may be only an Au (gold) layer, or may be only an Sn (tin) layer.
  • the substrate 4 is prepared.
  • the substrate 4 is made of a semiconductor material, for example, a single crystal material, and in this embodiment, it is a single crystal material of Si (silicon).
  • a Si wafer is prepared as the substrate 4.
  • the thickness of the substrate 4 is, for example, about 725 to 775 ⁇ m.
  • the substrate 4 is not limited to a Si (silicon) wafer, and may be, for example, a glass substrate.
  • the first metal layer 31A includes a plurality of through-hole wiring portions 310.
  • a base layer in contact with the substrate 4 is formed. This base layer is formed by a sputtering method.
  • a Ti (titanium) layer in contact with the substrate 4 is formed, and then a Cu (copper) layer in contact with the Ti (titanium) layer is formed.
  • the base layer is formed from a Ti (titanium) layer and a Cu (copper) layer stacked on each other.
  • the thickness of the Ti (titanium) layer is about 10 nm or more and 30 nm or less, and the thickness of the Cu (copper) layer is about 200 nm or more and 800 nm or less.
  • the constituent material and thickness of the base layer are not limited to those described above.
  • a plating layer in contact with the base layer is formed.
  • the plating layer is formed by forming a resist pattern by photolithography and electrolytic plating. Specifically, a photosensitive resist is applied so as to cover the entire surface of the underlayer, and the photosensitive resist is exposed and developed. This forms a patterned mask layer.
  • the photosensitive resist is applied, for example, using a spin coater, but is not limited to this.
  • a part of the underlayer is exposed from the mask layer.
  • electrolytic plating is performed using the underlayer as a conductive path.
  • a plating layer is precipitated on the underlayer exposed from the resist pattern.
  • the constituent material of the plating layer in this embodiment is, for example, Cu (copper).
  • the mask layer is removed. Through the above steps, a first metal layer 31A including a plurality of through wiring parts 310 is formed.
  • the first resin layer 21A is formed.
  • the first resin layer 21A is formed to cover the first metal layer 31A.
  • the process of forming the first resin layer 21A is, for example, by molding.
  • the first resin layer 21A has electrical insulation properties and is, for example, a synthetic resin whose main component is a black epoxy resin. Through this process, the first metal layer 31A is completely covered with the first resin layer 21A.
  • the first resin layer 21A is thinned from the z1 side opposite the semiconductor element 1 in the z direction.
  • the method of thinning is not limited, and in this embodiment, grinding is used, for example.
  • a mechanical grinding machine is used. Note that the grinding of the first resin layer 21A is not limited to grinding using a mechanical grinding machine.
  • the first resin layer 21A is ground until the through wiring portion 310 is exposed. By this process, the through wiring portion 310 is exposed from the seventh resin surface 207 of the first resin layer 21A.
  • a grinding mark which is a mark made by grinding with a grindstone, is formed on the seventh resin surface 207.
  • the grinding mark is formed across from the seventh resin surface 207 to the through wiring portion 310.
  • a part of the through wiring portion 310 is ground.
  • burrs may occur in the through wiring portion 310 due to the difference in material between the through wiring portion 310 and the first resin layer 21A.
  • a chemical treatment may be performed to remove the burrs.
  • the through wiring portion 310 may be slightly recessed toward the z2 side in the z direction from the seventh resin surface 207.
  • a mask layer 5 is formed.
  • a base layer (not shown) is formed on the seventh resin surface 207 and the through wiring portion 310.
  • the base layer is formed, for example, by a sputtering method.
  • a Ti (titanium) layer is formed to cover the first resin layer 21A and the through wiring portion 310, and then a Cu (copper) layer is formed in contact with the Ti (titanium) layer. Therefore, the base layer is formed from a Ti layer and a Cu layer stacked on top of each other.
  • the mask layer 5 has a plurality of openings 51.
  • the plurality of openings 51 expose the underlayer.
  • the plurality of openings 51 are sized, shaped, and positioned to correspond to the plurality of interconnect wiring sections 320.
  • a plating layer is deposited on the base layer exposed from the multiple openings 51 of the mask layer 5 by electrolytic plating using the base layer as a conductive path.
  • a metal layer containing, for example, Cu (copper) is deposited as the plating layer.
  • the plating layer is formed integrally with the base layer.
  • the mask layer 5 is removed. This forms the second metal layer 32A including the multiple interconnect wiring parts 320.
  • multiple conductive bonding materials 39 are formed.
  • the conductive bonding materials 39 are formed, for example, by electrolytic plating using the second metal layer 32A as a conductive path, to deposit the conductive bonding materials 39 on the second metal layer 32A exposed from the mask layer (not shown).
  • the conductive bonding materials 39 are formed by sequentially stacking a metal layer containing Cu (copper), a metal layer containing Ni (nickel), and an alloy layer containing Sn (tin).
  • the alloy layer containing Sn (tin) is, for example, a lead-free solder such as an Sn (tin)-Sb (antimony) alloy or an Sn (tin)-Ag (silver) alloy. After that, the mask layer formed in this process is removed.
  • a lead-free solder such as an Sn (tin)-Sb (antimony) alloy or an Sn (tin)-Ag (silver) alloy.
  • the semiconductor element 1 is mounted.
  • the semiconductor element 1 is mounted, for example, by flip chip bonding. Specifically, flux is applied to the semiconductor element 1, and then the multiple electrodes 12 of the semiconductor element 1 are temporarily attached onto the multiple conductive bonding materials 39, for example, using a flip chip bonder.
  • the conductive bonding materials 39 are then melted by reflow to bond with the multiple electrodes 12.
  • the conductive bonding materials 39 are then cooled and solidified.
  • the semiconductor element 1 is mounted on the second metal layer 32A, and the multiple electrodes 12 of the semiconductor element 1 are conductively bonded to the multiple interconnect wiring portions 320.
  • the second resin layer 22A is formed.
  • the second resin layer 22A has electrical insulation properties like the first resin layer 21A, and is a synthetic resin mainly made of, for example, black epoxy resin.
  • the second resin layer 22A that covers the semiconductor element 1, the first metal layer 31A, and the second metal layer 32A is formed on the seventh resin surface 207 of the first resin layer 21A.
  • the second resin layer 22A completely covers the semiconductor element 1 and the second metal layer 32A.
  • an underfill (not shown) mainly made of, for example, epoxy resin may be filled between the semiconductor element 1 and the seventh resin surface 207 of the first resin layer 21A.
  • the substrate 4 is removed.
  • grinding is performed using a mechanical grinder.
  • the grinding method is not limited to grinding using a mechanical grinder.
  • the substrate 4 is ground from the z1 side toward the z2 side in the z direction, and the substrate 4 is completely removed.
  • the substrate 4 is completely ground, and parts of the plurality of through-hole wiring portions 310 are also ground.
  • the second resin surface 202 is formed on the first resin layer 21A, and the back surface 311 is formed on the plurality of through-hole wiring portions 310.
  • the second resin surface 202 and the back surface 311 are flush with each other.
  • the substrate 4 is removed by peeling the glass substrate by chemical treatment or laser irradiation.
  • a number of recesses 291 are formed.
  • the multiple recesses 291 are formed, for example, by forming grooves from the z2 side in the z direction using a dicing blade Db1.
  • the recesses 291 are recessed from the second resin surface 202 to the z1 side in the z direction, and penetrate the first resin layer 21 and the second metal layer 32 to reach the second resin layer 22.
  • the multiple recesses 291 overlap the outline of the semiconductor device A1 to be formed by this manufacturing method when viewed in the z direction.
  • an end face 312 is formed in the through wiring portion 310.
  • the surface metal layer 33 is formed.
  • the process of forming the surface metal layer 33 is performed by electroless plating.
  • a Ni (nickel) layer, a Pd (palladium) layer, and an Au (gold) layer are deposited in this order by electroless plating.
  • a Ni layer is formed to cover the back surface 311 and end surface 312 of the through wiring portion 310, a Pd layer is formed on the Ni layer, and an Au layer is formed on the Pd layer.
  • the method of forming the surface metal layer 33 is not limited to this, and the Ni (nickel) layer and the Au (gold) layer may be deposited in this order, or only the Au (gold) layer may be formed, or only the Sn (tin) layer may be formed.
  • a cutting process is performed.
  • a dicing blade Db2 is used to cut along the multiple recesses 291.
  • the dicing blade Db2 is thinner than the dicing blade Db1. This causes the second resin layer 22A to be completely cut.
  • multiple semiconductor devices A1 are obtained.
  • the multiple recesses 291 remain as recesses 2051 and recesses 2061 in the semiconductor device A1.
  • the interconnect wiring section 320 has a portion that has an uneven shape when viewed in the z direction.
  • the contact area between the interconnect wiring section 320 and the sealing resin 2 (second resin layer 22) is increased. This makes it possible to suppress peeling between the wiring section 3 and the sealing resin 2.
  • the pair of first sides 323 have uneven portions.
  • the first sides 323 are close to the portions of the interconnection wiring portion 320 that are conductively joined to the multiple electrodes 12 of the semiconductor element 1.
  • the semiconductor, which is the main component of the semiconductor element 1, and the resin, which is the main component of the sealing resin 2 have different linear expansion coefficients. For this reason, if the semiconductor element 1 generates heat during operation of the semiconductor device A1, there is a risk that peeling will occur between the pair of first sides 323 and the sealing resin 2 (first resin layer 21). According to this embodiment, peeling at the pair of first sides 323 can be suppressed.
  • interconnect wiring section 320 having a concave-convex shape in the desired area.
  • mask layer 5 is formed by patterning using photolithography, for example, so fine processing is possible. Therefore, it is possible to more easily and reliably form an uneven shape of the desired shape and pitch in interconnect wiring section 320.
  • FIGS. 19 to 21 show other embodiments of the present disclosure.
  • elements that are the same as or similar to those in the above embodiment are given the same reference numerals as in the above embodiment.
  • the configurations of each part in each modified example and each embodiment can be combined with each other as appropriate to the extent that no technical contradictions arise.
  • Second embodiment: 19 shows a semiconductor device according to a second embodiment of the present disclosure.
  • the first edge 321 has an uneven shape.
  • the pitch of the uneven shape of the first edge 321 is the same as the pitch of the uneven shape of the first side 323, for example.
  • This embodiment also makes it possible to suppress peeling between the wiring portion 3 and the sealing resin 2. Furthermore, because the first edge 321 has an uneven shape, peeling between the wiring portion 3 and the sealing resin 2 inside the semiconductor device A1 can be further suppressed. Furthermore, as can be understood from this embodiment, there is no limitation as to which part of the connecting wiring portion 320 has an uneven shape, and for example, the first edge 321 may have an uneven shape and the first side 323 may not have an uneven shape.
  • Third embodiment 20 shows a semiconductor device according to a third embodiment of the present disclosure.
  • a portion of each of a pair of second sides 324 is formed in an uneven shape.
  • the pitch of the uneven shape of the second sides 324 is, for example, the same as the pitch of the uneven shape of the first side 323.
  • the portion of the second side 324 that is connected to the second edge 322 is formed in an uneven shape.
  • This embodiment also makes it possible to prevent peeling between the wiring portion 3 and the sealing resin 2. Furthermore, by including portions of the pair of second sides 324 that have an uneven shape, it is possible to prevent cracks that connect to the outside of the semiconductor device A1 from occurring between the sealing resin 2 and the wiring portion 3.
  • Fourth embodiment: 21 shows a semiconductor device according to a fourth embodiment of the present disclosure.
  • the portions of the interconnection portion 320 other than the second edge 322 are uneven. That is, the first edge 321, the pair of first sides 323, the pair of second sides 324, the multiple intermediate sides 325, and the multiple intermediate sides 326 are uneven.
  • This embodiment also makes it possible to suppress peeling between the wiring portion 3 and the sealing resin 2. Furthermore, this embodiment makes it possible to effectively suppress peeling between the sealing resin 2 and the wiring portion 3.
  • the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiment.
  • the specific configuration of the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure can be freely designed in various ways.
  • Appendix 1 A semiconductor element; A sealing resin; a wiring portion electrically connected to the semiconductor element, the sealing resin has a first resin surface facing a first side in a thickness direction and a second resin surface facing a second side; the wiring portion includes a first metal layer including a through wiring portion exposed from the second resin surface, and a second metal layer including a connecting wiring portion electrically connected to the through wiring portion and the semiconductor element, At least a portion of the interconnection portion has an uneven shape when viewed in the thickness direction.
  • the thickness of the interconnection portion is 10 ⁇ m or more and 60 ⁇ m or less, 2.
  • the semiconductor device according to claim 1, wherein the pitch of the concave and convex shapes is 15 ⁇ m or more and 100 ⁇ m or less.
  • the uneven shape is composed of a plurality of curved lines.
  • Appendix 4. the interconnection portion has a first end edge on a side conductively joined to the semiconductor element, and a pair of first sides extending from the first end edge; 4.
  • the semiconductor device according to claim 1, wherein the first side has an uneven shape when viewed in the thickness direction.
  • Appendix 5. The semiconductor device according to claim 4, wherein the first edge has an uneven shape when viewed in the thickness direction.
  • the interconnection portion has a second edge opposite to the first edge, and a pair of second sides extending from the second edge and overlapping with the through-hole wiring portion when viewed in the thickness direction;
  • the semiconductor device according to claim 4 or 5 wherein at least a portion of the second side has an uneven shape when viewed in the thickness direction.
  • Appendix 7. The semiconductor device according to claim 6, wherein a portion of the second side connected to the second end edge has an uneven shape when viewed in the thickness direction.
  • Appendix 8. 8.
  • the interconnection portion has a plurality of intermediate sides interposed between the pair of first sides and the pair of second sides,
  • Appendix 10. the sealing resin includes a first resin layer and a second resin layer laminated in the thickness direction, the first resin surface is constituted by the second resin layer, 10. The semiconductor device according to claim 1, wherein the second resin surface is constituted by the first resin layer. Appendix 11. 11. The semiconductor device according to claim 10, wherein the through wiring portion penetrates the first resin layer in the thickness direction.
  • Appendix 12. the first resin layer has a seventh resin surface in contact with the second resin layer, 12. The semiconductor device according to claim 10, wherein the second resin layer is formed on the seventh resin surface.
  • Appendix 13 10. The semiconductor device according to claim 9, wherein the through wiring portion has a back surface exposed from the second resin surface. Appendix 14. 14. The semiconductor device according to claim 13, wherein the wiring portion includes a surface metal layer covering the back surface. Appendix 15. 15. The semiconductor device according to claim 14, wherein the through wiring portion has an end surface that is exposed in a direction perpendicular to the thickness direction and is connected to the back surface. Appendix 16. 16. The semiconductor device of claim 15, wherein the surface metal layer covers the end faces. Appendix 17. the semiconductor element has an electrode facing the interconnection portion, 17. The semiconductor device according to claim 1, wherein the electrode is conductively joined to the interconnection portion via a conductive bonding material. Appendix 18.
  • a first metal layer having a plurality of through wiring portions on a substrate forming a first resin layer on the substrate to cover the first metal layer; a step of thinning the first resin layer from a side opposite to the substrate to expose the plurality of through wiring portions from the first resin layer; forming a mask layer having a plurality of openings on the first resin layer and the first metal layer; forming a second metal layer using the mask layer and electrically connecting to the first metal layer; mounting a semiconductor device on the second metal layer; forming a second resin layer on the first resin layer to cover the second metal layer and the semiconductor element; removing the substrate; Equipped with In the step of forming the mask layer, at least a portion of the opening is formed into an uneven shape.

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
PCT/JP2023/042179 2022-12-12 2023-11-24 半導体装置および半導体装置の製造方法 Ceased WO2024127945A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002270715A (ja) * 2001-03-09 2002-09-20 Sumitomo Bakelite Co Ltd 半導体装置の製造方法および半導体装置
JP2006093576A (ja) * 2004-09-27 2006-04-06 Hitachi Cable Ltd 半導体装置及びその製造方法
WO2007061112A1 (ja) * 2005-11-28 2007-05-31 Dai Nippon Printing Co., Ltd. 回路部材、回路部材の製造方法、及び、回路部材を含む半導体装置
JP2021005687A (ja) * 2019-06-27 2021-01-14 ローム株式会社 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002270715A (ja) * 2001-03-09 2002-09-20 Sumitomo Bakelite Co Ltd 半導体装置の製造方法および半導体装置
JP2006093576A (ja) * 2004-09-27 2006-04-06 Hitachi Cable Ltd 半導体装置及びその製造方法
WO2007061112A1 (ja) * 2005-11-28 2007-05-31 Dai Nippon Printing Co., Ltd. 回路部材、回路部材の製造方法、及び、回路部材を含む半導体装置
JP2021005687A (ja) * 2019-06-27 2021-01-14 ローム株式会社 半導体装置

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