WO2024079813A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024079813A1
WO2024079813A1 PCT/JP2022/038032 JP2022038032W WO2024079813A1 WO 2024079813 A1 WO2024079813 A1 WO 2024079813A1 JP 2022038032 W JP2022038032 W JP 2022038032W WO 2024079813 A1 WO2024079813 A1 WO 2024079813A1
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WO
WIPO (PCT)
Prior art keywords
elements
semiconductor
wiring
adjacent
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/038032
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English (en)
French (fr)
Japanese (ja)
Inventor
一廣 西村
英夫 河面
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to US18/872,707 priority Critical patent/US20250316657A1/en
Priority to PCT/JP2022/038032 priority patent/WO2024079813A1/ja
Priority to JP2024550966A priority patent/JP7738773B2/ja
Priority to CN202280100801.8A priority patent/CN120019492A/zh
Priority to DE112022007897.9T priority patent/DE112022007897T5/de
Publication of WO2024079813A1 publication Critical patent/WO2024079813A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/401—Resistive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/601—Capacitive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D80/00—Assemblies of multiple devices comprising at least one device covered by this subclass
    • H10D80/20—Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups H10D1/00 - H10D48/00, e.g. assemblies comprising capacitors, power FETs or Schottky diodes
    • H10D80/251—FETs covered by H10D30/00, e.g. power FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • This disclosure relates to a semiconductor device.
  • Patent Document 1 discloses a configuration in which wiring elements are provided separately from the semiconductor elements.
  • a wiring element is placed in the center of a base plate, and multiple semiconductor elements are placed to surround the wiring element, ensuring that the wire lengths of the semiconductor elements and wiring elements are uniform. This creates restrictions on the placement of the semiconductor elements and wiring elements, and on the routing of the external electrodes, resulting in a problem of low freedom of layout.
  • the present disclosure therefore aims to provide a technology that improves the degree of freedom in the layout of a semiconductor device equipped with multiple semiconductor elements, detects the temperature of the semiconductor elements while taking into account the heat distribution within the semiconductor device, and maximizes the effective area of the semiconductor elements.
  • the semiconductor device comprises a base plate, a plurality of semiconductor elements mounted on the base plate, each having a wire pad, and a plurality of wiring elements arranged on the base plate adjacent to the plurality of semiconductor elements, each having a wire pad, wherein a temperature sensor is arranged within each of the wiring elements to detect the temperature of an adjacent semiconductor element among the plurality of semiconductor elements, the wire pad of each of the wiring elements is arranged to face the wire pad of the adjacent semiconductor element, the temperature sensor of each of the wiring elements is arranged on the side of the adjacent semiconductor element, and the wire pad of each of the semiconductor elements and the wire pad of each of the wiring elements adjacent to each of the semiconductor elements are connected via a wire.
  • multiple wiring elements are arranged adjacent to multiple semiconductor elements, respectively, and the wire pads of each wiring element are arranged facing the wire pads of the adjacent semiconductor elements, so that the wires between the semiconductor elements and the wiring elements do not interfere with each other, and wiring can be performed with a certain wire length or less. This eliminates the need to arrange the semiconductor elements so as to surround the wiring elements, and improves the layout freedom of the semiconductor device compared to conventional methods.
  • a temperature sensor corresponding to each semiconductor element is placed inside each wiring element, so the semiconductor element that performs temperature detection can be selected taking into account the heat distribution inside the semiconductor device.
  • each wiring element is positioned on the side of the adjacent semiconductor element, it has good thermal coupling with the semiconductor element, resulting in good temperature detection accuracy for the semiconductor element. This makes it possible to eliminate the temperature sensor from the semiconductor element, maximizing the effective area of the semiconductor element.
  • FIG. FIG. 11 is an equivalent circuit diagram of a semiconductor device according to a second embodiment.
  • FIG. 11 is a top view of a semiconductor device according to a third embodiment.
  • FIG. 11 is a top view of a wiring element included in a semiconductor device according to a third embodiment. This is a cross-sectional view taken along line CC in Figure 11.
  • 11 is an equivalent circuit diagram of a semiconductor device and a control board when a high-voltage diode is provided on the control board.
  • FIG. 13 is an equivalent circuit diagram of a semiconductor device and a control board when a high-voltage diode is provided in the semiconductor device according to the third embodiment.
  • FIG. 13 is a top view of a wiring element included in a semiconductor device according to a fourth embodiment.
  • FIG. 13 is an equivalent circuit diagram of a wiring element included in a semiconductor device according to a fourth embodiment.
  • FIG. 13 is a top view of a semiconductor device according to a fifth embodiment.
  • FIG. 13 is a cross-sectional view of a semiconductor device according to a fifth embodiment.
  • FIG. 13 is a top
  • FIG. 1 is a top view of a semiconductor device 100 according to the first embodiment.
  • FIG. 2 is a cross-sectional view of the semiconductor device 100 according to the first embodiment.
  • FIG. 3 is a top view of a wiring element 10 included in the semiconductor device 100 according to the first embodiment.
  • FIG. 4 is a cross-sectional view taken along line A-A in FIG. 3.
  • FIG. 5 is a cross-sectional view taken along line B-B in FIG. 3.
  • FIG. 6 is an equivalent circuit diagram of the semiconductor device 100 according to the first embodiment. Note that in FIG. 2, the extending direction of the external electrode 20 and the control terminal 22 has been changed in order to make it easier to see the connection relationship of the respective members.
  • the semiconductor device 100 includes a base plate 1, multiple (e.g., three) semiconductor elements 2, multiple (e.g., three) wiring elements 10, an external electrode 20, and four control terminals 22.
  • the base plate 1 is mainly made of metals such as Cu and Al.
  • the base plate 1 is formed in a rectangular shape when viewed from above, and functions as a drain terminal.
  • the base plate 1 is also referred to as the drain terminal 1.
  • Each semiconductor element 2 is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the surface electrode of each semiconductor element 2 is divided into two areas: an area where a main terminal electrode 3 through which a main current flows is located, and an area where wire pads 4 for transmitting drive voltage, temperature, and overcurrent signals of each semiconductor element 2 are located.
  • the area where the wire pads 4 are located is on the right side in FIG. 1 (the wiring element 10 side), and the area where the main terminal electrodes 3 are located is on the left side in FIG. 1.
  • Each semiconductor element 2 may be a semiconductor switching element other than a MOSFET, such as an IGBT (Insulated Gate Bipolar Transistor) or a reverse conducting IGBT.
  • IGBT Insulated Gate Bipolar Transistor
  • the multiple wiring elements 10 are arranged on the base plate 1 so as to be adjacent to each of the multiple semiconductor elements 2.
  • the multiple wiring elements 10 are arranged on the base plate 1 by bonding their back surfaces via a conductive bonding material 5.
  • a resistor 14 that suppresses the oscillation action of an adjacent semiconductor element 2 among the multiple semiconductor elements 2, and a diode 13 that serves as a temperature sensor that detects the temperature of the adjacent semiconductor element 2.
  • the diode 13 of each wiring element 10 is arranged on the side of the adjacent semiconductor element 2.
  • the external electrode 20 is made of Cu, is disposed on the main terminal electrodes 3 of the multiple semiconductor elements 2, and connects the multiple semiconductor elements 2.
  • the main terminal electrodes 3 function as source terminals, and the external electrode 20 disposed on the main terminal electrodes 3 also functions as a source terminal.
  • the external electrode 20 is also referred to as the source terminal 20.
  • the multiple semiconductor elements 2 are connected in parallel, and the multiple wiring elements 10 are connected to the multiple semiconductor elements 2 while being adjacent to each of the multiple semiconductor elements 2.
  • the four control terminals 22 are terminals for inputting and outputting signals related to the control of each semiconductor element 2.
  • the four control terminals 22 are a current sense terminal 22a, a Kelvin source terminal 22b, a gate terminal 22c, and a temperature sense anode terminal 22d, and are connected to each semiconductor element 2 via each wiring element 10.
  • a current sense method is adopted as a short circuit detection method for detecting a short circuit state of the semiconductor element 2.
  • each wiring element 10 has a Si substrate 11 as a base material, and a back electrode 15 made of Al, Ti, Ni, or Au is formed on the back surface of the Si substrate 11.
  • the back surface of each wiring element 10 is bonded to the base plate 1 via a conductive bonding material 5, similar to the semiconductor element 2.
  • a thermal oxide film 16 is formed on the surface of the Si substrate 11, and passive elements such as a resistor 14 made of polycrystalline polysilicon (Poly-Si) 18 and a diode 13 made of polycrystalline polysilicon (P-type) 18a and polycrystalline polysilicon (N-type) 18b are formed on the thermal oxide film 16.
  • a resistor 14 made of polycrystalline polysilicon (Poly-Si) 18 and a diode 13 made of polycrystalline polysilicon (P-type) 18a and polycrystalline polysilicon (N-type) 18b are formed on the thermal oxide film 16.
  • an insulating interlayer film 17 is formed on the thermal oxide film 16 and the polycrystalline polysilicon 18, 18a, 18b.
  • a wire pad 12 made of Al is formed on the insulating interlayer film 17 as a surface electrode.
  • a contact portion 17a is provided in a portion of the insulating interlayer film 17 for electrically connecting the resistor 14 and the diode 13 to the wire pad 12 as a surface electrode.
  • the wire pad 4 of the semiconductor element 2 is connected to the control terminal 22 via the wiring element 10, and the wiring element 10 has a function of relaying wiring. Therefore, as shown in FIG. 1, FIG. 4, and FIG. 5, the surface of the wiring element 10 is provided with a wire pad 12 for connecting the wire pad 4 of the semiconductor element 2 and the control terminal 22 with a wire 21.
  • the wire pad 12 of each wiring element 10 is arranged so as to face the wire pad 4 of the adjacent semiconductor element 2, and is also arranged in other places.
  • the wire pad 4 of each semiconductor element 2 and the wire pad 12 of each wiring element 10 adjacent to each semiconductor element 2 are connected via the wire 21.
  • the inside of the semiconductor device 100 is sealed with a sealing material (not shown) made of epoxy resin or the like to ensure electrical insulation.
  • the wiring element is placed in the center of the base plate, and multiple semiconductor elements are placed to surround the wiring element, so that the wire lengths between the semiconductor element and the wiring element are uniform.
  • restrictions are imposed on the placement of the semiconductor element and the wiring element, and on the routing of the external electrodes, resulting in a problem of low freedom of layout.
  • the semiconductor device 100 includes a base plate 1, a plurality of semiconductor elements 2 mounted on the base plate 1 and each having a wire pad 4, and a plurality of wiring elements 10 arranged on the base plate 1 adjacent to the plurality of semiconductor elements 2, each having a wire pad 12.
  • a diode 13 is arranged in each wiring element 10 as a temperature sensor for detecting the temperature of an adjacent semiconductor element 2 among the plurality of semiconductor elements 2.
  • the wire pad 12 of each wiring element 10 is arranged so as to face the wire pad 4 of the adjacent semiconductor element 2.
  • the diode 13 as a temperature sensor of each wiring element 10 is arranged on the side of the adjacent semiconductor element 2.
  • the wire pad 4 of each semiconductor element 2 and the wire pad 12 of each wiring element 10 adjacent to each semiconductor element 2 are connected via a wire 21.
  • the multiple wiring elements 10 are arranged adjacent to the multiple semiconductor elements 2, respectively, and the wire pads 12 of each wiring element 10 are arranged facing the wire pads 4 of the adjacent semiconductor element 2, so that the wires 21 between the semiconductor elements 2 and the wiring elements 10 do not interfere with each other, and wiring can be performed with a certain wire length or less. This eliminates the need to arrange the semiconductor elements 2 so as to surround the wiring elements 10, and improves the layout freedom of the semiconductor device 100 compared to conventional methods.
  • a diode 13 is disposed in each wiring element 10 as a temperature sensor corresponding to each semiconductor element 2, so that the semiconductor element 2 for temperature detection can be selected taking into account the heat distribution within the semiconductor device 100.
  • the diode 13 acting as a temperature sensor for each wiring element 10 is arranged on the side of the adjacent semiconductor element 2, so that the thermal coupling with the semiconductor element 2 is good, and the temperature detection accuracy of the semiconductor element 2 is good. This makes it possible to eliminate the temperature sensor from the semiconductor element 2, thereby maximizing the effective area of the semiconductor element 2.
  • each wiring element 10 further includes a resistor 14 for suppressing oscillation of the adjacent semiconductor elements 2, so there is no need to provide a balance resistor in the semiconductor elements 2, and malfunction and destruction of the semiconductor device 100 can be suppressed at low cost.
  • a semiconductor device 100A according to a second embodiment will be described.
  • Fig. 7 is a top view of the semiconductor device 100A according to the second embodiment.
  • Fig. 8 is a top view of a wiring element 10A included in the semiconductor device 100A according to the second embodiment.
  • Fig. 9 is an equivalent circuit diagram of the semiconductor device 100A according to the second embodiment. Note that in the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals and description thereof will be omitted.
  • the short circuit detection method for detecting the short circuit state of the semiconductor element 2 is changed from the current sense method to the non-saturated voltage detection method. Therefore, instead of the current sense terminal 22a (see FIG. 1), a non-saturated voltage detection output terminal 22e is arranged as the control terminal 22 to take out the non-saturated voltage (drain voltage) of each semiconductor element 2 to the outside.
  • the non-saturated voltage detection output terminal 22e is connected to the drain terminal 1.
  • the semiconductor device 100A according to the second embodiment further includes a control terminal 22 for inputting and outputting signals related to the control of each semiconductor element 2, and the control terminal 22 includes a non-saturation voltage detection output terminal 22e for extracting the drain voltage of each semiconductor element 2 to the outside.
  • the current sensing elements 4a of each semiconductor element 2 and the current sensing paths of the wiring elements 10 can be reduced, realizing a reduction in cost of the semiconductor device 100A without compromising the protective function of the semiconductor element 2.
  • Fig. 10 is a top view of a semiconductor device 100B according to the third embodiment.
  • Fig. 11 is a top view of a wiring element 10B included in the semiconductor device 100B according to the third embodiment.
  • Fig. 12 is a cross-sectional view taken along line CC in Fig. 11. Note that in the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals, and description thereof will be omitted.
  • a high-voltage diode 19 is disposed in each wiring element 10B to insulate the non-saturated voltage detection output terminal 22e for extracting the drain voltage of the adjacent semiconductor element 2 to the outside.
  • An N- layer 29, an N + layer 30, a P- layer 31, and a P + layer 32 are formed in the Si substrate 11.
  • FIG. 13 is an equivalent circuit diagram of the semiconductor device and the control board when the high-voltage diode 19 is provided on the control board.
  • FIG. 14 is an equivalent circuit diagram of the semiconductor device 100B and the control board when the high-voltage diode 19 is provided in the semiconductor device 100B according to the third embodiment.
  • control board is provided with a high-voltage diode 19 in addition to a control IC 33, resistor 34, and capacitor 35, and it is necessary to provide high-voltage wiring at the point on the control board that is connected to the desaturation voltage detection output terminal 22e.
  • the desaturation voltage detection output terminal 22e is electrically insulated within the semiconductor device 100B, eliminating the need to provide high-voltage wiring on the control board, which can lead to a smaller control board and improved layout flexibility.
  • the saturation voltage V DS of a MOSFET has a positive temperature characteristic in which the absolute value increases as the temperature increases, so the higher the environmental temperature, the higher the overcurrent determination threshold V DESAT .
  • the control IC 33 monitors the overcurrent determination threshold V DESAT , and when it exceeds a certain level, it transitions to overcurrent protection operation. However, since there is a limit to the monitoring range of the control IC 33, if the overcurrent determination threshold V DESAT becomes too high at high temperatures, it affects the operating temperature range of the overcurrent protection circuit.
  • the temperature of the high-voltage diode 19 rises more than in the case of Fig. 13.
  • the forward voltage VF of the high-voltage diode 19 has a negative temperature characteristic that decreases as the temperature increases, and acts in a direction that cancels the saturation voltage temperature characteristic of the MOSFET, improving the detection accuracy of the overcurrent determination threshold VDESAT .
  • Fig. 15 is a top view of a wiring element 10C included in the semiconductor device according to the fourth embodiment.
  • Fig. 16 is an equivalent circuit diagram of the wiring element 10C included in the semiconductor device according to the fourth embodiment. Note that in the fourth embodiment, the same components as those described in the first to third embodiments are denoted by the same reference numerals and description thereof will be omitted.
  • a protection diode 24 is added to the first embodiment. Specifically, as shown in Figs. 15 and 16, a protection diode 24 is arranged in each wiring element 10C to protect the adjacent semiconductor element 2 from electrostatic breakdown. Specifically, in each wiring element 10C, a protection diode 24 is arranged between the gate terminal G and the Kelvin source terminal KS, and between the current sense terminal CS and the Kelvin source terminal KS.
  • the gate terminal G, the Kelvin source terminal KS, the current sense terminal CS, and the temperature sense anode terminal A in Figs. 15 and 16 are connected to the gate terminal 22c, the Kelvin source terminal 22b, the current sense terminal 22a, and the temperature sense anode terminal 22d in Fig. 1, respectively, via wires 21.
  • a semiconductor device 100D according to a fifth embodiment will be described.
  • Fig. 17 is a top view of the semiconductor device 100D according to the fifth embodiment.
  • Fig. 18 is a cross-sectional view of the semiconductor device 100D according to the fifth embodiment. Note that in the fifth embodiment, the same components as those described in the first to fourth embodiments are denoted by the same reference numerals, and the description thereof will be omitted.
  • the wiring elements 10 are arranged at locations on the external electrode 20 corresponding to each of the semiconductor elements 2 so as to be adjacent to and above each of the semiconductor elements 2 with the external electrode 20 in between.
  • the wiring elements 10 are arranged on the external electrode 20 by bonding their back surfaces via a conductive bonding material 5.
  • each wiring element 10 a resistor 14 is arranged to suppress the oscillation of the semiconductor element 2 adjacent to the lower side across the external electrode 20, and a diode 13 is arranged as a temperature sensor to detect the temperature of the semiconductor element 2 adjacent to the lower side across the external electrode 20.
  • the wire pad 12 of each wiring element 10 is arranged to face the wire pad 4 of the semiconductor element 2 adjacent to the lower side across the external electrode 20, and is also arranged in other places.
  • the diode 13 of each wiring element 10 is arranged on the side of the semiconductor element 2 adjacent to the lower side across the external electrode 20.
  • the wire pad 4 of each semiconductor element 2 and the wire pad 12 of each wiring element 10 adjacent to the upper side of each semiconductor element 2 are connected via a wire 21.
  • the degree of freedom of layout is improved, and the temperature of the semiconductor element 2 is detected while taking into account the heat distribution within the semiconductor device 100D, and the effective area of the semiconductor element 2 can be maximized.
  • the multiple wiring elements 10 are arranged at locations on the external electrode 20 corresponding to each of the multiple semiconductor elements 2 so as to be adjacent to the upper side of each of the multiple semiconductor elements 2 with the external electrode 20 in between, the area of the base plate 1 can be reduced more than in the case of embodiment 1. This allows the semiconductor device 100D to be made smaller.
  • FIG. 19 is a top view of the semiconductor device 100E according to the sixth embodiment. Note that in the sixth embodiment, the same components as those described in the first to fifth embodiments are denoted by the same reference numerals, and the description thereof will be omitted.
  • the multiple wiring elements 10 are arranged on the upper surface of the external electrodes 20 that are arranged in the area where the main terminal electrodes 3 of each semiconductor element 2 are arranged.
  • the main terminal electrode 3 which is the surface electrode of each semiconductor element 2, is divided into two regions 3a and 3b.
  • Multiple wiring elements 10 are arranged in one region 3a, and external electrodes 20 are arranged in the other region 3b.
  • the wiring elements 10 are bonded to one region 3a of each of the semiconductor elements 2 via a conductive bonding material (not shown) so as to be adjacent to and above each of the semiconductor elements 2.
  • the external electrodes 20 are bonded to the other region 3b of each of the semiconductor elements 2 via a conductive bonding material (not shown).
  • each wiring element 10 a resistor 14 is arranged to suppress the oscillation of the semiconductor element 2 adjacent below among the multiple semiconductor elements 2, and a diode 13 is arranged as a temperature sensor to detect the temperature of the semiconductor element 2 adjacent below.
  • the wire pad 12 of each wiring element 10 is arranged to face the wire pad 4 of the semiconductor element 2 adjacent below, and is also arranged in other places.
  • the diode 13 of each wiring element 10 is arranged on the side of the semiconductor element 2 adjacent below.
  • the wire pad 4 of each semiconductor element 2 and the wire pad 12 of each wiring element 10 adjacent above each semiconductor element 2 are connected via wires 21.
  • the degree of freedom of layout is improved, and the temperature of the semiconductor element 2 is detected while taking into account the heat distribution within the semiconductor device 100E, and the effective area of the semiconductor element 2 can be maximized.
  • each semiconductor element 2 is divided into two regions 3a and 3b, with each wiring element 10 arranged in one region 3a and the external electrode 20 arranged in the other region 3b, so that the thermal coupling between the wiring elements 10 and the semiconductor element 2 is improved compared to the fifth embodiment, and the temperature detection accuracy of the semiconductor element 2 is improved.
  • the number of the semiconductor elements 2 and the number of the wiring elements 10, 10A, 10B, 10C are each described as three, but this is not limited thereto, and it is sufficient that the number of each is two or more and the same.
  • the same number of wiring elements 10, 10A, 10B, 10C as the semiconductor elements 2 are arranged, but the number of wiring elements 10, 10A, 10B, 10C does not have to be the same as the semiconductor elements 2, and two or more wiring elements 10, 10A, 10B, 10C may be configured on one Si substrate 11.
  • a capacitor made of a silicon oxide film or an insulating interlayer film may be formed in each of the wiring elements 10, 10A, 10B, and 10C.
  • a capacitor made of a silicon oxide film or an insulating interlayer film may be formed in each of the wiring elements 10, 10A, 10B, and 10C.
  • the resistors 14 arranged in each of the wiring elements 10, 10A, 10B, and 10C may have a resistance value adjustable by laser trimming. This makes it possible to suppress variations in the balance resistors connected between each of the semiconductor elements 2.
  • the risk of oscillation increases if there is a large difference in the values of the balance resistors connected to each of the semiconductor elements 2.
  • the variation in the resistance values is reduced, the risk of oscillation is reduced and malfunction of the semiconductor elements 2 can be suppressed.
  • protection diode 24 of embodiment 4 can be used in embodiments 2 and 3, and the desaturation voltage detection output terminal 22e of embodiment 2, the high-voltage diode 19 of embodiment 3, and the protection diode 24 of embodiment 4 can be used in embodiments 5 and 6.
  • each embodiment can be freely combined, modified, or omitted as appropriate.

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  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
PCT/JP2022/038032 2022-10-12 2022-10-12 半導体装置 Ceased WO2024079813A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US18/872,707 US20250316657A1 (en) 2022-10-12 2022-10-12 Semiconductor device
PCT/JP2022/038032 WO2024079813A1 (ja) 2022-10-12 2022-10-12 半導体装置
JP2024550966A JP7738773B2 (ja) 2022-10-12 2022-10-12 半導体装置
CN202280100801.8A CN120019492A (zh) 2022-10-12 2022-10-12 半导体装置
DE112022007897.9T DE112022007897T5 (de) 2022-10-12 2022-10-12 Halbleitervorrichtung

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11214304A (ja) * 1998-01-21 1999-08-06 Murata Mfg Co Ltd 半導体装置およびそれを用いた電子装置
JP2001267493A (ja) * 2000-03-21 2001-09-28 Sanyo Electric Co Ltd 半導体装置
JP2001284395A (ja) * 2000-03-31 2001-10-12 Sanken Electric Co Ltd 半導体装置
JP2008211237A (ja) * 2008-04-18 2008-09-11 Fujitsu Ltd 半導体装置に配設される中継部材及び半導体装置
WO2019202687A1 (ja) * 2018-04-18 2019-10-24 三菱電機株式会社 半導体モジュール

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4138192B2 (ja) * 1999-12-27 2008-08-20 三菱電機株式会社 半導体スイッチ装置
JP4384948B2 (ja) * 2004-07-26 2009-12-16 株式会社日立製作所 パワーモジュール
JP5206188B2 (ja) * 2008-07-15 2013-06-12 三菱電機株式会社 半導体装置
JP7077893B2 (ja) * 2018-09-21 2022-05-31 株式会社デンソー 半導体装置
JP7428017B2 (ja) * 2020-03-06 2024-02-06 富士電機株式会社 半導体モジュール
JP7567191B2 (ja) * 2020-03-27 2024-10-16 富士電機株式会社 半導体モジュール
US12040263B2 (en) * 2020-09-30 2024-07-16 Stmicroelectronics S.R.L. Semiconductor device with die mounted to an insulating substrate and corresponding method of manufacturing semiconductor devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11214304A (ja) * 1998-01-21 1999-08-06 Murata Mfg Co Ltd 半導体装置およびそれを用いた電子装置
JP2001267493A (ja) * 2000-03-21 2001-09-28 Sanyo Electric Co Ltd 半導体装置
JP2001284395A (ja) * 2000-03-31 2001-10-12 Sanken Electric Co Ltd 半導体装置
JP2008211237A (ja) * 2008-04-18 2008-09-11 Fujitsu Ltd 半導体装置に配設される中継部材及び半導体装置
WO2019202687A1 (ja) * 2018-04-18 2019-10-24 三菱電機株式会社 半導体モジュール

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