DE112022007897T5 - Halbleitervorrichtung - Google Patents

Halbleitervorrichtung

Info

Publication number
DE112022007897T5
DE112022007897T5 DE112022007897.9T DE112022007897T DE112022007897T5 DE 112022007897 T5 DE112022007897 T5 DE 112022007897T5 DE 112022007897 T DE112022007897 T DE 112022007897T DE 112022007897 T5 DE112022007897 T5 DE 112022007897T5
Authority
DE
Germany
Prior art keywords
elements
wiring
semiconductor
adjacent
semiconductor elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE112022007897.9T
Other languages
German (de)
English (en)
Inventor
Kazuhiro Nishimura
Hideo KOMO
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE112022007897T5 publication Critical patent/DE112022007897T5/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00Arrangements for thermal protection or thermal control
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00Arrangements for protection of devices
    • H10W42/60Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00Electrical arrangements for controlling or matching impedance
    • H10W44/401Resistive arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00Electrical arrangements for controlling or matching impedance
    • H10W44/601Capacitive arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/401Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D80/00Assemblies of multiple devices comprising at least one device covered by this subclass
    • H10D80/20Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups H10D1/00 - H10D48/00, e.g. assemblies comprising capacitors, power FETs or Schottky diodes
    • H10D80/251FETs covered by H10D30/00, e.g. power FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/853On the same surface
    • H10W72/865Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
DE112022007897.9T 2022-10-12 2022-10-12 Halbleitervorrichtung Pending DE112022007897T5 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/038032 WO2024079813A1 (ja) 2022-10-12 2022-10-12 半導体装置

Publications (1)

Publication Number Publication Date
DE112022007897T5 true DE112022007897T5 (de) 2025-07-24

Family

ID=90669206

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112022007897.9T Pending DE112022007897T5 (de) 2022-10-12 2022-10-12 Halbleitervorrichtung

Country Status (5)

Country Link
US (1) US20250316657A1 (https=)
JP (1) JP7738773B2 (https=)
CN (1) CN120019492A (https=)
DE (1) DE112022007897T5 (https=)
WO (1) WO2024079813A1 (https=)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11214304A (ja) * 1998-01-21 1999-08-06 Murata Mfg Co Ltd 半導体装置およびそれを用いた電子装置
JP4138192B2 (ja) * 1999-12-27 2008-08-20 三菱電機株式会社 半導体スイッチ装置
JP3491885B2 (ja) * 2000-03-21 2004-01-26 三洋電機株式会社 半導体装置
JP2001284395A (ja) * 2000-03-31 2001-10-12 Sanken Electric Co Ltd 半導体装置
JP4384948B2 (ja) * 2004-07-26 2009-12-16 株式会社日立製作所 パワーモジュール
JP4774075B2 (ja) * 2008-04-18 2011-09-14 富士通セミコンダクター株式会社 半導体装置に配設される中継部材及び半導体装置
JP5206188B2 (ja) * 2008-07-15 2013-06-12 三菱電機株式会社 半導体装置
JP6897869B2 (ja) * 2018-04-18 2021-07-07 三菱電機株式会社 半導体モジュール
JP7077893B2 (ja) * 2018-09-21 2022-05-31 株式会社デンソー 半導体装置
JP7428017B2 (ja) * 2020-03-06 2024-02-06 富士電機株式会社 半導体モジュール
JP7567191B2 (ja) * 2020-03-27 2024-10-16 富士電機株式会社 半導体モジュール
US12040263B2 (en) * 2020-09-30 2024-07-16 Stmicroelectronics S.R.L. Semiconductor device with die mounted to an insulating substrate and corresponding method of manufacturing semiconductor devices

Also Published As

Publication number Publication date
US20250316657A1 (en) 2025-10-09
CN120019492A (zh) 2025-05-16
WO2024079813A1 (ja) 2024-04-18
JPWO2024079813A1 (https=) 2024-04-18
JP7738773B2 (ja) 2025-09-12

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Legal Events

Date Code Title Description
R012 Request for examination validly filed
R079 Amendment of ipc main class

Free format text: PREVIOUS MAIN CLASS: H01L0025180000

Ipc: H10W0090000000