WO2024000663A1 - 显示面板和电子装置 - Google Patents

显示面板和电子装置 Download PDF

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Publication number
WO2024000663A1
WO2024000663A1 PCT/CN2022/105527 CN2022105527W WO2024000663A1 WO 2024000663 A1 WO2024000663 A1 WO 2024000663A1 CN 2022105527 W CN2022105527 W CN 2022105527W WO 2024000663 A1 WO2024000663 A1 WO 2024000663A1
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WIPO (PCT)
Prior art keywords
sub
layer
stack
substrate
opening
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PCT/CN2022/105527
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English (en)
French (fr)
Inventor
黄灿
陈中明
刘娜
郑辉
刘生泽
鲜于文旭
张春鹏
Original Assignee
武汉华星光电半导体显示技术有限公司
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Publication of WO2024000663A1 publication Critical patent/WO2024000663A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H10K50/858—Arrangements for extracting light from the devices comprising refractive means, e.g. lenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and an electronic device.
  • a transparent display screen means that the display itself has a certain degree of penetration and can clearly show the background behind the panel.
  • Transparent displays are suitable for a variety of application scenarios such as building windows, car windows, and store windows. In addition to the original transparent display function, they also have the potential to be used as information displays in the future, so they have attracted market attention.
  • the transparent display screen also includes multiple insulating layers and conductive layers made of different materials. The existence of these film layers will inevitably affect the transmittance of the transparent display screen.
  • the present application provides a display panel and electronic device to alleviate the technical problem of poor penetration rate of existing transparent display screens.
  • An embodiment of the present application provides a display panel, which includes pixel areas and transparent areas between the pixel areas.
  • the display panel further includes:
  • a first stacked layer is disposed on the base substrate
  • an opening is provided on the second stack corresponding to the transparent area, and the opening penetrates the second stack and the first stack, and penetrates at least part of the base substrate.
  • the opening includes a first sub-hole, a second sub-hole and a third sub-hole that penetrate each other, the first sub-hole penetrates the second laminate, and the The second sub-hole penetrates the first stack, and the third sub-hole penetrates at least part of the base substrate.
  • the opening size of the opening of the third sub-hole close to the side of the first stack is larger than the opening size of the opening of the second sub-hole close to the side of the base substrate.
  • the opening size of the opening of the first sub-hole close to the second sub-hole is larger than the opening size of the opening of the second sub-hole close to the first sub-hole.
  • the base substrate includes a first substrate disposed close to the first laminate, the first laminate is disposed on the first substrate, and the third Three sub-holes penetrate part of the first substrate.
  • the base substrate includes a first substrate and a second substrate, the first stack is provided on the first substrate, and the second substrate is located on The first substrate is on a side away from the first stack, and the third sub-hole penetrates the first substrate and exposes part of the second substrate.
  • the base substrate further includes a first barrier layer located between the first substrate and the second substrate, and the third sub-hole penetrates the first substrate. bottom and expose part of the first barrier layer.
  • the second stack includes a planarization layer located above the first stack, and a pixel definition located on a side of the planarization layer away from the first stack. layer, a pixel opening is provided on the pixel definition layer corresponding to the pixel area;
  • the display panel further includes a light-emitting layer located in the pixel opening and an organic auxiliary layer located on a side of the light-emitting layer close to the planarization layer.
  • the organic auxiliary layer also extends to the opening of the transparent area. hole, and is disconnected between the third sub-hole and the second sub-hole.
  • the display panel further includes:
  • a first electrode is located on the planarization layer in the pixel area, and the pixel opening exposes part of the first electrode;
  • a second electrode is located on the side of the light-emitting layer away from the first electrode, and the second electrode extends to the transparent area, and is provided with a notch at a position corresponding to the opening;
  • An encapsulation layer is provided on the side of the second electrode away from the light-emitting layer.
  • the encapsulation layer includes a first sub-encapsulation layer and a second sub-encapsulation layer arranged in a stack, wherein the first sub-encapsulation layer extends into the opening and covers it.
  • the second sub-encapsulation layer fills the opening.
  • the display panel further includes a transparent filler filled in the opening, and the encapsulation layer covers the transparent filler.
  • An embodiment of the present application also provides an electronic device, which includes the display panel of one of the foregoing embodiments.
  • the display panel includes a pixel area and a transparent area between the pixel areas, and the display panel further includes a first stack and a second layer disposed on a base substrate. Stacked layer, an opening is provided on the second stacked layer corresponding to the transparent area, the opening penetrates the second stacked layer and the first stacked layer, and penetrates at least part of the base substrate .
  • This application solves the problem of poor transmittance of existing transparent display screens by arranging openings in the transparent area to remove the first stacked layer in the transparent area to improve the transmittance of the transparent area.
  • FIG. 1 is a schematic top structural view of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 3 is a schematic diagram of the detailed structure of the opening provided by the embodiment of the present application.
  • FIG. 4 is another schematic cross-sectional structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 5 is another schematic cross-sectional structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a top view of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a display panel provided by an embodiment of the present application. A detailed structural diagram of the opening is provided.
  • the display panel 100 includes a pixel area PA and a transparent area TA located between the pixel areas PA.
  • Each of the pixel areas PA includes at least three sub-pixels of different colors, such as a red sub-pixel R and a green sub-pixel G. and blue sub-pixel B.
  • the transparent area TA is located between the pixel areas PA, and external ambient light can pass through the transparent area TA to achieve transparent display of the display panel 100 .
  • the display panel 100 also includes a wiring area LA, and the wiring area LA is provided with signal lines such as gate scanning lines, data lines, and power lines for connecting the sub-pixels of the pixel area PA.
  • the transparent area TA is specifically arranged in an area other than the pixel area PA and the wiring area LA, so that the transparent area TA avoids the wiring area LA and the pixel area PA.
  • the display panel 100 further includes a base substrate 10, a first stack 20 and a second stack 30 disposed on the base substrate 10, and the second stack 30 is disposed on the first The side of the stack 20 away from the base substrate 10 .
  • an opening 31 is provided on the second stack 30 corresponding to the transparent area TA, and the opening 31 penetrates the second stack 30 and the first stack 20 and penetrates at least part of it.
  • the base substrate 10 The first stack 20 is an inorganic stack, and the second stack 30 is an organic stack.
  • the opening 31 penetrating at least part of the base substrate 10 means that the opening 31 penetrates the surface of the base substrate 10 close to the first stack 20 and extends to The opening 31 does not penetrate the base substrate 10 but does not penetrate the surface of the base substrate 10 away from the first stack 20 . That is, the opening 31 does not penetrate the base substrate 10 .
  • the display panel 100 includes a first stack 20 and a second stack 30 disposed on a base substrate 10 , wherein a transistor 40 and a transistor 40 are disposed on the base substrate 10 in the pixel area PA.
  • the light-emitting unit is provided in the transparent area TA with the opening 31 penetrating the second stack 30 , the first stack 20 and part of the base substrate 10 .
  • the transistor 40 is used to drive the light-emitting unit to emit light.
  • the light-emitting unit includes a first electrode 51 , a second electrode 54 , a light-emitting layer 52 and an organic auxiliary layer 53 sandwiched between the first electrode 51 and the second electrode 54 .
  • FIG. 2 only illustrates one sub-pixel of the pixel area PA and one transistor 40 of the one sub-pixel, but the application is not limited thereto.
  • One sub-pixel of the application may include at least two transistors, such as one switching transistor and a driver transistor.
  • the transistor 40 and the first stack 20 are both disposed on the base substrate 10 , and the base substrate 10 includes a first substrate 11 disposed close to the first stack 20 .
  • the material of the first substrate 11 includes flexible film materials such as polyimide (PI).
  • the material of the first substrate 11 may also be a highly permeable flexible film material such as clear polyimide (CPI).
  • the transistor 40 includes an active layer 41 , a gate electrode 42 , a drain electrode 44 and a drain electrode 44 .
  • the first stack 20 includes a stacked second barrier layer 21 , a gate insulating layer 22 and an interlayer insulating layer 23 .
  • the second barrier layer 21 is located on the first substrate 11
  • the active layer 41 of the transistor 40 is located on the second barrier layer 21 .
  • the second barrier layer 21 can prevent undesired impurities or contaminants (eg, moisture, oxygen, etc.) from diffusing from the first substrate 11 into devices that may be damaged by these impurities or contaminants.
  • the material of the second barrier layer 21 includes inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc.
  • a buffer layer 24 may be disposed between the second barrier layer 21 and the active layer 41 , and the buffer layer 24 may further prevent undesired impurities or contaminants (such as moisture, oxygen, etc.) Diffusion from the first substrate 11 into devices that may be damaged by these impurities or contaminants, and the buffer layer 24 may also provide a flat top surface.
  • the buffer layer 24 may be made of the same material as the second barrier layer 21 , such as silicon oxide, silicon nitride, silicon oxynitride and other inorganic materials.
  • the active layer 41 is disposed on the buffer layer 24 , and the active layer 41 includes a channel and source and drain regions located on both sides of the channel.
  • the material of the active layer 41 includes, for example, indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO) Or oxide semiconductor materials such as indium tin zinc oxide (ITZO).
  • the gate insulating layer 22 covers the active layer 41 and the second barrier layer 21 .
  • the gate insulating layer 22 Covered on the active layer 41 and the buffer layer 24 .
  • the material of the gate insulating layer 22 may also include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the gate electrode 42 of the transistor 40 is located on the gate insulating layer 22 , and the gate electrode 42 is disposed corresponding to the channel of the active layer 41 .
  • other signal lines such as gate scanning lines provided in the same layer as the gate electrode 42 may also be formed, and the gate scanning lines are located in the wiring area LA.
  • the gate 42 is electrically connected to the gate scanning line.
  • “same layer arrangement” in this application means that in the preparation process, film layers formed of the same material are patterned to obtain at least two different features, then the at least two different features are the same. Layer settings. For example, if the gate electrode 42 and the gate scanning line in this embodiment are obtained by patterning the same conductive film layer, then the gate electrode 42 and the gate scanning line are arranged in the same layer.
  • the interlayer insulating layer 23 covers the gate electrode 42 and the gate insulating layer 22 , and the source electrode 43 and the drain electrode 44 of the transistor 40 are located on the interlayer insulating layer 23 .
  • the material of the interlayer insulating layer 23 may also include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the source electrode 43 of the transistor 40 is electrically connected to the source region of the active layer 41
  • the drain electrode 44 of the transistor 40 is electrically connected to the drain region of the active layer 41 .
  • signals such as data lines and power lines (such as VDD, etc.) provided in the same layer as the source electrode 43 and the drain electrode 44 can also be formed. lines, the data lines and the power lines are also located in the wiring area LA.
  • the data line may be electrically connected to the source 43 of the transistor 40 .
  • the second stack 30 and the light emitting unit are located above the first stack 20 and the transistor 40 .
  • the second stack 30 includes a planarization layer 32 located above the first stack 20 , and a pixel definition layer 33 located on a side of the planarization layer 32 away from the first stack 20 .
  • a pixel opening 331 is provided on the pixel definition layer 33 of the pixel area PA, and the light-emitting unit is located in the pixel opening 331.
  • the planarization layer 32 covers the source electrode 43 , the drain electrode 44 and the interlayer insulating layer 23 , and the planarization layer 32 has a substantially flat or horizontal top surface.
  • the material of the planarization layer 32 includes organic materials such as polyimide, epoxy resin, acrylic resin, or polyester.
  • the first electrode 51 of the light-emitting unit is disposed on the planarization layer 32 , and the first electrode 51 is electrically connected to the drain electrode 44 of the transistor 40 through a via hole of the planarization layer 32 .
  • the first electrode 51 corresponds to the pixel opening 331 , and the pixel opening 331 exposes part of the first electrode 51 .
  • the first electrode 51 may be a transparent electrode or a reflective electrode. If the first electrode 51 is a transparent electrode, the first electrode 51 may be made of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ZnO or In 2 O 3 is formed. If the first electrode 51 is a reflective electrode, the first electrode 51 may include, for example, a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a combination thereof; Layer formed from ITO, IZO, ZnO or In 2 O 3 . However, the first electrode 51 is not limited thereto, and the first electrode 51 may be formed of various materials, and may also be formed in a single-layer or multi-layer structure.
  • the pixel definition layer 33 covers the planarization layer 32 and the first electrode 51.
  • the pixel definition layer 33 is provided with the pixel opening 331 at a position corresponding to the first electrode 51.
  • the pixel The opening 331 exposes part of the first electrode 51 .
  • the material of the pixel definition layer 33 may include a transparent organic material of polyimide or acrylic resin.
  • the pixel opening 331 is formed on the pixel definition layer 33 of the pixel area PA
  • the opening 31 is formed on the pixel definition layer 33 of the transparent area TA
  • the openings 31 are sequentially Penetrating the second stack 30 , the first stack 20 and part of the first substrate 11 .
  • the plane where the base substrate 10 is located refers to the plane where the surface of the base substrate 10 facing the first stack 20 is located.
  • the opening 31 includes a first sub-hole 311, a second sub-hole 312, and a third sub-hole 313 that penetrate each other.
  • the first sub-hole 311 penetrates the second stack 30, and the third sub-hole 311 penetrates the second stack 30.
  • the two sub-holes 312 penetrate through the first stack 20 , and the third sub-hole 313 penetrates at least part of the base substrate 10 .
  • the first sub-hole 311 penetrates the pixel definition layer 33 and the planarization layer 32 in sequence.
  • the second sub-hole 312 penetrates the interlayer insulating layer 23 , the gate insulating layer 22 , the buffer layer 24 and the second barrier layer 21 in sequence.
  • the third sub-hole 313 penetrates part of the first substrate 11 .
  • the cross-sectional shapes of the first sub-hole 311 and the second sub-hole 312 include an inverted trapezoid, and the third sub-hole has an inverted trapezoid.
  • the cross-sectional shape of the hole 313 includes a rectangular shape, but the cross-sectional shape of the third sub-hole 313 is not limited thereto.
  • the opening size D1 of the opening of the first sub-hole 311 close to the second sub-hole 312 is larger than the opening size D2 of the opening of the second sub-hole 312 close to the first sub-hole 311 to simplify the process. It can be understood that under the same process conditions, the etching of the organic film layer is easier than the etching of the inorganic film layer, so the opening of the first sub-hole 311 and the opening of the second sub-hole 312 are different. The standardized design can use the same process conditions, thus simplifying the process.
  • the opening size of each sub-hole refers to the maximum length of the opening of each sub-hole in a direction parallel to the plane of the substrate 10 , such as when the shape of the opening of each sub-hole is circular, the opening size of the opening may be the diameter of the circle; when the shape of the opening of each sub-hole is square, the opening size of the opening may be the diagonal of the square length.
  • the opening size D4 of the opening of the third sub-hole 313 close to the side of the first stack 20 is larger than the opening size D3 of the opening of the second sub-hole 312 close to the side of the base substrate 10 , so that the The opening 31 forms an undercut structure between the first stack 20 and the base substrate 10 .
  • the second sub-hole 312 is formed by etching the first stack 20
  • the third sub-hole 313 is formed by etching the first substrate 11
  • the first substrate 11 is made of organic material. form. In this way, by adjusting the dry etching process, the difference in etching rates of the organic film layer and the inorganic film layer is used to form the second sub-hole 312 and the third sub-hole 313 to form the opening 31 with an undercut structure.
  • the undercut structure of the opening 31 can cause the organic auxiliary layer 53 in the light-emitting unit to be disconnected at the undercut structure, thereby cutting off the path for water and oxygen to enter the light-emitting unit through the organic auxiliary layer 53 of the light-emitting unit. , to protect the light-emitting layer 52 in the light-emitting unit from being invaded by water and oxygen and causing failure.
  • the luminescent layer 52 is located in the pixel opening 331 .
  • the luminescent layer 52 is formed of a luminescent material printed in the pixel opening 331 .
  • Different colors of luminescent materials form different colors of the luminescent layer 52 .
  • the luminescent layer 52 may include a red luminescent layer formed of red luminescent material, a green luminescent layer formed of green luminescent material, and a blue luminescent layer formed of blue luminescent material.
  • the red luminescent layer emits red light
  • the green luminescent layer emits green light.
  • Light, the blue luminescent layer emits blue light.
  • a second electrode 54 opposite to the first electrode 51 is also required.
  • the second electrode 54 is located on the side of the light-emitting layer 52 away from the first electrode 51.
  • the second electrode 54 covers the light-emitting layer 52 and the pixel definition layer 33, and Extending to the transparent area TA, a notch is provided at a position corresponding to the opening 31 to further improve the transmittance of the transparent area TA.
  • the luminescent layer 52 emits light under the joint action of the first electrode 51 and the second electrode 54 .
  • the luminescent layers 52 of different colors emit light of different colors, thereby realizing color display of the display panel 100 .
  • the first electrode 51 in the embodiment of the present application is an anode
  • the second electrode 54 is a cathode.
  • the present application is not limited thereto.
  • the first electrode 51 of the present application may also be a cathode, and accordingly , the second electrode 54 is an anode.
  • the organic auxiliary layer 53 is located on the side of the light-emitting layer 52 close to the planarization layer 32 . Specifically, the organic auxiliary layer 53 is located between the light-emitting layer 52 and the first electrode 51 . The organic auxiliary layer 53 covers the first electrode 51 and the pixel definition layer 33, and also extends into the opening 31 of the transparent area TA, and is between the first stacked layer 20 and the pixel definition layer 33. The base substrate 10 is disconnected, that is, the organic auxiliary layer 53 is disconnected at the undercut structure of the opening 31 .
  • the organic auxiliary layer 53 includes a hole transport layer (HTL) or a stack of a hole injection layer (HIL) and a hole transport layer (HTL).
  • the organic auxiliary layer 53 may also include an electron injection layer (EIL) and an electron transport layer (ETL) located between the light-emitting layer 52 and the second electrode 54 .
  • the hole injection layer receives holes transmitted by the first electrode 51, and the holes are transmitted to the light-emitting layer 52 through the hole transmission layer.
  • the electron injection layer receives electrons transmitted by the second electrode 54, and the electrons are transmitted to the light-emitting layer 52 through the electron transmission layer.
  • the holes and electrons combine at the position of the light-emitting layer 52 to generate excitons, which transition from the excited state to the ground state to release energy and emit light.
  • the display panel 100 further includes an encapsulation layer 60 disposed on the side of the light-emitting unit away from the base substrate 10 .
  • the encapsulation layer 60 includes a stacked first sub-encapsulation layer 61 and a second sub-encapsulation layer 62, wherein the first sub-encapsulation layer 61 is an inorganic encapsulation layer, and the second sub-encapsulation layer 62 is an organic encapsulation layer,
  • the first sub-encapsulation layer 61 extends into the opening 31 and covers the organic auxiliary layer 53
  • the second sub-encapsulation layer 62 fills the opening 31 .
  • the encapsulation layer 60 may also include more encapsulation sub-layers.
  • the encapsulation layer 60 may further include a third sub-encapsulation layer 63.
  • the encapsulation layer 63 covers the second sub-encapsulation layer 62, and the third sub-encapsulation layer 63 is an inorganic encapsulation layer.
  • the first sub-encapsulation layer 61 covers the organic auxiliary layer 53 and fills the position where the organic auxiliary layer 53 is disconnected in the opening 31 , so that the first sub-encapsulation layer 61 is located at the position where the organic auxiliary layer 53 is disconnected.
  • the organic auxiliary layer 53 in the first sub-hole 311 and the second sub-hole 312 is disconnected between the base substrate 10 and the first stack 20 to avoid Water oxygen or external water oxygen passing through the base substrate 10 enters the light-emitting unit through the organic auxiliary layer 53, causing the light-emitting unit to fail.
  • the second sub-encapsulation layer 62 covers the first sub-encapsulation layer 61 and fills the opening 31 .
  • the light transmittance of the second sub-encapsulation layer 62 is greater than the light transmittance of the second stack 30 and the first stack 20 , and the opening 31 is provided in the transparent area TA to remove the
  • the second stack 30 , the first stack 20 and part of the first substrate 11 are filled with the second sub-packaging layer 62 in the opening 31 , so that the transparent area TA can have Better light transmittance, thereby improving the transmittance of the transparent area TA.
  • FIG. 4 is another schematic cross-sectional structural diagram of a display panel provided by an embodiment of the present application.
  • the base substrate 10 includes a first substrate 11 and a second substrate 12, and the first stack 20 is disposed on the first substrate.
  • the second substrate 12 is located on a side of the first substrate 11 away from the first stack 20 , and the third sub-hole 313 penetrates the first substrate 11 and is exposed.
  • the third sub-hole 313 with a deeper depth can also be provided, which will be beneficial to the first sub-packaging layer 61 in the opening. settings within 31.
  • the use of a double-layer substrate can also improve the support performance of the first stack 20 and the second stack 30 .
  • the material of the second substrate 12 is the same as the material of the first substrate 11 .
  • the base substrate 10 further includes a first barrier layer 13 located between the first substrate 11 and the second substrate 12 , and the third sub-hole 313 penetrates the first The substrate 11 is exposed to partially expose the first barrier layer 13 .
  • the first barrier layer 13 can prevent undesired impurities or contaminants (eg, moisture, oxygen, etc.) from diffusing from the second substrate 12 into devices that may be damaged by these impurities or contaminants.
  • the material of the first barrier layer 13 is the same as the material of the second barrier layer 21 , and may include inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc. .
  • the transistor 40 in this embodiment adopts a double-gate structure.
  • the gate 42 includes a first gate 42-1 and a second gate 42-2.
  • the gate insulating layer 22 also includes a first gate insulating layer 22-1 and a second gate 42-1. Two gate insulating layers 22-2.
  • the first gate insulating layer 22-1 covers the active layer 41 and the buffer layer 24, and the first gate 42-1 is disposed on the first gate insulating layer 22-1. , and are arranged corresponding to the channel of the active layer 41 .
  • the second gate insulating layer 22-2 covers the first gate 42-1 and the first gate insulating layer 22-1, and the second gate 42-2 is disposed on the first gate insulating layer 22-1.
  • the second gate insulating layer 22-2 is disposed corresponding to the first gate 42-1.
  • the interlayer insulating layer 23 covers the second gate electrode 42-2 and the second gate insulating layer 22-2.
  • FIG. 5 is another schematic cross-sectional structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 102 further includes a transparent filler 70 filled in the opening 31 , and the encapsulation layer 60 covers the transparent filler 70 .
  • the first sub-encapsulation layer 61 also covers the organic auxiliary layer 53 in the opening 31 to cut off the water and oxygen intrusion path of the organic auxiliary layer 53, and the transparent filler 70 is filled with In the opening 31 and covering the first sub-packaging layer 61 in the opening 31 .
  • the second sub-encapsulation layer 62 covers the first sub-encapsulation layer 61 and the transparent filler 70
  • the third sub-encapsulation layer 63 covers the second sub-encapsulation layer 62 .
  • the transparent filler 70 has greater light transmittance than the first stack 20 and the second stack 30 .
  • the transparent filler 70 includes transparent materials such as OCA optical glue.
  • an embodiment of the present application also provides an electronic device, which includes the display panel of one of the above embodiments to achieve transparent display.
  • the electronic devices include electronic products such as televisions, and can be applied to scenarios such as car window displays and glass curtain walls.
  • the present application provides a display panel and an electronic device.
  • the display panel includes a pixel area and a transparent area between the pixel areas.
  • the display panel further includes a first stack and a second layer disposed on a base substrate. Stacked layer, an opening is provided on the second stacked layer corresponding to the transparent area, the opening penetrates the second stacked layer and the first stacked layer, and penetrates at least part of the base substrate .
  • This application solves the problem of poor transmittance of existing transparent display screens by arranging openings in the transparent area to remove the first stacked layer in the transparent area to improve the transmittance of the transparent area.

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  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示面板（100）和电子装置，该显示面板（100）包括设置在衬底基板（10）上的第一叠层（20）和第二叠层（30），在对应透明区（TA）的第二叠层（30）上设置有开孔（31），开孔（31）贯穿第二叠层（30）以及第一叠层（20），并至少贯穿部分衬底基板（10）。通过在透明区（TA）设置开孔（31），以去除透明区（TA）内的第一叠层（20），以提高透明区（TA）的穿透率，缓解现有透明显示屏穿透率不佳的问题。

Description

显示面板和电子装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和电子装置。
 背景技术
随着显示技术的发展，透明显示屏(Transparent Display)的出现大大扩展了显示应用的场景和范围。透明显示屏是指显示屏本身具有一定程度的穿透性，能够清楚地显示面板后方的背景。透明显示屏适用于建筑物窗户、汽车车窗与商店橱窗等多种应用场景，除了原有的透明显示功能以外，还具有未来可能作为信息显示器的发展潜力，因而备受市场关注。然而透明显示屏同样包括由不同的材料形成的多个绝缘层和导电层，这些膜层的存在势必会影响透明显示屏的穿透率。
 技术问题
本申请提供一种显示面板和电子装置，以缓解现有透明显示屏穿透率不佳的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，其包括像素区以及位于所述像素区之间的透明区，所述显示面板还包括：
衬底基板；
第一叠层，设置于所述衬底基板上；
第二叠层，设置在所述第一叠层远离所述衬底基板的一侧；
其中，在对应所述透明区的所述第二叠层上设置有开孔，所述开孔贯穿所述第二叠层以及所述第一叠层，并贯穿至少部分所述衬底基板。
在本申请实施例提供的显示面板中，所述开孔包括相互贯通的第一子孔、第二子孔以及第三子孔，所述第一子孔贯穿所述第二叠层，所述第二子孔贯穿所述第一叠层，所述第三子孔贯穿至少部分所述衬底基板。
在本申请实施例提供的显示面板中，所述第三子孔靠近所述第一叠层侧的开口的开口大小大于所述第二子孔靠近所述衬底基板侧的开口的开口大小。
在本申请实施例提供的显示面板中，所述第一子孔靠近所述第二子孔侧的开口的开口大小大于所述第二子孔靠近所述第一子孔侧的开口的开口大小。
在本申请实施例提供的显示面板中，所述衬底基板包括靠近所述第一叠层设置的第一衬底，所述第一叠层设置在所述第一衬底上，所述第三子孔贯穿部分所述第一衬底。
在本申请实施例提供的显示面板中，所述衬底基板包括第一衬底和第二衬底，所述第一叠层设置在所述第一衬底上，所述第二衬底位于所述第一衬底远离所述第一叠层的一侧，所述第三子孔贯穿所述第一衬底并暴露出部分所述第二衬底。
在本申请实施例提供的显示面板中，所述衬底基板还包括位于所述第一衬底和第二衬底之间的第一阻挡层，所述第三子孔贯穿所述第一衬底并暴露出部分所述第一阻挡层。
在本申请实施例提供的显示面板中，所述第二叠层包括位于所述第一叠层上方的平坦化层，以及位于所述平坦化层远离所述第一叠层一侧的像素定义层，在对应所述像素区的所述像素定义层上设置有像素开口；
所述显示面板还包括位于所述像素开口内的发光层以及位于所述发光层靠近所述平坦化层一侧的有机辅助层，所述有机辅助层还延伸至所述透明区的所述开孔内，并在所述第三子孔和所述第二子孔之间断开。
在本申请实施例提供的显示面板中，所述显示面板还包括：
第一电极，位于所述像素区的所述平坦化层上，所述像素开口暴露出部分所述第一电极；
第二电极，位于所述发光层远离所述第一电极的一侧，且所述第二电极延伸至所述透明区，并在对应所述开孔的位置设置有缺口；
封装层，设置在所述第二电极远离所述发光层的一侧。
在本申请实施例提供的显示面板中，所述封装层包括层叠设置的第一子封装层和第二子封装层，其中所述第一子封装层延伸至所述开孔内，并覆于所述有机辅助层上，所述第二子封装层填充于所述开孔。
在本申请实施例提供的显示面板中，所述显示面板还包括填充于所述开孔的透明填料，所述封装层覆于所述透明填料上。
本申请实施例还提供一种电子装置，其包括前述实施例其中之一的显示面板。
 有益效果
本申请提供的显示面板和电子装置中，所述显示面板包括像素区以及位于所述像素区之间的透明区，所述显示面板还包括设置在衬底基板上的第一叠层和第二叠层，在对应所述透明区的所述第二叠层上设置有开孔，所述开孔贯穿所述第二叠层以及所述第一叠层，并至少贯穿部分所述衬底基板。本申请通过在透明区设置开孔，以去除透明区内的第一叠层，以提高透明区的穿透率，解决了现有透明显示屏穿透率不佳的问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的俯视结构示意图。
图2为本申请实施例提供的显示面板的一种剖面结构示意图。
图3为本申请实施例提供的开孔的细节结构示意图。
图4为本申请实施例提供的显示面板的另一种剖面结构示意图。
图5为本申请实施例提供的显示面板的又一种剖面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
请结合参照图1至图3，图1为本申请实施例提供的显示面板的俯视结构示意图，图2为本申请实施例提供的显示面板的一种剖面结构示意图，图3为本申请实施例提供的开孔的细节结构示意图。所述显示面板100包括像素区PA以及位于所述像素区PA之间的透明区TA，每个所述像素区PA包括至少三个不同颜色的子像素，比如红色子像素R、绿色子像素G以及蓝色子像素B。所述透明区TA位于所述像素区PA之间，外部环境光能够从所述透明区TA穿过，以实现所述显示面板100的透明显示。当然地，所述显示面板100还包括走线区LA，所述走线区LA设置有用于连接所述像素区PA各子像素的栅极扫描线、数据线、电源线等信号线。所述透明区TA具体设置在除了所述像素区PA和所述走线区LA之外的区域，使所述透明区TA避让所述走线区LA和所述像素区PA。
具体地，所述显示面板100还包括衬底基板10、设置于所述衬底基板10上的第一叠层20和第二叠层30，所述第二叠层30设置在所述第一叠层20远离所述衬底基板10的一侧。其中，在对应所述透明区TA的所述第二叠层30上设置有开孔31，所述开孔31贯穿所述第二叠层30以及所述第一叠层20，并贯穿至少部分所述衬底基板10。其中所述第一叠层20为无机叠层，所述第二叠层30为有机叠层。
通过在所述透明区TA设置所述开孔31，以去除所述透明区TA内的所述第一叠层20，提高了所述透明区TA的穿透率，进而解决了现有透明显示屏穿透率不佳的问题。需要说明的是，所述开孔31贯穿至少部分所述衬底基板10是指所述开孔31贯穿所述衬底基板10靠近所述第一叠层20一侧的表面，并延伸至所述衬底基板10内，但未贯穿所述衬底基板10远离所述第一叠层20一侧的表面，也即所述开孔31并未穿透所述衬底基板10。
下面将具体阐述所述显示面板100具体的膜层结构以及所述开孔31的结构：
参照图2，所述显示面板100包括设置在衬底基板10上的第一叠层20和第二叠层30，其中在所述像素区PA的所述衬底基板10上设置有晶体管40和发光单元，而在所述透明区TA设置有贯穿所述第二叠层30、所述第一叠层20以及部分所述衬底基板10的所述开孔31。所述晶体管40用于驱动所述发光单元发光。所述发光单元包括第一电极51、第二电极54以及夹设在所述第一电极51和所述第二电极54之间的发光层52以及有机辅助层53。需要说明的，图2仅示意出所述像素区PA的一个子像素以及该一个子像素的一个晶体管40，但本申请不限于此，本申请的一个子像素可包括至少两个晶体管，比如一个开关晶体管和一个驱动晶体管。
具体地，所述晶体管40和所述第一叠层20均设置在所述衬底基板10上，所述衬底基板10包括靠近所述第一叠层20设置的第一衬底11。可选地，所述第一衬底11的材料包括聚酰亚胺（Polyimide，PI）等柔性薄膜材料。而为了进一步提高所述透明区TA的穿透率，所述第一衬底11的材料还可为透明聚酰亚胺（Clear Polyimide，CPI）等高透过性的柔性薄膜材料。
所述晶体管40包括有源层41、栅极42、漏极44和漏极44。所述第一叠层20包括层叠设置的第二阻挡层21、栅极绝缘层22以及层间绝缘层23。所述第二阻挡层21位于所述第一衬底11上，所述晶体管40的所述有源层41位于所述第二阻挡层21上。所述第二阻挡层21可防止不期望的杂质或污染物（例如湿气、氧气等）从所述第一衬底11扩散至可能因这些杂质或污染物而受损的器件中。可选地，所述第二阻挡层21的材料包括氧化硅（SiOx）、氮化硅（SiNx）、氮氧化硅（SiON）等无机材料。
可选地，所述第二阻挡层21和所述有源层41之间还可设置缓冲层24，所述缓冲层24可进一步避免不期望的杂质或污染物（例如湿气、氧气等）从所述第一衬底11扩散至可能因这些杂质或污染物而受损的器件中，且所述缓冲层24还可提供平坦的顶表面。所述缓冲层24的材料可与所述第二阻挡层21的材料相同，比如均为氧化硅、氮化硅、氮氧化硅等无机材料。
所述有源层41设置在所述缓冲层24上，所述有源层41包括沟道以及位于所述沟道两侧的源区和漏区。可选地，所述有源层41的材料包括例如氧化铟镓锌(IGZO)、氧化锌锡(ZTO) 或氧化铟锡锌(ITZO)等的氧化物半导体材料。
所述栅极绝缘层22覆于所述有源层41以及所述第二阻挡层21上，当然地，当所述第一叠层20还包括缓冲层24时，所述栅极绝缘层22覆于所述有源层41和所述缓冲层24上。可选地，所述栅极绝缘层22的材料也可包括氧化硅、氮化硅、氮氧化硅等无机材料。
所述晶体管40的所述栅极42位于所述栅极绝缘层22上，所述栅极42对应所述有源层41的所述沟道设置。当然地，在形成所述栅极42的同时，还可形成与所述栅极42同层设置的栅极扫描线等其他信号线，所述栅极扫描线即位于所述走线区LA。其中所述栅极42与所述栅极扫描线电连接。
需要说明的是，本申请中的“同层设置”是指在制备工艺中，将相同材料形成的膜层进行图案化处理得到至少两个不同的特征，则所述至少两个不同的特征同层设置。比如，本实施例的所述栅极42与所述栅极扫描线由同一导电膜层进行图案化处理后得到，则所述栅极42与所述栅极扫描线同层设置。
所述层间绝缘层23覆于所述栅极42以及所述栅极绝缘层22上，所述晶体管40的所述源极43和所述漏极44位于所述层间绝缘层23上。所述层间绝缘层23的材料也可包括氧化硅、氮化硅、氮氧化硅等无机材料。
所述晶体管40的所述源极43与所述有源层41的所述源区电连接，所述晶体管40的所述漏极44与所述有源层41的所述漏区电连接。当然地，在形成所述源极43和所述漏极44的同时，还可形成与所述源极43和所述漏极44同层设置的数据线以及电源线（如VDD等）等信号线，所述数据线以及所述电源线也位于所述走线区LA。其中所述数据线可与所述晶体管40的源极43电连接。
所述第二叠层30和所述发光单元位于所述第一叠层20和所述晶体管40上方。所述第二叠层30包括位于所述第一叠层20上方的平坦化层32，以及位于所述平坦化层32远离所述第一叠层20一侧的像素定义层33，在对应所述像素区PA的所述像素定义层33上设置有像素开口331，所述发光单元位于所述像素开口331内。
具体地，所述平坦化层32覆于所述源极43、所述漏极44以及所述层间绝缘层23上，所述平坦化层32具有基本平坦或水平的顶表面。可选地，所述平坦化层32的材料包括聚酰亚胺、环氧类树脂、丙烯酰类树脂或聚酯等的有机材料。
所述发光单元的所述第一电极51设置在所述平坦化层32上，所述第一电极51通过所述平坦化层32的过孔与所述晶体管40的漏极44电连接。所述第一电极51对应所述像素开口331，所述像素开口331暴露出部分所述第一电极51。
可选地，所述第一电极51可以是透明电极或反射电极，如果所述第一电极51是透明电极，则所述第一电极51可以由例如氧化铟锡(ITO)、氧化铟锌(IZO)、ZnO或In 2O 3形成。如果所述第一电极51是反射电极，则所述第一电极51例如可以包括由Ag、Mg、Al、Pt、Pd、Au、Ni、Nd、Ir、Cr或它们的组合形成的反射层以及由ITO、IZO、ZnO或In 2O 3形成的层。然而，第一电极51不限于此，第一电极51可以由各种材料形成，并且也可以形成为单层或多层结构。
所述像素定义层33覆于所述平坦化层32以及所述第一电极51上，所述像素定义层33在对应所述第一电极51的位置设置有所述像素开口331，所述像素开口331暴露出部分所述第一电极51。可选地，所述像素定义层33的材料可包括聚酰亚胺或丙烯酰类树脂的透明有机材料。
在所述像素区PA的所述像素定义层33上形成所述像素开口331的同时，在所述透明区TA的所述像素定义层33上形成所述开孔31，所述开孔31依次贯穿所述第二叠层30、所述第一叠层20以及部分所述第一衬底11。可以理解的是，在沿垂直于所述衬底基板10所在平面的方向上，由于所述像素开口331的深度远小于所述开孔31的深度，使得在形成所述开孔31时，需要更多的工艺步骤。其中所述衬底基板10所在平面是指所述衬底基板10面向所述第一叠层20的表面所在的平面。
具体而言，所述开孔31包括相互贯通的第一子孔311、第二子孔312以及第三子孔313，所述第一子孔311贯穿所述第二叠层30，所述第二子孔312贯穿所述第一叠层20，所述第三子孔313至少贯穿部分所述衬底基板10。更具体地，所述第一子孔311依次贯穿所述像素定义层33和所述平坦化层32。所述第二子孔312依次贯穿所述层间绝缘层23、所述栅极绝缘层22、所述缓冲层24以及所述第二阻挡层21。所述第三子孔313贯穿部分所述第一衬底11。
可选地，参照图3，在垂直于所述衬底基板10所在平面的方向上，所述第一子孔311和所述第二子孔312的截面形状包括倒梯形，所述第三子孔313的截面形状包括矩形，但所述第三子孔313的截面形状不限于此。通过设置倒梯形的所述第一子孔311和所述第二子孔312，将有利于后续在所述开孔31内制备膜层的爬坡。
所述第一子孔311靠近所述第二子孔312侧的开口的开口大小D1大于所述第二子孔312靠近所述第一子孔311侧的开口的开口大小D2，以简化工艺。可以理解的是，在相同的工艺条件下，有机膜层的蚀刻相较于无机膜层的蚀刻较为容易，而使所述第一子孔311的开口与所述第二子孔312的开口差异化设计，即可采用相同的工艺条件，从而可简化工艺。其中各子孔（以所述第一子孔311为例）的所述开口的开口大小是指沿平行于所述衬底基板10所在平面的方向上各子孔的开口的最大长度，比如当各子孔的开口的形状为圆形时，所述开口的开口大小可为圆形的直径；当各子孔的开口的形状为方形时，所述开口的开口大小可为方形的对角线的长度。
进一步地，所述第三子孔313靠近所述第一叠层20侧的开口的开口大小D4大于所述第二子孔312靠近所述衬底基板10侧的开口的开口大小D3，使得所述开孔31在所述第一叠层20和所述衬底基板10之间形成底切结构。同样地，所述第二子孔312由蚀刻所述第一叠层20形成，所述第三子孔313由蚀刻所述第一衬底11形成，而所述第一衬底11由有机材料形成。如此，通过调整干刻蚀刻工艺，利用有机膜层和无机膜层蚀刻速率差异形成所述第二子孔312和所述第三子孔313，以形成具有底切结构的所述开孔31。
所述开孔31的底切结构能够使所述发光单元内的有机辅助层53在底切结构处断开，从而切断水氧通过所述发光单元的有机辅助层53进入所述发光单元的路径，以保护所述发光单元中的发光层52，避免被水氧入侵而导致失效。
具体地，所述发光层52位于所述像素开口331内，所述发光层52是由打印在所述像素开口331内的发光材料形成，不同颜色的发光材料形成不同颜色的发光层52。比如发光层52可以包括由红色发光材料形成的红色发光层，由绿色发光材料形成的绿色发光层，由蓝色发光材料形成的蓝色发光层，红色发光层发出红光，绿色发光层发出绿光，蓝色发光层发出蓝光。
当然地，要实现所述发光单元的发光，还需要与所述第一电极51相对的第二电极54。所述第二电极54位于所述发光层52远离所述第一电极51的一侧，具体而言，所述第二电极54覆于所述发光层52以及所述像素定义层33上，并延伸到所述透明区TA，且在对应所述开孔31的位置设置有缺口，以进一步提高所述透明区TA的穿透率。所述发光层52在所述第一电极51和所述第二电极54的共同作用下发光，不同颜色的所述发光层52发射不同颜色的光，进而实现所述显示面板100的彩色显示。其中本申请实施例的所述第一电极51为阳极，所述第二电极54为阴极，当然地，本申请不限于此，本申请的所述第一电极51也可为阴极，而相应地，所述第二电极54为阳极。
所述有机辅助层53位于所述发光层52靠近所述平坦化层32的一侧，具体而言，所述有机辅助层53位于所述发光层52和所述第一电极51之间。所述有机辅助层53覆于所述第一电极51以及所述像素定义层33上，且还延伸至所述透明区TA的所述开孔31内，并在所述第一叠层20和所述衬底基板10之间断开，也即所述有机辅助层53在所述开孔31的底切结构处断开。
可选地，所述有机辅助层53包括空穴传输层(HTL)或者空穴注入层(HIL)与空穴传输层(HTL)的叠层。当然地，所述有机辅助层53还可包括位于所述发光层52和所述第二电极54之间的电子注入层(EIL)、电子传输层(ETL)。空穴注入层接收第一电极51传输的空穴，空穴经由空穴传输层传输至发光层52，电子注入层接收第二电极54传输的电子，电子经由电子传输层传输至发光层52，空穴和电子在发光层52位置结合后产生激子，激子由激发态跃迁至基态释放能量并发光。
进一步地，为了避免所述发光层52被水氧入侵导致失效，所述显示面板100还包括设置于所述发光单元远离所述衬底基板10一侧的封装层60。所述封装层60包括层叠设置的第一子封装层61和第二子封装层62，其中所述第一子封装层61为无机封装层，所述第二子封装层62为有机封装层，所述第一子封装层61延伸至所述开孔31内，并覆于所述有机辅助层53上，所述第二子封装层62填充于所述开孔31。当然地，为了提高所述封装层60的封装效果，所述封装层60还可包括更多的封装子层，比如所述封装层60还可包括第三子封装层63，所述第三子封装层63覆于所述第二子封装层62上，所述第三子封装层63为无机封装层。
在所述开孔31内，所述第一子封装层61覆于所述有机辅助层53上，并填充在所述有机辅助层53在所述开孔31内断开的位置，使位于所述第一子孔311和所述第二子孔312内的所述有机辅助层53在所述衬底基板10和所述第一叠层20之间断开，避免所述衬底基板10内的水氧或透过所述衬底基板10的外界水氧通过所述有机辅助层53进入所述发光单元内，导致所述发光单元失效。
而所述第二子封装层62覆于所述第一子封装层61上，并填充在所述开孔31内。所述第二子封装层62的透光性大于所述第二叠层30以及所述第一叠层20的透光性，通过在所述透明区TA设置所述开孔31以去除所述第二叠层30、所述第一叠层20以及部分所述第一衬底11，并在所述开孔31内填充所述第二子封装层62，从而可使得所述透明区TA具有较好的透光性，进而提高了所述透明区TA的穿透率。
在一种实施例中，请参照图1至图4，图4为本申请实施例提供的显示面板的另一种剖面结构示意图。与上述实施例不同的是，在本实施例的显示面板101中，所述衬底基板10包括第一衬底11和第二衬底12，所述第一叠层20设置在所述第一衬底11上，所述第二衬底12位于所述第一衬底11远离所述第一叠层20的一侧，所述第三子孔313贯穿所述第一衬底11并暴露出部分所述第二衬底12，如此在提高所述透明区TA的同时，还可设置深度更深的所述第三子孔313，将有利于所述第一子封装层61在所述开孔31内的设置。而且采用双层衬底，还可提高对所述第一叠层20和所述第二叠层30的支撑性能。可选地，所述第二衬底12的材料与所述第一衬底11的材料相同。
在一种实施例中，所述衬底基板10还包括位于所述第一衬底11和第二衬底12之间的第一阻挡层13，所述第三子孔313贯穿所述第一衬底11并暴露出部分所述第一阻挡层13。所述第一阻挡层13可防止不期望的杂质或污染物（例如湿气、氧气等）从所述第二衬底12扩散至可能因这些杂质或污染物而受损的器件中。可选地，所述第一阻挡层13的材料与所述第二阻挡层21的材料相同，比如可包括氧化硅（SiOx）、氮化硅（SiNx）、氮氧化硅（SiON）等无机材料。
另外，与上述实施例不同的还有所述晶体管40的结构，本实施例的晶体管40采用双栅结构。具体而言，所述栅极42包括第一栅极42-1和第二栅极42-2，相对应地，所述栅极绝缘层22也包括第一栅极绝缘层22-1和第二栅极绝缘层22-2。所述第一栅极绝缘层22-1覆于所述有源层41以及所述缓冲层24上，所述第一栅极42-1设置在所述第一栅极绝缘层22-1上，并与所述有源层41的沟道对应设置。所述第二栅极绝缘层22-2覆于所述第一栅极42-1以及所述第一栅极绝缘层22-1上，所述第二栅极42-2设置在所述第二栅极绝缘层22-2上，并与所述第一栅极42-1对应设置。所述层间绝缘层23覆于所述第二栅极42-2以及所述第二栅极绝缘层22-2上。需要说明的是，本申请的所述晶体管40结构不限于上述实施例示例的，比如本申请的所述晶体管40还可采用底栅结构等。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请参照图1至图5，图5为本申请实施例提供的显示面板的又一种剖面结构示意图。与上述实施例不同的是，所述显示面板102还包括填充于所述开孔31的透明填料70，所述封装层60覆于所述透明填料70上。具体而言，所述第一子封装层61还覆于所述开孔31内的所述有机辅助层53上，以切断所述有机辅助层53的水氧入侵路径，所述透明填料70填充在所述开孔31内并覆于所述开孔31内的所述第一子封装层61上。所述第二子封装层62覆于所述第一子封装层61以及所述透明填料70上，所述第三子封装层63覆于所述第二子封装层62上。其中所述透明填料70的透光性大于所述第一叠层20以及所述第二叠层30，可选地，所述透明填料70包括OCA光学胶等透明材料。通过在所述透明区TA设置所述开孔31，并在所述开孔31内填充所述透明填料70，提高了所述透明区TA的穿透率。其他说明请参照上述实施例，在此不再赘述。
基于同一发明构思，本申请实施例还提供一种电子装置，所述电子装置包括上述实施例其中之一的显示面板，以实现透明显示。所述电子装置包括电视等电子产品，可应用汽车车窗显示、玻璃幕墙等场景。
根据上述实施例可知：
本申请提供一种显示面板和电子装置，所述显示面板包括像素区以及位于所述像素区之间的透明区，所述显示面板还包括设置在衬底基板上的第一叠层和第二叠层，在对应所述透明区的所述第二叠层上设置有开孔，所述开孔贯穿所述第二叠层以及所述第一叠层，并至少贯穿部分所述衬底基板。本申请通过在透明区设置开孔，以去除透明区内的第一叠层，以提高透明区的穿透率，解决了现有透明显示屏穿透率不佳的问题。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括像素区以及位于所述像素区之间的透明区，所述显示面板还包括：
    衬底基板；
    第一叠层，设置于所述衬底基板上；
    第二叠层，设置在所述第一叠层远离所述衬底基板的一侧；
    其中，在对应所述透明区的所述第二叠层上设置有开孔，所述开孔贯穿所述第二叠层以及所述第一叠层，并贯穿至少部分所述衬底基板。
  2. 根据权利要求1所述的显示面板，其中，所述开孔包括相互贯通的第一子孔、第二子孔以及第三子孔，所述第一子孔贯穿所述第二叠层，所述第二子孔贯穿所述第一叠层，所述第三子孔贯穿至少部分所述衬底基板。
  3. 根据权利要求2所述的显示面板，其中，所述第三子孔靠近所述第一叠层侧的开口的开口大小大于所述第二子孔靠近所述衬底基板侧的开口的开口大小。
  4. 根据权利要求2所述的显示面板，其中，所述第一子孔靠近所述第二子孔侧的开口的开口大小大于所述第二子孔靠近所述第一子孔侧的开口的开口大小。
  5. 根据权利要求2所述的显示面板，其中，所述衬底基板包括靠近所述第一叠层设置的第一衬底，所述第一叠层设置在所述第一衬底上，所述第三子孔至少贯穿部分所述第一衬底。
  6. 根据权利要求2所述的显示面板，其中，所述衬底基板包括第一衬底和第二衬底，所述第一叠层设置在所述第一衬底上，所述第二衬底位于所述第一衬底远离所述第一叠层的一侧，所述第三子孔贯穿所述第一衬底并暴露出部分所述第二衬底。
  7. 根据权利要求6所述的显示面板，其中，所述衬底基板还包括位于所述第一衬底和第二衬底之间的第一阻挡层，所述第三子孔贯穿所述第一衬底并暴露出部分所述第一阻挡层。
  8. 根据权利要求3所述的显示面板，其中，所述第二叠层包括位于所述第一叠层上方的平坦化层，以及位于所述平坦化层远离所述第一叠层一侧的像素定义层，在对应所述像素区的所述像素定义层上设置有像素开口；
    所述显示面板还包括位于所述像素开口内的发光层以及位于所述发光层靠近所述平坦化层一侧的有机辅助层，所述有机辅助层还延伸至所述透明区的所述开孔内，并在所述第一叠层和所述衬底基板之间断开。
  9. 根据权利要求8所述的显示面板，其中，所述显示面板还包括：
    第一电极，位于所述像素区的所述平坦化层上，所述像素开口暴露出部分所述第一电极；
    第二电极，位于所述发光层远离所述第一电极的一侧，且所述第二电极延伸至所述透明区，并在对应所述开孔的位置设置有缺口；
    封装层，设置在所述第二电极远离所述发光层的一侧。
  10. 根据权利要求9所述的显示面板，其中，所述封装层包括层叠设置的第一子封装层和第二子封装层，其中所述第一子封装层延伸至所述开孔内，并覆于所述有机辅助层上，所述第二子封装层填充于所述开孔。
  11. 根据权利要求9所述的显示面板，其中，所述显示面板还包括填充于所述开孔的透明填料，所述封装层覆于所述透明填料上。
  12. 一种电子装置，其包括显示面板，所述显示面板包括像素区以及位于所述像素区之间的透明区，所述显示面板还包括：
    衬底基板；
    第一叠层，设置于所述衬底基板上；
    第二叠层，设置在所述第一叠层远离所述衬底基板的一侧；
    其中，在对应所述透明区的所述第二叠层上设置有开孔，所述开孔贯穿所述第二叠层以及所述第一叠层，并贯穿至少部分所述衬底基板。
  13. 根据权利要求12所述的电子装置，其中，所述开孔包括相互贯通的第一子孔、第二子孔以及第三子孔，所述第一子孔贯穿所述第二叠层，所述第二子孔贯穿所述第一叠层，所述第三子孔贯穿至少部分所述衬底基板。
  14. 根据权利要求13所述的电子装置，其中，所述第三子孔靠近所述第一叠层侧的开口的开口大小大于所述第二子孔靠近所述衬底基板侧的开口的开口大小。
  15. 根据权利要求13所述的电子装置，其中，所述第一子孔靠近所述第二子孔侧的开口的开口大小大于所述第二子孔靠近所述第一子孔侧的开口的开口大小。
  16. 根据权利要求13所述的电子装置，其中，所述衬底基板包括靠近所述第一叠层设置的第一衬底，所述第一叠层设置在所述第一衬底上，所述第三子孔至少贯穿部分所述第一衬底。
  17. 根据权利要求13所述的电子装置，其中，所述衬底基板包括第一衬底和第二衬底，所述第一叠层设置在所述第一衬底上，所述第二衬底位于所述第一衬底远离所述第一叠层的一侧，所述第三子孔贯穿所述第一衬底并暴露出部分所述第二衬底。
  18. 根据权利要求17所述的电子装置，其中，所述衬底基板还包括位于所述第一衬底和第二衬底之间的第一阻挡层，所述第三子孔贯穿所述第一衬底并暴露出部分所述第一阻挡层。
  19. 根据权利要求14所述的电子装置，其中，所述第二叠层包括位于所述第一叠层上方的平坦化层，以及位于所述平坦化层远离所述第一叠层一侧的像素定义层，在对应所述像素区的所述像素定义层上设置有像素开口；
    所述显示面板还包括位于所述像素开口内的发光层以及位于所述发光层靠近所述平坦化层一侧的有机辅助层，所述有机辅助层还延伸至所述透明区的所述开孔内，并在所述第一叠层和所述衬底基板之间断开。
  20. 根据权利要求19所述的电子装置，其中，所述显示面板还包括：
    第一电极，位于所述像素区的所述平坦化层上，所述像素开口暴露出部分所述第一电极；
    第二电极，位于所述发光层远离所述第一电极的一侧，且所述第二电极延伸至所述透明区，并在对应所述开孔的位置设置有缺口；
    封装层，设置在所述第二电极远离所述发光层的一侧。
PCT/CN2022/105527 2022-06-30 2022-07-13 显示面板和电子装置 WO2024000663A1 (zh)

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