WO2020154875A1 - 像素单元及其制造方法和双面oled显示装置 - Google Patents

像素单元及其制造方法和双面oled显示装置 Download PDF

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Publication number
WO2020154875A1
WO2020154875A1 PCT/CN2019/073579 CN2019073579W WO2020154875A1 WO 2020154875 A1 WO2020154875 A1 WO 2020154875A1 CN 2019073579 W CN2019073579 W CN 2019073579W WO 2020154875 A1 WO2020154875 A1 WO 2020154875A1
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Prior art keywords
layer
cathode
anode
driving transistor
substrate
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PCT/CN2019/073579
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English (en)
French (fr)
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黄兴
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/642,193 priority Critical patent/US11183111B2/en
Priority to PCT/CN2019/073579 priority patent/WO2020154875A1/zh
Priority to CN201980000095.8A priority patent/CN109997230A/zh
Priority to CN202111188889.7A priority patent/CN113825196A/zh
Publication of WO2020154875A1 publication Critical patent/WO2020154875A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W36/00—Hand-off or reselection arrangements
    • H04W36/14—Reselecting a network or an air interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W36/00—Hand-off or reselection arrangements
    • H04W36/16—Performing reselection for specific purposes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/04—Wireless resource allocation
    • H04W72/044—Wireless resource allocation based on the type of the allocated resource
    • H04W72/0446—Resources in time domain, e.g. slots or frames
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/50—Allocation or scheduling criteria for wireless resources
    • H04W72/53—Allocation or scheduling criteria for wireless resources based on regulatory allocation policies
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/02—Terminal devices
    • H04W88/06—Terminal devices adapted for operation in multiple networks or having at least two operational modes, e.g. multi-mode terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/128—Active-matrix OLED [AMOLED] displays comprising two independent displays, e.g. for emitting information from two major sides of the display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel unit and a manufacturing method thereof, and a double-sided OLED display device.
  • the display panel with double-sided display is to glue two display panels with single-sided display together.
  • a pixel unit including: a substrate; a driving circuit layer disposed on one side of the substrate, the driving circuit layer including a first driving transistor and a second driving transistor;
  • the light emitting device includes: a first anode arranged on the side of the driving circuit layer away from the substrate and connected to the drain of the first driving transistor; a first functional layer arranged on the first anode away from the A side of the driving circuit layer; and a cathode, which is arranged on the side of the first functional layer away from the first anode; and a second light-emitting device, which includes: the cathode; and a second functional layer that is arranged on the The cathode is on a side away from the first functional layer; and a second anode is arranged on the side of the second functional layer away from the cathode and connected to the drain of the second driving transistor.
  • the cathode is a reflective cathode.
  • the first driving transistor and the second driving transistor are spaced apart on the substrate.
  • the driving circuit layer further includes a cathode trace connected to the cathode; wherein: the orthographic projection of the first light-emitting device on the substrate is located on the substrate of the first driving transistor. Between the orthographic projection on the substrate and the orthographic projection of the second drive transistor on the substrate, and the orthographic projection of the cathode trace on the substrate is located on the substrate of the first light-emitting device Between the orthographic projection and the orthographic projection of the second driving transistor on the substrate; or, the orthographic projection of the first driving transistor and the second driving transistor on the substrate is located on the first light emitting device The orthographic projection of the cathode trace on the substrate is located on the second side of the orthographic projection of the first light-emitting device on the substrate, and the second side is opposite to the first side Set up.
  • the pixel unit further includes: a planarization layer disposed between the driving circuit layer and the first light-emitting device; a first connecting wire and a second connecting wire, wherein the first The connecting wire, the second connecting wire and the first anode are spaced apart on the planarization layer; wherein the first anode passes through the first via hole penetrating the planarization layer and the first anode
  • the drain of a driving transistor is connected, the cathode is connected to the cathode trace through the first connecting wire and the second via hole penetrating the planarization layer, and the second anode is connected to the second connecting wire
  • a third via hole penetrating the planarization layer is connected to the drain of the second driving transistor.
  • the first light-emitting device further includes a first pixel defining layer on the first anode, the first connecting wire, and the second connecting wire, and the first pixel defining layer has The first opening and the second opening, the first functional layer is connected to the first anode through the first opening, and the cathode is connected to the first connecting wire through the second opening.
  • the orthographic projection of the first pixel defining layer on the substrate covers the orthographic projection of the first driving transistor and the second driving transistor on the substrate.
  • the second light emitting device further includes a second pixel defining layer on the cathode, the second pixel defining layer has a third opening, and the second functional layer passes through the third opening Connect with the cathode.
  • the first pixel defining layer further has a fourth opening
  • the second pixel defining layer further has a fifth opening
  • the second anode passes through the fourth opening and the fifth opening.
  • the second connecting wire is connected.
  • the material of the cathode is selected from one or more of the following: aluminum and silver.
  • a double-sided OLED display device including: a plurality of pixel units described in any one of the foregoing embodiments.
  • a method for manufacturing a pixel unit including: forming a driving circuit layer on one side of a substrate, the driving circuit layer including a first driving transistor and a second driving transistor; A first light-emitting device and a second light-emitting device are formed on the side of the driving circuit layer away from the substrate.
  • the first light-emitting device includes a first anode connected to the drain of the first driving transistor.
  • the first functional layer on the side away from the driving circuit layer, and the cathode on the side away from the first anode on the first functional layer, the second light-emitting device includes the cathode, and the cathode on the side away from the cathode.
  • forming a driving circuit layer on one side of the substrate includes: forming a first active layer for the first driving transistor and for the second driving transistor on one side of the substrate using the same process.
  • a second active layer of a transistor forming a gate dielectric layer covering the first active layer and the second active layer; forming a first gate and a second gate on the gate dielectric layer using the same process Gate; forming an interlayer insulating layer covering the first gate and the second gate; using the same process to form a first source and a first source penetrating the interlayer insulating layer and the gate dielectric layer Drain, second source, and second drain, wherein the first source and the first drain are connected to the first active layer, and the second source and the second drain The pole is connected to the second active layer.
  • the driving circuit layer further includes a cathode trace connected to the cathode on the gate dielectric layer, and the interlayer insulating layer also covers the cathode trace, wherein the cathode
  • the wiring, the first gate and the second gate are formed by the same process.
  • forming the first light emitting device and the second light emitting device on the side of the driving circuit layer away from the substrate includes: forming a first via hole on the side of the driving circuit layer away from the substrate. , The planarization layer of the second via and the third via; forming a conductive material layer on the side of the planarization layer away from the substrate; patterning the conductive material layer to form a first connecting wire, The second connecting wire and the first anode, wherein the first anode is connected to the drain of the first driving transistor through the first via hole, and the first connecting wire passes through the second via hole Connected to the cathode trace, the second connecting wire is connected to the drain of the second driving transistor through the third via; forming a first pixel defining layer, the first pixel defining layer has a first An opening and a second opening, the first opening exposes part of the first anode, and the second opening exposes part of the first connecting wire; forming the first function in the first opening Layer; forming the catho
  • the first pixel defining layer further has a fourth opening, and the fourth opening exposes a part of the second connecting wire; the second pixel defining layer further has a fifth opening, the The fifth opening is in communication with the fourth opening, wherein the second anode is in contact with the exposed part of the second connecting wire.
  • FIG. 1 is a schematic structural diagram of a pixel unit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic flowchart of a method for manufacturing a pixel unit according to an embodiment of the present disclosure
  • 3A to 3H show schematic cross-sectional views of structures obtained at different stages of forming a pixel unit according to some embodiments of the present disclosure.
  • a specific component when it is described that a specific component is located between the first component and the second component, there may or may not be an intermediate component between the specific component and the first component or the second component.
  • the specific component When it is described that a specific component is connected to another component, the specific component may be directly connected to the other component without an intermediate component, or may not be directly connected to the other component but with an intermediate component.
  • the two single-sided display panels in the current double-sided display panels have their own array substrates, and the double-sided display panel has a relatively large thickness, which is not conducive to the development of light and thin display panels.
  • Fig. 1 is a schematic structural diagram of a pixel unit according to an embodiment of the present disclosure.
  • the pixel unit includes a substrate 101, a driving circuit layer 102, a first light-emitting device (including at least a first anode 103, a first functional layer 104, and a cathode 105) and a second light-emitting device (including at least a cathode 105, a cathode 105).
  • a first light-emitting device including at least a first anode 103, a first functional layer 104, and a cathode 105
  • a second light-emitting device including at least a cathode 105, a cathode 105.
  • Two functional layer 106 and second anode 107 Two functional layer 106 and second anode 107).
  • the driving circuit layer 102 is provided on one side of the substrate 101.
  • the driving circuit layer 102 includes a first driving transistor 112 (eg, a thin film transistor) configured to drive a first light emitting device and a second driving transistor 122 (eg, a thin film transistor) configured to drive a second light emitting device.
  • the driving circuit layer 102 may at least include switching transistors, storage capacitors, etc. not shown in FIG. 1.
  • the first driving transistor 112 includes an active layer 1121, a source 1122, a drain 1123, a gate 1124, and a gate dielectric layer 1125.
  • the second driving transistor 122 includes an active layer 1221, a source 1222, a drain 1223, and a gate dielectric layer 1125.
  • the driving circuit layer 102 further includes a cathode trace 132 connected to the cathode 105.
  • the first anode 103 is disposed on the side of the driving circuit layer 102 away from the substrate 101 and connected to the drain 1123 of the first driving transistor 112.
  • the first anode 103 may be connected to the drain 1123 through the first via hole 11 penetrating the planarization layer 10.
  • the material of the planarization layer 10 may include, for example, a resin material such as polyimide.
  • the first functional layer 104 is disposed on the side of the first anode 103 away from the driving circuit layer 102.
  • the first functional layer 104 includes at least a first light-emitting layer.
  • the material of the first light-emitting layer may include, for example, an organic electroluminescent material or the like.
  • the first functional layer 104 may further include at least one of a first hole transport layer and a first electron transport layer, and the first hole transport layer is located between the first light-emitting layer and the first anode 103 , The first electron transport layer is located between the first light-emitting layer and the cathode 105.
  • the first functional layer 104 may further include at least one of a first hole injection layer and a first electron injection layer, and the first hole injection layer is located between the first hole transport layer and the first anode 103 In between, the first electron injection layer is located between the first electron transport layer and the cathode 105.
  • the cathode 105 is arranged on the side of the first functional layer 104 away from the first anode 103. In some embodiments, the cathode 105 may be connected to the cathode trace 132 in the driving circuit layer 102.
  • the second functional layer 106 is disposed on the side of the cathode 105 away from the first functional layer 104.
  • the second functional layer 106 includes at least a second light-emitting layer.
  • the material of the second light-emitting layer may include, for example, organic electroluminescent materials and the like.
  • the second functional layer 104 may further include at least one of a second hole transport layer and a second electron transport layer, and the second hole transport layer is located between the second light-emitting layer and the second anode 103 , The second electron transport layer is located between the second light-emitting layer and the cathode 105.
  • the second functional layer 104 may further include at least one of a second hole injection layer and a second electron injection layer, and the second hole injection layer is located between the second hole transport layer and the second anode 103 In between, the second electron injection layer is located between the second electron transport layer and the cathode 105.
  • the second anode 107 is disposed on the side of the second functional layer 106 away from the cathode 105 and connected to the drain 1223 of the second driving transistor 122.
  • the pixel unit further includes an encapsulation layer 108 covering the second anode 107.
  • the encapsulation layer 108 may include, for example, two inorganic layers and an organic layer between the two inorganic layers.
  • the first driving transistor 112 is used to drive the first light emitting device to emit light in the bottom emission mode
  • the second driving transistor 122 is used to drive the second light emitting device to emit light in the top emission mode.
  • the cathode 105 may be a transparent cathode. In other embodiments, the cathode 105 is a reflective cathode, so that the light emitted by the first functional layer 103 and the second functional layer 106 will not affect each other as much as possible. In other words, the cathode 105 may be configured to reflect at least part of the light emitted by the first functional layer 104 to the side facing the substrate 101 and at least part of the light emitted from the second functional layer 106 to the side away from the substrate 101.
  • the light emitted by the first light-emitting layer in the first functional layer 104 is reflected by the cathode 105 and then transmitted through the first anode 103 to achieve bottom light emission, that is, light from top to bottom.
  • the light emitted by the second light-emitting layer in the second functional layer 106 is reflected by the cathode 105 and then transmitted through the second anode 107 to achieve top-emission, that is, to emit light from bottom to top.
  • the reflectivity of the cathode 105 to visible light may be higher, for example, greater than 90%, so as to further prevent the light emitted by the first functional layer 103 and the second functional layer 106 from affecting each other as much as possible.
  • the material of the cathode 105 may be selected from one or more of the following: metals with high reflectivity such as aluminum and silver, or alloys including at least one of the foregoing metals, and the like.
  • the first anode 103 and the second anode 107 are transparent anodes.
  • the transmittance of the first anode 103 and the second anode 107 to visible light is relatively high, for example, it may be greater than 90% to realize the transmission of visible light. .
  • the driving circuit layer includes a first driving transistor and a second driving transistor, the first driving transistor is connected to the first anode, and the second driving transistor is connected to the second anode.
  • the first driving transistor and the second driving transistor are used to drive different light emitting devices to emit light.
  • the first driving transistor 112 and the second driving transistor 122 are disposed on the substrate 101 with an interval.
  • the functional layers in the first driving transistor 112 and the second driving transistor 122 can be formed by the same process, and the process is simpler.
  • the active layer 1121 of the first driving transistor 112 and the active layer 1221 of the second driving transistor 122 are formed by the same process; the gate dielectric layer 1125 of the first driving transistor 112 and the gate of the second driving transistor 122 The dielectric layer 1225 is formed by the same process; the source 1123 of the first driving transistor 112, the drain 1124 of the first driving transistor 112, the source 1223 of the second driving transistor 122, and the drain 1224 of the second driving transistor 122 are The gate electrode 1124 of the first driving transistor 112 and the gate electrode 1224 of the second driving transistor 122 are formed by the same process. A detailed description will be given later in conjunction with the manufacturing method of the pixel unit.
  • using the same process means using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • a patterning process may include multiple exposure, development or etching processes.
  • the specific pattern formed can be continuous or discontinuous. These particular graphics may be at different heights or have different thicknesses.
  • the cathode wiring 132 may be arranged at different positions in the driving circuit layer 102. The description is given below in combination with different embodiments.
  • the orthographic projection of the first light-emitting device on the substrate 101 is located between the orthographic projection of the first driving transistor 112 on the substrate 101 and the orthographic projection of the second driving transistor 122 on the substrate 101, and the cathode goes The orthographic projection of the line 132 on the substrate 101 is located between the orthographic projection of the first light-emitting device on the substrate 101 and the orthographic projection of the second driving transistor 122 on the substrate 101.
  • the orthographic projection of the first driving transistor 112 and the second driving transistor 122 on the substrate 101 is located on the first side of the first light emitting device, and the orthographic projection of the cathode trace 132 on the substrate 101 is located on the first light emitting device.
  • the device is on the second side of the orthographic projection of the substrate 101.
  • the second side is opposite to the first side.
  • the orthographic projection of the first driving transistor 112 and the second driving transistor 122 on the substrate 101 is on the left side of the orthographic projection of the first light-emitting device on the substrate 101, and the orthographic projection of the cathode wiring 132 on the substrate 101 is positioned on the first A light emitting device is on the right side of the orthographic projection on the substrate 101.
  • the first driving transistor 112 and the second driving transistor 122 are arranged on the same side, and the cathode wiring 132 is arranged on the other side, which helps to increase the aperture ratio of the pixel unit.
  • the pixel unit may further include a planarization layer 10 disposed between the driving circuit layer 102 and the first light emitting device.
  • the pixel unit may further include a first connecting wire 108 and a second connecting wire 109.
  • the first connection wire 108, the second connection wire 109, and the first anode 103 are spaced apart on the surface of the planarization layer 10.
  • the first anode 103, the first connecting wire 108, and the second connecting wire 109 may be formed by the same process, that is, by patterning the same conductive material layer.
  • the first anode 103 is connected to the drain 123 of the first driving transistor 112 through a first via 11 penetrating the planarization layer 10.
  • the cathode 104 may be connected to the cathode trace 132 through the first connecting wire 108 and the second via hole 12 passing through the planarization layer 10.
  • the second anode 107 is connected to the drain 1223 of the second driving transistor 122 through the second connecting wire 109 and the third via 13 penetrating the planarization layer 10.
  • the first light-emitting device in the pixel unit further includes a first pixel defining layer 20 on the first anode 103, the first connecting wire 108 and the second connecting wire 109.
  • the first pixel defining layer 20 has a first opening 21 and a second opening 22.
  • the first functional layer 104 is connected to the first anode 103 through the first opening 21, and the cathode 105 is connected to the first connecting wire 108 through the second opening 22. It should be understood that the first opening 21 exposes a part of the first anode 103, and the second opening 22 exposes a part of the first connecting wire 108.
  • the first pixel defining layer 20 covers the portion of the first anode 103 and the portion of the first connecting wire 108, thereby defining the first opening 21 and the second opening 22.
  • the first functional layer 104 is disposed in the first opening 21, and the cathode 105 is in contact with the exposed part of the first connecting wire 108 (ie, the first connecting wire 108 at the bottom of the second opening 22).
  • the orthographic projection of the first pixel defining layer 20 on the substrate 101 covers the orthographic projection of the first driving transistor 112 and the second driving transistor 122 on the substrate 101.
  • the orthographic projection of the first driving transistor 112 and the second driving transistor 122 on the substrate 101 is within the orthographic projection of the first pixel defining layer 20 on the substrate 101, so that the light emitted by the first light emitting device does not pass through the A driving transistor 112 and a second driving transistor 122 are used to improve the light extraction efficiency.
  • the first driving transistor 112 and the second driving transistor 122 shown in FIG. 1 are located on both sides of the cathode wiring 132, this is not restrictive.
  • the first driving transistor 112 and the second driving transistor 122 may be located on the same side of the cathode wiring 132, for example, the first driving transistor 112 and the second driving transistor 122 are both located on the left side of the cathode wiring 132 Or right. In some embodiments, the first driving transistor 112 and the second driving transistor 122 may be sequentially arranged below the first pixel defining layer 20 in a direction perpendicular to the paper surface.
  • the second light emitting device in the pixel unit further includes a second pixel defining layer 30 on the cathode 105.
  • the second pixel defining layer 30 has a third opening 31, and the second functional layer 106 is connected to the cathode 105 through the third opening 31.
  • the third opening 31 may expose a part of the cathode 105, and the second functional layer 106 is disposed in the third opening 31 and is in contact with the exposed part of the cathode 105.
  • the following describes a specific implementation manner in which the second anode 107 is connected to the drain 1223 of the second driving transistor 122 through the second connecting wire 109.
  • the first pixel defining layer 20 may have a fourth opening 23
  • the second pixel defining layer 30 may have a fifth opening 32
  • the second anode 107 may pass through the fourth opening 23 and the fifth opening 32.
  • Connect with the second connecting wire 109 the first pixel defining layer 20 and the second pixel defining layer 30 may expose a part of the second connecting wire 109, that is, the first pixel defining layer 20 and the second pixel defining layer 30 cover a part of the second connecting wire 109 .
  • the second anode 107 is in contact with the exposed portion of the second connecting wire 109.
  • the exposed portion of the second connecting wire 109 is the portion of the second connecting wire 109 that is not covered by the first pixel defining layer 20 and the second pixel defining layer 30.
  • the first pixel defining layer 20 may have a fourth opening 23 and the second pixel defining layer 30 may have a fifth opening 32 communicating with the fourth opening 23.
  • the fourth opening 23 and the fifth opening 32 expose a part of the second connecting wire 109.
  • FIG. 2 is a schematic flowchart of a method for manufacturing a pixel unit according to an embodiment of the present disclosure.
  • 3A to 3H show schematic cross-sectional views of structures obtained at different stages of forming a pixel unit according to some embodiments of the present disclosure.
  • a driving circuit layer 102 is formed on one side of the substrate 101, as shown in FIG. 3A.
  • the driving circuit layer 102 includes a first driving transistor 112 and a second driving transistor 122.
  • the first driving transistor 112 and the second driving transistor 122 may be formed as follows: First, the active layer 1121 for the first driving transistor 112 and the active layer 1121 for the second driving transistor 122 are formed on the substrate 101 using the same process. Active layer 1221. Then, a gate dielectric layer 142 covering the active layer 1121 and the active layer 1221 is formed. Here, the portion of the gate dielectric layer 142 on the active layer 1121 may serve as the gate dielectric layer 1125, and the portion of the gate dielectric layer 142 on the active layer 1221 may serve as the gate dielectric layer 1225. After that, a gate 1124 and a gate 1224 are formed on the gate dielectric layer 142.
  • the gate 1124 is located on the gate dielectric layer 1125 and the gate 1224 is located on the gate dielectric layer 1225.
  • an interlayer insulating layer 152 covering the gate electrode 1124 and the gate electrode 1224 is formed.
  • the source electrode 1122, the drain electrode 1123, the source electrode 1222, and the drain electrode 1223 that penetrate the interlayer insulating layer 152 and the gate dielectric layer 142 are formed.
  • the source electrode 1122 and the drain electrode 1123 are connected to the active layer 1121
  • the source electrode 1222 and the drain electrode 1223 are connected to the active layer 1221.
  • the active layer 1121 may also be referred to as a first active layer, and the active layer 1221 may also be referred to as a second active layer.
  • the gate dielectric layer 1125 may also be referred to as a first gate dielectric layer, and the gate dielectric layer 1225 may also be referred to as a second gate dielectric layer.
  • Other components in the first driving transistor 112 and the second driving transistor 122 can also be distinguished in this manner, and details are not described herein again.
  • a cathode trace 132 may also be formed on the gate dielectric layer 142, and the cathode trace 132 is connected to the cathode formed subsequently.
  • the gate 1124 of the first driving transistor 112, the gate 1224 of the second driving transistor 122, and the cathode wiring 132 may be formed by the same process.
  • a metal material layer may be deposited on the gate dielectric layer 142, and then the formed metal material layer may be patterned to form a gate electrode. 1124, gate 1224 and cathode wiring 132.
  • the formed driving circuit layer 102 may also include other devices, such as switching transistors.
  • step 204 a first light emitting device and a second light emitting device are formed on the side of the driving circuit layer 102 away from the substrate 101.
  • a planarization layer 10 having a first via hole 11 is formed on the side of the driving circuit layer 102 away from the substrate 101. Then, a conductive material layer is formed on the side of the planarization layer 10 away from the substrate 101. After that, the conductive material layer is patterned to form the first anode 11.
  • the first anode 103 is connected to the drain 1123 of the first driving transistor 112 through the first via 11.
  • the material of the first anode 103 may include metal oxides such as indium tin oxide.
  • the planarization layer 10 further has a second via hole 12 and a third via hole 13.
  • the first connecting wire 108 and the second connecting wire 109 may also be formed on the side of the driving circuit layer 102 away from the substrate 101.
  • the subsequently formed cathode may be connected to the cathode wiring 132 through the first connecting wire 108 and the second via 12, and the subsequently formed second anode may be connected to the second driving transistor via the second connecting wire 109 and the third via 13
  • the drain 1223 of 122 is connected.
  • the planarization layer 10 can be formed on the side of the driving circuit layer 102 away from the substrate 101 first; then, the first via 11 connected to the drain 1123, the second via 12 connected to the cathode trace 132, and the connection To the third via 13 of the drain 1223; after that, a first connector located in the first via 11, a second connector located in the second via 12, and a third connection located in the third via 13 are formed Components, the first anode 103, the first connecting wire 108 and the second connecting wire 109.
  • the first via 11, the second via 12, and the third via 13 may be filled and covered.
  • the first connector formed in the first via 11 and the first anode 103 are integrally arranged
  • the second connector formed in the second via 12 and the second connecting wire 108 are integrally arranged
  • the third via The third connecting member formed in 13 and the second connecting wire 109 are integrally arranged.
  • the first via hole 11, the second via hole 12, and the third via hole 13 may be filled with conductive material through a separate process to form the first connector, the second connector, and the third via.
  • the first connecting piece and the first anode 103 are not integrally arranged
  • the second connecting piece and the second connecting wire 108 are not integrally arranged
  • the third connecting piece and the second connecting wire 109 are not integrally arranged.
  • the first pixel defining layer 20 has a first opening 21 and a second opening 22.
  • the first opening 21 exposes a part of the first anode 103
  • the second opening 22 exposes a part of the first connecting wire 108.
  • a first functional layer 104 is formed in the first opening 21.
  • the first functional layer 104 can be formed by an inkjet printing process.
  • a cathode 105 is formed on the side of the first functional layer 104 away from the first anode 103.
  • the cathode 105 is in contact with the exposed portion of the first connection wire 108.
  • the thickness of the cathode 105 may be, for example, 150 angstroms to 300 angstroms, such as 200 angstroms, 250 angstroms, and so on.
  • the cathode 105 within such a thickness range on the one hand can block the light in the subsequent exposure process (for example, the exposure process used when forming the second pixel defining layer 30) from passing through the cathode 105, so as to prevent the light from reaching the first underneath the cathode 105.
  • a functional layer 104 causes damage.
  • the cathode 105 within such a thickness range makes it difficult for subsequent etching processes (for example, a wet etching process to remove the photoresist used when forming the second pixel defining layer 30) to etch through the cathode 105. Avoid damage to the first functional layer 104 under the cathode 105.
  • the cathode material layer may be deposited by a process such as physical vapor deposition; then, the cathode material layer may be etched using a wet etching process or a laser induced etching process to form the cathode 105 .
  • a second pixel defining layer 30 is formed.
  • the second pixel defining layer 30 has a third opening 31, and the third opening 31 exposes part of the cathode 105.
  • the second functional layer 106 is formed in the third opening 31.
  • the second functional layer 106 can be formed by an inkjet printing process.
  • a second anode 107 is formed on the side of the second functional layer 106 away from the cathode 105.
  • the material of the second anode 107 may include a metal oxide, such as indium tin oxide or the like.
  • the material of the second anode 107 may include a conductive polymer.
  • a conductive polymer can be formed as the second anode 107 by an inkjet printing process.
  • the temperature for forming the metal oxide is greater than 400°C, and the formation of the second anode 107 by the inkjet printing process can avoid damage to the second functional layer 106 caused by the high temperature process, and will not affect the luminous efficiency and luminous efficiency of the second functional layer 106.
  • the life of the pixel unit when the second functional layer 106 and the second anode 107 are both formed by an inkjet printing process, the process is more convenient to realize.
  • the formed first pixel defining layer 20 may further have a fourth opening 23, and the fourth opening 23 exposes a part of the second connecting wire 109.
  • the formed second pixel defining layer may also have a fifth opening 32 which communicates with the fourth opening 23.
  • the fifth opening 32 and the fourth opening 23 expose part of the second connecting wire 109, and the second anode 107 contacts the exposed part of the second connecting wire 109.
  • openings that expose portions of the second connecting wires 109 may be formed respectively.
  • the formed first pixel defining layer 20 may not have the fourth opening 23, that is, the first pixel defining layer 20 may completely cover the second connecting wire 109.
  • an opening penetrating through the second pixel defining layer 30 and the first pixel defining layer 20 and connected to the second connecting wire 109 may be formed.
  • an encapsulation layer 108 covering the second anode 105 may be formed to form the pixel unit shown in FIG. 1.
  • the encapsulation layer 108 may be formed by a process such as plasma chemical vapor deposition.
  • the encapsulation layer 108 can block water vapor or oxygen from entering the first functional layer 104 and the second functional layer 106 to avoid damage to the light-emitting layers in the first functional layer 104 and the second functional layer 106.
  • the packaging layer 108 may also cover a part of the driving circuit layer 102.
  • a double-sided display panel including a plurality of pixel units can be formed through a single manufacturing process, and there is no need to form two display panels separately and then attach the two display panels together. In addition, there is no need to form two array substrates, and the thickness of the display panel is smaller.
  • the embodiment of the present disclosure also provides a double-sided OLED display device.
  • the double-sided OLED display device may include a plurality of pixel units of any one of the foregoing embodiments.
  • the double-sided OLED display device may be, for example, a display panel, a mobile terminal, a television, a monitor, a notebook computer, a digital photo frame, a navigator, an electronic paper, a virtual reality system, or any other product or component with a display function.
  • the double-sided OLED display device further includes an encapsulation layer 110 covering a plurality of pixel units.
  • the plurality of pixel units may include, for example, a red pixel unit (R), a green pixel unit (G), and a blue pixel unit (B).
  • the pixel unit may also be referred to as a sub-pixel.
  • the driving circuit layer 102 in the display panel may include a first driving transistor 112 and a second driving transistor 122 for each pixel unit. Therefore, there is no need to address two single-sided
  • the display panel of the display is provided with two array substrates respectively, which reduces the thickness of the display panel.
  • the control of the image of the display panel is more flexible. For example, you can control the two sides of the display panel to display different screens.

Abstract

一种像素单元及其制造方法和双面OLED显示装置，像素单元包括：基板(101)；设置在基板(101)的一侧的驱动电路层(102)，包括第一驱动晶体管(112)和第二驱动晶体管(122)；第一发光器件和第二发光器件。第一发光器件包括：第一阳极(103)，设置在驱动电路层(102)远离基板(101)的一侧，且与第一驱动晶体管(112)的漏极(1123)连接；第一功能层(104)，设置在第一阳极(103)远离驱动电路层(102)的一侧；阴极(105)，设置在第一功能层(104)远离第一阳极(103)的一侧。第二发光器件包括：阴极(105)；第二功能层(106)，设置在阴极(105)远离第一功能层(104)的一侧；第二阳极(107)，设置在第二功能层(106)远离阴极(105)的一侧，且与第二驱动晶体管(122)的漏极(1223)连接。

Description

像素单元及其制造方法和双面OLED显示装置 技术领域
本公开涉及显示技术领域，尤其涉及像素单元及其制造方法和双面OLED显示装置。
背景技术
随着显示技术的发展，双面显示成为新的趋势。目前，双面显示的显示面板是将两个单面显示的显示面板贴合在一起。
发明内容
根据本公开实施例的一方面，提供一种像素单元，包括：基板；驱动电路层，设置在所述基板的一侧，所述驱动电路层包括第一驱动晶体管和第二驱动晶体管；第一发光器件，包括：第一阳极，设置在所述驱动电路层远离所述基板的一侧，并且与所述第一驱动晶体管的漏极连接；第一功能层，设置在所述第一阳极远离所述驱动电路层的一侧；和阴极，设置在所述第一功能层远离所述第一阳极的一侧；和第二发光器件，包括：所述阴极；第二功能层，设置在所述阴极远离所述第一功能层的一侧；和第二阳极，设置在所述第二功能层远离所述阴极的一侧，并且与所述第二驱动晶体管的漏极连接。
在一些实施例中，所述阴极为反射式阴极。
在一些实施例中，所述第一驱动晶体管和所述第二驱动晶体管间隔开地设置在所述基板上。
在一些实施例中，所述驱动电路层还包括与所述阴极连接的阴极走线；其中：所述第一发光器件在所述基板上的正投影位于所述第一驱动晶体管在所述基板上的正投影与所述第二驱动晶体管在所述基板上的正投影之间，并且，所述阴极走线在所述基板上的正投影位于所述第一发光器件在所述基板上的正投影与所述第二驱动晶体管在所述基板上的正投影之间；或者，所述第一驱动晶体管和所述第二驱动晶体管在所述基板上的正投影位于所述第一发光器件的第一侧，所述阴极走线在所述基板上的正投影位于所述第一发光器件在所述基板上的正投影的第二侧，所述第二侧与所述第一侧相对设置。
在一些实施例中，所述像素单元还包括：平坦化层，设置在所述驱动电路层与所述第一发光器件之间；第一连接导线和第二连接导线，其中，所述第一连接导线、所述第二连接导线和所述第一阳极间隔开地设置在所述平坦化层上；其中，所述第一阳极通过贯穿所述平坦化层的第一过孔与所述第一驱动晶体管的漏极连接，所述阴极通过所述第一连接导线和贯穿所述平坦化层的第二过孔与所述阴极走线连接，所述第二阳极通过所述第二连接导线和贯穿所述平坦化层的第三过孔与所述第二驱动晶体管的漏极连接。
在一些实施例中，所述第一发光器件还包括位于所述第一阳极、所述第一连接导线和所述第二连接导线上的第一像素界定层，所述第一像素界定层具有第一开口和第二开口，所述第一功能层通过所述第一开口与所述第一阳极连接，所述阴极通过所述第二开口与所述第一连接导线连接。
在一些实施例中，所述第一像素界定层在所述基板上的正投影覆盖所述第一驱动晶体管和所述第二驱动晶体管在所述基板上的正投影。
在一些实施例中，所述第二发光器件还包括位于所述阴极上的第二像素界定层，所述第二像素界定层具有第三开口，所述第二功能层通过所述第三开口与所述阴极连接。
在一些实施例中，所述第一像素界定层还具有第四开口，所述第二像素界定层还具有第五开口，所述第二阳极通过所述第四开口和所述第五开口与所述第二连接导线连接。
在一些实施例中，所述阴极的材料选自下列中的一种或多种：铝、银。
根据本公开实施例的另一方面，提供一种双面OLED显示装置，包括：多个上述任意一个实施例所述的像素单元。
根据本公开实施例的又一方面，提供一种像素单元的制造方法，包括：在基板的一侧形成驱动电路层，所述驱动电路层包括第一驱动晶体管和第二驱动晶体管；在所述驱动电路层远离所述基板的一侧形成第一发光器件和第二发光器件，所述第一发光器件包括与所述第一驱动晶体管的漏极连接的第一阳极、在所述第一阳极远离所述驱动电路层一侧的第一功能层、以及在所述第一功能层远离所述第一阳极一侧的阴极，所述第二发光器件包括所述阴极、在所述阴极远离所述第一功能层的一侧的第二功能层、以及在所述第二功能层远离所述阴极的一侧且与所述第二驱动晶体管的漏极连接的第二阳极。
在一些实施例中，在基板的一侧形成驱动电路层包括：在所述基板的一侧利用同一工艺形成用于所述第一驱动晶体管的第一有源层和用于所述第二驱动晶体管的第二有源层；形成覆盖所述第一有源层和所述第二有源层的栅极电介质层；利用同一工艺在所述栅极电介质层上形成第一栅极和第二栅极；形成覆盖所述第一栅极和所述第二栅极的层间绝缘层；利用同一工艺形成贯穿所述层间绝缘层和所述栅极电介质层的第一源极、第一漏极、第二源极和第二漏极，其中，所述第一源极和所述第一漏极连接到所述第一有源层，所述第二源极和所述第二漏极连接到所述第二有源层。
在一些实施例中，所述驱动电路层还包括在所述栅极电介质层上与所述阴极连接的阴极走线，所述层间绝缘层还覆盖所述阴极走线，其中，所述阴极走线、所述第一栅极和所述第二栅极是利用同一工艺形成的。
在一些实施例中，在所述驱动电路层远离所述基板的一侧形成第一发光器件和第二发光器件包括：在所述驱动电路层远离所述基板的一侧形成具有第一过孔、第二过孔和第三过孔的平坦化层；在所述平坦化层远离所述基板的一侧形成导电材料层；对所述导电材料层进行图案化，以形成第一连接导线、第二连接导线以及所述第一阳极，其中，所述第一阳极通过所述第一过孔与所述第一驱动晶体管的漏极连接，所述第一连接导线通过所述第二过孔与所述阴极走线连接，所述第二连接导线通过所述第三过孔与所述第二驱动晶体管的漏极连接；形成第一像素界定层，所述第一像素界定层具有第一开口和第二开口，所述第一开口使得所述第一阳极的部分露出，所述第二开口使得所述第一连接导线的部分露出；在所述第一开口中形成所述第一功能层；在所述第一功能层远离所述第一阳极的一侧形成所述阴极，所述阴极与所述第一连接导线的露出部分接触；形成第二像素界定层，所述第二像素界定层具有第三开口，所述第三开口使得所述阴极的部分露出；在所述第三开口中形成所述第二功能层；在所述第二功能层远离所述阴极的一侧形成所述第二阳极。
在一些实施例中，所述第一像素界定层还具有第四开口，所述第四开口使得所述第二连接导线的部分露出；所述第二像素界定层还具有第五开口，所述第五开口与所述第四开口连通，其中，所述第二阳极与所述第二连接导线的露出部分接触。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是根据本公开一个实施例的像素单元的结构示意图；
图2是根据本公开一个实施例的像素单元的制造方法的流程示意图；
图3A-图3H示出了根据本公开一些实施例的形成像素单元的不同阶段得到的结构的截面示意图。
应当明白，附图中所示出的各个部分的尺寸并不必然是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定部件位于第一部件和第二部件之间时，在该特定部件与第一部件或第二部件之间可以存在居间部件，也可以不存在居间部件。当描述到特定部件连接其它部件时，该特定部件可以与所述其它部件直接连接而不具有居间部件，也可以不与所述其它部件直接连接而具有居间部件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
发明人注意到，目前的双面显示的显示面板中的两个单面显示的显示面板具有各自的阵列基板，双面显示的显示面板的厚度较大，不利于显示面板的轻薄化发展。
图1是根据本公开一个实施例的像素单元的结构示意图。
如图1所示，像素单元包括基板101、驱动电路层102、第一发光器件(至少包括第一阳极103、第一功能层104和阴极105)和第二发光器件(至少包括阴极105、第二功能层106和第二阳极107)。
驱动电路层102设置在基板101的一侧。这里，驱动电路层102包括被配置为驱动第一发光器件的第一驱动晶体管112(例如薄膜晶体管)和被配置为驱动第二发光器件的第二驱动晶体管122(例如薄膜晶体管)。应理解，驱动电路层102至少还可以包括图1未示出的开关晶体管、存储电容等。第一驱动晶体管112包括有源层1121、源极1122、漏极1123、栅极1124和栅极电介质层1125，第二驱动晶体管122包括有源层1221、源极1222、漏极1223、栅极1124和栅极电介质层1225。有源层1121和有源层1221的材料例如可以包括多晶硅(例如p型低温多晶硅)、氧化物半导体等半导体材料等。在一些实施例中，驱动电路层102还包括与阴极105连接的阴极走线132。
第一阳极103设置在驱动电路层102远离基板101的一侧，并且与第一驱动晶体管112的漏极1123连接。例如，第一阳极103可以通过贯穿平坦化层10的第一过孔11与漏极1123连接。平坦化层10的材料例如可以包括聚酰亚胺等树脂材料。
第一功能层104设置在第一阳极103远离驱动电路层102的一侧。第一功能层104至少包括第一发光层。第一发光层的材料例如可以包括有机电致发光材料等。在一些实施例中，第一功能层104还可以包括第一空穴传输层和第一电子传输层中的至少一层，第一空穴传输层位于第一发光层和第一阳极103之间，第一电子传输层位于第一发光层和阴极105之间。在一些实施例中，第一功能层104还可以包括第一空穴注入层和第一电子注入层中的至少一层，第一空穴注入层位于第一空穴传输层和第一阳极103之间，第一电子注入层位于第一电子传输层和阴极105之间。
阴极105设置在第一功能层104远离第一阳极103的一侧。在一些实施例中，阴极105可以与驱动电路层102中的阴极走线132连接。
第二功能层106设置在阴极105远离第一功能层104的一侧。第二功能层106至少包括第二发光层。第二发光层的材料例如可以包括有机电致发光材料等。在一些实施例中，第二功能层104还可以包括第二空穴传输层和第二电子传输层中的至少一层， 第二空穴传输层位于第二发光层和第二阳极103之间，第二电子传输层位于第二发光层和阴极105之间。在一些实施例中，第二功能层104还可以包括第二空穴注入层和第二电子注入层中的至少一层，第二空穴注入层位于第二空穴传输层和第二阳极103之间，第二电子注入层位于第二电子传输层和阴极105之间。
第二阳极107设置在第二功能层106远离阴极105的一侧，并且与第二驱动晶体管122的漏极1223连接。
在一些实施例中，像素单元还包括覆盖第二阳极107的封装层108。封装层108例如可以包括两层无机层、以及位于两层无机层之间的有机层。
应理解，第一发光器件和第二发光器件共用阴极105。第一驱动晶体管112用于驱动第一发光器件以底发光模式发光，第二驱动晶体管122用于驱动第二发光器件以顶发光模式发光。
在一些实施例中，阴极105可以为透明阴极。在另一些实施例中，阴极105为反射式阴极，以使得第一功能层103和第二功能层106发出的光尽可能不会互相影响。换言之，阴极105可以被配置为将第一功能层104发出的光的至少一部分反射至朝向基板101的一侧，将第二功能层106发出的光的至少一部分反射至远离基板101的一侧。这样，在第一发光器件中，第一功能层104中的第一发光层发出的光经阴极105反射后，再透过第一阳极103，以实现底发光，即从上向下发光。在第二发光器件中，第二功能层106中的第二发光层发出的光经阴极105反射后，再透过第二阳极107，以实现顶发光，即从下向上发光。
在一些实施例中，阴极105对可见光的反射率可以较高，例如大于90％，以进一步使得第一功能层103和第二功能层106发出的光尽可能不会互相影响。作为示例，阴极105的材料可以选自下列中的一种或多种：铝、银等具有高反射率金属、或者包括上述金属中的至少一种的合金等。在一些实施例中，第一阳极103和第二阳极107是透明阳极，例如，第一阳极103和第二阳极107对可见光的透射率较高，例如可以大于90％，以实现可见光的透过。
上述实施例中，驱动电路层包括第一驱动晶体管和第二驱动晶体管，第一驱动晶体管与第一阳极连接，第二驱动晶体管与第二阳极连接。第一驱动晶体管和第二驱动晶体管用于驱动不同的发光器件发光。这样的像素单元中，无需在第二阳极远离基板的一侧额外设置与第二阳极连接的薄膜晶体管，厚度更小。
在一些实施例中，参见图1，第一驱动晶体管112和第二驱动晶体管122间隔开 地设置在基板101上。在某些实施例中，第一驱动晶体管112和第二驱动晶体管122中的各功能层可以利用同一工艺来形成，制程更为简单。例如，第一驱动晶体管112的有源层1121和第二驱动晶体管122的有源层1221是利用同一工艺形成的；第一驱动晶体管112的栅极电介质层1125和第二驱动晶体管122的栅极电介质层1225是利用同一工艺形成的；第一驱动晶体管112的源极1123、第一驱动晶体管112的漏极1124、第二驱动晶体管122的源极1223和第二驱动晶体管122的漏极1224是利用同一工艺形成的；第一驱动晶体管112的栅极1124和第二驱动晶体管122的栅极1224是利用同一工艺形成的。后文将结合像素单元的制造方法进行详细说明。
应理解，“利用同一工艺”是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层进行图案化。需要说明的是，根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺。所形成的特定图形可以是连续的也可以是不连续的。这些特定图形可能处于不同的高度或者具有不同的厚度。
阴极走线132可以设置在驱动电路层102中的不同位置。下面结合不同实施例进行说明。
在一些实施例中，第一发光器件在基板101上的正投影位于第一驱动晶体管112在基板101上的正投影与第二驱动晶体管122在基板101上的正投影之间，并且，阴极走线132在基板101上的正投影位于第一发光器件在基板101上的正投影与第二驱动晶体管122在基板101上的正投影之间。
在另一些实施例中，第一驱动晶体管112和第二驱动晶体管122在基板101上的正投影位于第一发光器件的第一侧，阴极走线132在基板101上的正投影位于第一发光器件在基板101上的正投影的第二侧。这里，第二侧与第一侧相对设置。例如，第一驱动晶体管112和第二驱动晶体管122在基板101上的正投影位于第一发光器件在基板101上的正投影的左侧，而阴极走线132在基板101上的正投影位于第一发光器件在基板101上的正投影的右侧。这样的方式下，第一驱动晶体管112和第二驱动晶体管122设置在同一侧，阴极走线132设置在另一侧，有助于提高像素单元的开口率。
在一些实施例中，参见图1，像素单元还可以包括设置在驱动电路层102与第一发光器件之间的平坦化层10。像素单元还可以包括第一连接导线108和第二连接导线109。第一连接导线108、第二连接导线109和第一阳极103间隔开地设置在平坦化层10的表面上。在一些实现方式中，第一阳极103、第一连接导线108和第二连接导线 109可以通过同一工艺形成，即通过对同一导电材料层进行图案化来形成。
第一阳极103通过贯穿平坦化层10的第一过孔11与第一驱动晶体管112的漏极123连接。阴极104可以通过第一连接导线108和贯穿平坦化层10的第二过孔12与阴极走线132连接。第二阳极107通过第二连接导线109和贯穿平坦化层10的第三过孔13与第二驱动晶体管122的漏极1223连接。
在一些实现方式中，参见图1，像素单元中的第一发光器件还包括位于第一阳极103、第一连接导线108和第二连接导线109上的第一像素界定层20。第一像素界定层20具有第一开口21和第二开口22。第一功能层104通过第一开口21与第一阳极103连接，阴极105通过第二开口22与第一连接导线108连接。应理解，第一开口21使得第一阳极103的部分露出，第二开口22使得第一连接导线108的部分露出。换言之，第一像素界定层20覆盖第一阳极103的部分和第一连接导线108的部分，从而限定出第一开口21和第二开口22。第一功能层104设置在第一开口21中，阴极105与第一连接导线108的露出部分(即第二开口22底部的第一连接导线108)接触。
在一些实施例中，第一像素界定层20在基板101上的正投影覆盖第一驱动晶体管112和第二驱动晶体管122在基板101上的正投影。换言之，第一驱动晶体管112和第二驱动晶体管122在基板101上的正投影在第一像素界定层20在基板101上的正投影之内，从而使得第一发光器件发出的光不会经过第一驱动晶体管112和第二驱动晶体管122，以提高出光效率。应理解，虽然图1示出的第一驱动晶体管112和第二驱动晶体管122位于阴极走线132的两侧，但这并非是限制性的。在某些实施例中，第一驱动晶体管112和第二驱动晶体管122可以位于阴极走线132的同侧，例如，第一驱动晶体管112和第二驱动晶体管122均位于阴极走线132的左侧或右侧。在某些实施例中，第一驱动晶体管112和第二驱动晶体管122可以在沿着垂直纸面的方向上依次排列在第一像素界定层20下方。
在一些实现方式中，参见图1，像素单元中的第二发光器件还包括位于阴极105上的第二像素界定层30。第二像素界定层30具有第三开口31，第二功能层106通过第三开口31与阴极105连接。应理解，第三开口31可以使得阴极105的部分露出，第二功能层106设置在第三开口31中，且与阴极105的露出部分接触。
下面介绍第二阳极107通过第二连接导线109与第二驱动晶体管122的漏极1223连接的具体实现方式。
参见图1，在一些实现方式中，第一像素界定层20可以具有第四开口23，第二 像素界定层30可以具有第五开口32，第二阳极107通过第四开口23和第五开口32与第二连接导线109连接。换言之，第一像素界定层20和第二像素界定层30可以使得第二连接导线109的部分露出，也即，第一像素界定层20和第二像素界定层30覆盖第二连接导线109的一部分。第二阳极107与第二连接导线109的露出部分接触。应理解，这里，第二连接导线109的露出部分也即第二连接导线109未被第一像素界定层20和第二像素界定层30覆盖的部分。例如，第一像素界定层20可以具有第四开口23，第二像素界定层30可以具有与第四开口23连通的第五开口32。第四开口23和第五开口32使得第二连接导线109的一部分露出。
图2是根据本公开一个实施例的像素单元的制造方法的流程示意图。图3A-图3H示出了根据本公开一些实施例的形成像素单元的不同阶段得到的结构的截面示意图。
下面结合图2、图3A-图3H介绍根据本公开一些实施例的像素单元的形成过程。
在步骤202，在基板101的一侧形成驱动电路层102，如图3A所示。驱动电路层102包括第一驱动晶体管112和第二驱动晶体管122。
例如，可以通过如下方式形成第一驱动晶体管112和第二驱动晶体管122：首先，在基板101上利用同一工艺形成用于第一驱动晶体管112的有源层1121和用于第二驱动晶体管122的有源层1221。然后，形成覆盖有源层1121和有源层1221的栅极电介质层142。这里，栅极电介质层142位于有源层1121上的部分可以作为栅极电介质层1125，栅极电介质层142位于有源层1221上的部分可以作为栅极电介质层1225。之后，在栅极电介质层142上形成栅极1124和栅极1224。应理解，栅极1124位于栅极电介质层1125上，栅极1224位于栅极电介质层1225上。之后，形成覆盖栅极1124和栅极1224的层间绝缘层152。之后，形成贯穿层间绝缘层152和栅极电介质层142的源极1122、漏极1123、源极1222和漏极1223。这里，源极1122和漏极1123连接到有源层1121，源极1222和漏极1223连接到有源层1221。
为了区分第一驱动晶体管112和第二驱动晶体管122，有源层1121也可以称为第一有源层，有源层1221也可以称为第二有源层。类似地，栅极电介质层1125也可以称为第一栅极电介质层，栅极电介质层1225也可以称为第二栅极电介质层。第一驱动晶体管112和第二驱动晶体管122中的其他部件也可以按照这样的方式进行区分，这里不再赘述。
在一些实施例中，在形成第一驱动晶体管112和第二驱动晶体管122的过程中，还可以在栅极电介质层142上形成阴极走线132，阴极走线132与后续形成的阴极连 接。
例如，可以通过同一工艺形成第一驱动晶体管112的栅极1124、第二驱动晶体管122的栅极1224和阴极走线132。例如，在形成覆盖有源层1121和有源层1221的栅极电介质层142后，可以在栅极电介质层142上沉积金属材料层，然后对形成的金属材料层进行图案化，以形成栅极1124、栅极1224和阴极走线132。
应理解，形成的驱动电路层102还可以包括其他器件，例如开关晶体管等。
在步骤204，在驱动电路层102远离基板101的一侧形成第一发光器件和第二发光器件。
下面结合图3B-图3H介绍形成第一发光器件和第二发光器件的过程。
首先，如图3B所示，在驱动电路层102远离基板101的一侧形成具有第一过孔11的平坦化层10。然后，在平坦化层10远离基板101的一侧形成导电材料层。之后，对导电材料层进行图案化以形成第一阳极11。
第一阳极103通过第一过孔11与第一驱动晶体管112的漏极1123连接。第一阳极103的材料例如可以包括氧化铟锡等金属氧化物。
在一些实施例中，参见图3B，平坦化层10还具有第二过孔12和第三过孔13。在驱动电路层102远离基板101的一侧形成第一阳极103的过程中，还可以在驱动电路层102远离基板101的一侧形成第一连接导线108和第二连接导线109。这里，后续形成的阴极可以通过第一连接导线108和第二过孔12与阴极走线132连接，后续形成的第二阳极可以通过第二连接导线109和第三过孔13与第二驱动晶体管122的漏极1223连接。
例如，可以先在驱动电路层102远离基板101的一侧形成平坦化层10；然后，形成连接到漏极1123的第一过孔11、连接到阴极走线132的第二过孔12和连接到漏极1223的第三过孔13；之后，形成位于第一过孔11中的第一连接件、位于第二过孔12中的第二连接件、位于第三过孔13的第三连接件、第一阳极103、第一连接导线108和第二连接导线109。
在一些实施例中，可以在形成第一过孔11、第二过孔12和第三过孔13后，形成填充第一过孔11、第二过孔12和第三过孔13、且覆盖平坦化层10的导电材料层；然后，对导电材料层进行图案化，以形成第一阳极103、第一连接导线108、第二连接导线109。这种情况下，第一过孔11中形成的第一连接件与第一阳极103一体设置，第二过孔12中形成的第二连接件和第二连接导线108一体设置，第三过孔13中形成 的第三连接件与第二连接导线109一体设置。
在另一些实施例中，也可以先通过单独的工艺在第一过孔11、第二过孔12和第三过孔13中填充导电材料，以形成第一连接件、第二连接件和第三连接件，在形成第一连接件、第二连接件和第三连接件后，在平坦化层10上沉积导电材料，然后对导电材料进行图案化以形成第一阳极103、第一连接导线108和第二连接导线109。这种情况下，第一连接件与第一阳极103并非一体设置，第二连接件和第二连接导线108并非一体设置，第三连接件与第二连接导线109并非一体设置。
之后，如图3C所示，形成第一像素界定层20。第一像素界定层20具有第一开口21和第二开口22，第一开口21使得第一阳极103的部分露出，第二开口22使得第一连接导线108的部分露出。
然后，如图3D所示，在第一开口21中形成第一功能层104。例如，可以通过喷墨打印工艺形成第一功能层104。
之后，如图3E所示，在第一功能层104远离第一阳极103的一侧形成阴极105。这里，阴极105与第一连接导线108的露出部分接触。在一些实施例中，阴极105的厚度例如可以为150埃至300埃，例如200埃、250埃等。在这样的厚度范围内的阴极105一方面可以阻挡后续的曝光工艺(例如，形成第二像素界定层30时采用的曝光工艺)中的光线透过阴极105，从而避免光线对阴极105下方的第一功能层104造成损伤。另外，在这样的厚度范围内的阴极105使得后续的刻蚀工艺(例如，去除形成第二像素界定层30时采用的光致抗蚀剂的湿法刻蚀工艺)不容易刻穿阴极105，避免对阴极105下方的第一功能层104造成损伤。
例如，在形成第一功能层104后，可以通过物理气相沉积等工艺沉积阴极材料层；然后，利用湿法刻蚀工艺或激光诱导刻蚀工艺等对阴极材料层进行刻蚀，以形成阴极105。
接下来，如图3F所示，形成第二像素界定层30。第二像素界定层30具有第三开口31，第三开口31使得阴极105的部分露出。
之后，如图3G所示，在第三开口31中形成第二功能层106。例如，可以通过喷墨打印工艺形成第二功能层106。
之后，如图3H所示，在第二功能层106远离阴极105的一侧形成第二阳极107。
在一些实施例中，第二阳极107的材料可以包括金属氧化物，例如氧化铟锡等。在另一些实施例中，第二阳极107的材料可以包括导电聚合物。例如，可以通过喷墨 打印工艺形成导电聚合物作为第二阳极107。通常情况下，形成金属氧化物的温度大于400℃，而通过喷墨打印工艺形成第二阳极107可以避免高温工艺对第二功能层106造成损伤，不会影响第二功能层106的发光效率和像素单元的寿命。另外，在均通过喷墨打印工艺形成第二功能层106和第二阳极107的情况下，工艺实现更为便利。
在一些实施例中，参见图3E，所形成的第一像素界定层20还可以具有第四开口23，第四开口23使得第二连接导线109的部分露出。另外，参见图3F，所形成的第二像素界定层还可以具有第五开口32，第五开口32与第四开口23连通。第五开口32与第四开口23使得第二连接导线109的部分露出，第二阳极107与第二连接导线109的露出部分接触。这种情况下，在形成第一像素界定层20和第二像素界定层30时，可以分别形成使得第二连接导线109的部分露出的开口。
在另一些实施例中，所形成的第一像素界定层20也可以不具有第四开口23，即，第一像素界定层20可以完全覆盖第二连接导线109。这种情况下，可以在形成第二像素界定层30后，再形成贯穿第二像素界定层30和第一像素界定层20、且连接到第二连接导线109的开口。
在一些实施例中，在形成第二阳极105后，还可以形成覆盖第二阳极105的封装层108，从而形成图1所示的像素单元。例如，可以通过等离子体化学气相沉积等工艺形成封装层108。封装层108可以阻挡水汽或氧气进入第一功能层104和第二功能层106，以避免对第一功能层104和第二功能层106中的发光层造成损坏。应理解，封装层108还可以覆盖驱动电路层102的一部分。
以上介绍了根据本公开一些实施例的像素单元的形成过程。按照这样的方式，通过一次制程工艺即可形成包括多个像素单元的双面显示的显示面板，无需分别单独形成两个显示面板，再将两个显示面板贴合在一起。另外，也无需形成两个阵列基板，显示面板的厚度更小。
本公开实施例还提供了一种双面OLED显示装置。双面OLED显示装置可以包括多个上述任意一个实施例的像素单元。在一些实施例中，双面OLED显示装置例如可以是显示面板、移动终端、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸、虚拟现实系统等任何具有显示功能的产品或部件。
在一些实施例中，双面OLED显示装置还包括覆盖多个像素单元的封装层110。多个像素单元例如可以包括红色像素单元(R)、绿色像素单元(G)和蓝色像素单元(B)。这里，像素单元也可以称为子像素。
在双面OLED显示装置为显示面板的情况下，显示面板中的驱动电路层102可以包括用于每个像素单元的第一驱动晶体管112和第二驱动晶体管122，因此，无需针对两个单面显示的显示面板分别设置两个阵列基板，减小了显示面板的厚度。
另外，由于每个像素单元中的第一发光器件和第二发光器件分别由第一驱动晶体管112和第二驱动晶体管122来驱动，因此对显示面板的画面的控制更为灵活。例如，可以控制显示面板的两面显示不同的画面。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (16)

  1. 一种像素单元，包括：
    基板；
    驱动电路层，设置在所述基板的一侧，所述驱动电路层包括第一驱动晶体管和第二驱动晶体管；
    第一发光器件，包括：
    第一阳极，设置在所述驱动电路层远离所述基板的一侧，并且与所述第一驱动晶体管的漏极连接；
    第一功能层，设置在所述第一阳极远离所述驱动电路层的一侧；和
    阴极，设置在所述第一功能层远离所述第一阳极的一侧；和
    第二发光器件，包括：
    所述阴极；
    第二功能层，设置在所述阴极远离所述第一功能层的一侧；和
    第二阳极，设置在所述第二功能层远离所述阴极的一侧，并且与所述第二驱动晶体管的漏极连接。
  2. 根据权利要求1所述的像素单元，其中，所述阴极为反射式阴极。
  3. 根据权利要求2所述的像素单元，其中，所述第一驱动晶体管和所述第二驱动晶体管间隔开地设置在所述基板上。
  4. 根据权利要求2所述的像素单元，其中，所述驱动电路层还包括与所述阴极连接的阴极走线；其中：
    所述第一发光器件在所述基板上的正投影位于所述第一驱动晶体管在所述基板上的正投影与所述第二驱动晶体管在所述基板上的正投影之间，并且，所述阴极走线在所述基板上的正投影位于所述第一发光器件在所述基板上的正投影与所述第二驱动晶体管在所述基板上的正投影之间；
    或者
    所述第一驱动晶体管和所述第二驱动晶体管在所述基板上的正投影位于所述第 一发光器件的第一侧，所述阴极走线在所述基板上的正投影位于所述第一发光器件在所述基板上的正投影的第二侧，所述第二侧与所述第一侧相对设置。
  5. 根据权利要求4所述的像素单元，还包括：
    平坦化层，设置在所述驱动电路层与所述第一发光器件之间；
    第一连接导线和第二连接导线，其中，所述第一连接导线、所述第二连接导线和所述第一阳极间隔开地设置在所述平坦化层上；
    其中，所述第一阳极通过贯穿所述平坦化层的第一过孔与所述第一驱动晶体管的漏极连接，所述阴极通过所述第一连接导线和贯穿所述平坦化层的第二过孔与所述阴极走线连接，所述第二阳极通过所述第二连接导线和贯穿所述平坦化层的第三过孔与所述第二驱动晶体管的漏极连接。
  6. 根据权利要求5所述的像素单元，其中，所述第一发光器件还包括位于所述第一阳极、所述第一连接导线和所述第二连接导线上的第一像素界定层，所述第一像素界定层具有第一开口和第二开口，所述第一功能层通过所述第一开口与所述第一阳极连接，所述阴极通过所述第二开口与所述第一连接导线连接。
  7. 根据权利要求6所述的像素单元，其中，所述第一像素界定层在所述基板上的正投影覆盖所述第一驱动晶体管和所述第二驱动晶体管在所述基板上的正投影。
  8. 根据权利要求6或7所述的像素单元，其中，所述第二发光器件还包括位于所述阴极上的第二像素界定层，所述第二像素界定层具有第三开口，所述第二功能层通过所述第三开口与所述阴极连接。
  9. 根据权利要求8所述的像素单元，其中，所述第一像素界定层还具有第四开口，所述第二像素界定层还具有第五开口，所述第二阳极通过所述第四开口和所述第五开口与所述第二连接导线连接。
  10. 根据权利要求1所述的像素单元，其中，所述阴极的材料选自下列中的一种或多种：铝、银。
  11. 一种双面OLED显示装置，包括：如权利要求1-10任意一项所述的像素单元。
  12. 一种像素单元的制造方法，包括：
    在基板的一侧形成驱动电路层，所述驱动电路层包括第一驱动晶体管和第二驱动晶体管；
    在所述驱动电路层远离所述基板的一侧形成第一发光器件和第二发光器件，所述第一发光器件包括与所述第一驱动晶体管的漏极连接的第一阳极、在所述第一阳极远离所述驱动电路层一侧的第一功能层、以及在所述第一功能层远离所述第一阳极一侧的阴极，所述第二发光器件包括所述阴极、在所述阴极远离所述第一功能层的一侧的第二功能层、以及在所述第二功能层远离所述阴极的一侧且与所述第二驱动晶体管的漏极连接的第二阳极。
  13. 根据权利要求12所述的方法，其中，在基板的一侧形成驱动电路层包括：
    在所述基板的一侧利用同一工艺形成用于所述第一驱动晶体管的第一有源层和用于所述第二驱动晶体管的第二有源层；
    形成覆盖所述第一有源层和所述第二有源层的栅极电介质层；
    利用同一工艺在所述栅极电介质层上形成第一栅极和第二栅极；
    形成覆盖所述第一栅极和所述第二栅极的层间绝缘层；
    利用同一工艺形成贯穿所述层间绝缘层和所述栅极电介质层的第一源极、第一漏极、第二源极和第二漏极，其中，所述第一源极和所述第一漏极连接到所述第一有源层，所述第二源极和所述第二漏极连接到所述第二有源层。
  14. 根据权利要求13所述的方法，其中，所述驱动电路层还包括在所述栅极电介质层上与所述阴极连接的阴极走线，所述层间绝缘层还覆盖所述阴极走线，其中，所述阴极走线、所述第一栅极和所述第二栅极是利用同一工艺形成的。
  15. 根据权利要求14所述的方法，其中，在所述驱动电路层远离所述基板的一侧形成第一发光器件和第二发光器件包括：
    在所述驱动电路层远离所述基板的一侧形成具有第一过孔、第二过孔和第三过孔 的平坦化层；
    在所述平坦化层远离所述基板的一侧形成导电材料层；
    对所述导电材料层进行图案化，以形成第一连接导线、第二连接导线以及所述第一阳极，其中，所述第一阳极通过所述第一过孔与所述第一驱动晶体管的漏极连接，所述第一连接导线通过所述第二过孔与所述阴极走线连接，所述第二连接导线通过所述第三过孔与所述第二驱动晶体管的漏极连接；
    形成第一像素界定层，所述第一像素界定层具有第一开口和第二开口，所述第一开口使得所述第一阳极的部分露出，所述第二开口使得所述第一连接导线的部分露出；
    在所述第一开口中形成所述第一功能层；
    在所述第一功能层远离所述第一阳极的一侧形成所述阴极，所述阴极与所述第一连接导线的露出部分接触；
    形成第二像素界定层，所述第二像素界定层具有第三开口，所述第三开口使得所述阴极的部分露出；
    在所述第三开口中形成所述第二功能层；
    在所述第二功能层远离所述阴极的一侧形成所述第二阳极。
  16. 根据权利要求15所述的方法，其中：
    所述第一像素界定层还具有第四开口，所述第四开口使得所述第二连接导线的部分露出；
    所述第二像素界定层还具有第五开口，所述第五开口与所述第四开口连通，其中，所述第二阳极与所述第二连接导线的露出部分接触。
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