WO2023221110A1 - 纳米线、薄膜晶体管制备方法、薄膜晶体管及半导体器件 - Google Patents

纳米线、薄膜晶体管制备方法、薄膜晶体管及半导体器件 Download PDF

Info

Publication number
WO2023221110A1
WO2023221110A1 PCT/CN2022/094188 CN2022094188W WO2023221110A1 WO 2023221110 A1 WO2023221110 A1 WO 2023221110A1 CN 2022094188 W CN2022094188 W CN 2022094188W WO 2023221110 A1 WO2023221110 A1 WO 2023221110A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode
substrate
sacrificial layer
thin film
Prior art date
Application number
PCT/CN2022/094188
Other languages
English (en)
French (fr)
Inventor
吴昊
李柳青
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/094188 priority Critical patent/WO2023221110A1/zh
Priority to CN202280001313.1A priority patent/CN117461144A/zh
Publication of WO2023221110A1 publication Critical patent/WO2023221110A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present disclosure belongs to the field of semiconductor technology, and specifically relates to a nanowire, a thin film transistor preparation method, a thin film transistor and a semiconductor device.
  • Silicon nanowires are one-dimensional nanostructures with significant quantum effects, large specific surface areas and other characteristics, which enable field-effect transistor (MOS) devices based on silicon nanowires to have good gate control capabilities and current characteristics.
  • Planar Solid-Liquid-Solid (IP-SLS) growth technology is a metal-catalyzed growth technology for nanowires.
  • the silicon-based nanowires formed through this technology have single-crystal-like characteristics, while the growth temperature is lower than 400°C and are compatible with
  • the display panel production line has high compatibility and can be used as a potential application technology for future production line upgrades.
  • the present disclosure aims to provide a nanowire, a thin film transistor preparation method, a thin film transistor and a semiconductor device.
  • a first aspect of the present disclosure provides a method for preparing nanowires, which includes:
  • a precipitation layer is prepared on the surface of the sacrificial layer facing away from the substrate and in the guide trench, and the precipitation layer covers the induction particles;
  • the sacrificial layer is removed.
  • the induction particles include indium particles
  • Preparing induced particles in the guide groove includes:
  • the patterned catalytic layer is reduced using a plasma-enhanced chemical vapor deposition process to obtain the induced particles.
  • the material of the catalytic layer is indium tin oxide, and the material of the precipitation layer includes amorphous silicon;
  • Processing the precipitation layer to cause predetermined elements to precipitate along the guide grooves under the induction of the induction particles to form nanowires includes:
  • the precipitation layer is annealed so that the silicon in the precipitation layer is induced by the induction particles to precipitate along the guide trench to obtain silicon nanowires.
  • the material of the sacrificial layer includes one of positive photoresist and negative photoresist.
  • the method further includes:
  • the sacrificial layer is processed by ion implantation to form a porous structure at least on the surface of the sacrificial layer on the side facing away from the substrate.
  • the thickness of the porous structure accounts for one thousandth to one percent of the total thickness of the sacrificial layer.
  • the ions injected into the sacrificial layer include at least one of phosphorus ions and boron ions;
  • the accelerating voltage of the ion implantation is 10-70keV, and the implantation dose is 1 ⁇ 1013-5 ⁇ 1014ions/cm2.
  • the process includes:
  • removing the sacrificial layer includes:
  • the modified sacrificial layer is removed through a stripping process.
  • the method before removing the sacrificial layer, the method further includes:
  • the precipitated layer is removed using an etching process.
  • embodiments of the disclosure provide a method for preparing a thin film transistor.
  • the thin film transistor includes an active layer, and the active layer includes nanowires.
  • the method for preparing the nanowires includes all the methods provided by the embodiments of the disclosure. method described.
  • the method further includes:
  • a transition layer and an electrode layer are sequentially prepared on the surface of the insulating layer and the nanowire facing away from the substrate; the material of the transition layer includes N+ type amorphous silicon;
  • the transition layer and the electrode layer are patterned, and the first and second electrodes of the transistor are obtained on the electrode layer and the first and second transition electrodes are obtained on the transition layer.
  • a mask is used to pattern the transition layer and the electrode layer, a transition electrode is obtained on the transition layer, and a first electrode and a second electrode are obtained on the electrode layer.
  • the method further includes:
  • a passivation layer is deposited, covering the exposed surfaces of the insulating layer, the nanowire, the first electrode and the second electrode.
  • the passivation layer after depositing the passivation layer, it also includes:
  • a third electrode of the transistor is prepared on the passivation layer facing away from the substrate surface.
  • the method before preparing the insulating layer on the first surface of the substrate, the method further includes:
  • a third electrode of the transistor is prepared on the first surface of the substrate.
  • the substrate includes one of a glass substrate and a silicon substrate.
  • a thin film transistor which includes:
  • the substrate including a first surface
  • An insulating layer, the insulating layer is disposed on the first surface of the substrate;
  • Nanowires are arranged on the surface of the insulating layer facing away from the substrate;
  • the electrode layer is stacked on the surface of the insulating layer facing away from the substrate, and the first electrode provided on the electrode layer is electrically connected to the source region of the nanowire, and is provided on the electrode layer
  • the second electrode is electrically connected to the drain region of the nanowire.
  • At least one of phosphorus ions and boron ions is provided in the insulating layer located below the nanowire.
  • the maximum depth of doped ions in the insulating layer is 1000-3000 angstroms.
  • a first transition electrode is provided between the first electrode and the source region of the nanowire, and a second transition electrode is provided between the second electrode and the drain region of the nanowire.
  • the material of the first transition electrode and the second transition electrode is N+ type amorphous silicon.
  • a third electrode is further included, and the third electrode is disposed between the substrate and the insulating layer.
  • a passivation layer is also included, and the passivation layer covers the exposed surface of the insulating layer, the electrode layer and the nanowire.
  • It also includes a passivation layer and a third electrode, the passivation layer covering the insulating layer and the exposed surface of the nanowire;
  • the third electrode is disposed on a surface of the passivation layer facing away from the substrate.
  • an embodiment of the present disclosure provides a semiconductor device, which includes the thin film transistor provided by an embodiment of the present disclosure.
  • Figure 1 is a schematic diagram of nanowire growth
  • Figure 2 is a flow chart of a nanowire preparation method provided by an embodiment of the present disclosure
  • Figure 3 is a cross-sectional view of the sacrificial layer when phosphorus ions are implanted into the sacrificial layer through an accelerating voltage of 20keV and the implantation dose is 3 ⁇ 10 14 ions/cm 2 according to an embodiment of the present disclosure;
  • Figure 4 is a flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure
  • Figure 5 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of another thin film transistor provided by an embodiment of the present disclosure.
  • step S701 is implemented in an embodiment of the present disclosure
  • Figure 8 is a schematic interface diagram of a thin film transistor after step S701 is implemented in an embodiment of the present disclosure
  • Figure 9 is a schematic structural perspective view of a thin film transistor after step S702 is implemented in an embodiment of the present disclosure
  • Figure 10 is a schematic interface diagram of a thin film transistor after step S702 is implemented in an embodiment of the present disclosure
  • Figure 11 is a schematic structural perspective view of a thin film transistor after step S703 is implemented in an embodiment of the present disclosure
  • Figure 12 is a schematic interface diagram of a thin film transistor after step S703 is implemented in an embodiment of the present disclosure
  • Figure 13 is a schematic structural perspective view of a thin film transistor after step S704 is implemented in an embodiment of the present disclosure
  • Figure 14 is a schematic interface diagram of a thin film transistor after step S704 is implemented in an embodiment of the present disclosure
  • Figure 15 is a schematic structural perspective view of a thin film transistor after step S705 is implemented in an embodiment of the present disclosure
  • Figure 16 is a schematic interface diagram of a thin film transistor after step S705 is implemented in an embodiment of the present disclosure
  • Figure 17 is a schematic structural perspective view of a thin film transistor after step S706 is implemented in an embodiment of the present disclosure
  • Figure 18 is a schematic interface diagram of a thin film transistor after step S706 is implemented in an embodiment of the present disclosure
  • Figure 19 is a schematic structural perspective view of a thin film transistor after step S707 is implemented in an embodiment of the present disclosure
  • Figure 20 is a schematic interface diagram of a thin film transistor after step S707 is implemented in an embodiment of the present disclosure
  • Figure 21 is a schematic structural perspective view of a thin film transistor after step S708 is implemented in an embodiment of the present disclosure
  • Figure 22 is a schematic interface diagram of a thin film transistor after step S708 is implemented in an embodiment of the present disclosure
  • Figure 23 is a schematic structural perspective view of a thin film transistor after step S709 is implemented in an embodiment of the present disclosure
  • FIG. 24 is a schematic interface diagram of the thin film transistor after step S709 is implemented in an embodiment of the present disclosure.
  • Figure 1 is a schematic diagram of nanowire growth. As shown in Figure 1, the principle of nanowire growth includes the following steps:
  • step S11 the insulating layer 2 is prepared on the surface of the substrate 1, and the catalytic layer is prepared on the surface of the insulating layer 2.
  • the metal particles are processed in situ to form nanoparticles 81, as shown in Figure 1(a).
  • step S12 the precursor a-Si is deposited on the surface of the substrate 1, and then the substrate is heated to form alloy droplets, such as indium alloy droplets 82, as shown in Figure 1(b).
  • step S13 when the silicon concentration in the alloy droplets is supersaturated, crystal nuclei 83 are precipitated, as shown in Figure 1(c).
  • Step S14 driven by Gibbs free energy, the alloy droplets pull the crystal nuclei to grow, forming nanowires 84.
  • the nanowires are driven by Gibbs free energy to grow laterally along the bottom sidewall of the guide trench.
  • the nanowires located at the top of the trench grow disorderly due to lack of guidance. These disorderly grown nanowires
  • the line is uneven. Due to process limitations, these disorderly grown nanowires cannot be removed, affecting the overlap between the source-drain (S/D) electrode layer and the nanowires.
  • Embodiments of the present disclosure provide a method for preparing nanowires, which can remove disorderly grown nanowires outside the nanowire area and improve the yield of nanowires; and remove guide trenches in the process of preparing nanowires to improve electrodes.
  • the overlapping properties with nanowires improve the mobility of nanowires.
  • FIG. 2 is a flow chart of a nanowire preparation method according to an embodiment of the present disclosure. As shown in Figure 2, the nanowire preparation method includes:
  • Step S201 prepare an insulating layer on the first surface of the substrate.
  • the substrate can be used to carry electronic devices such as transistors.
  • the substrate includes but is not limited to a glass substrate and a silicon substrate, and the present disclosure does not limit the material of the substrate.
  • the substrate includes a first surface and a second surface arranged oppositely, and the first surface is used to carry various components of the electronic device.
  • the second surface may also be used to carry electronic devices.
  • the embodiments of the present disclosure are described by taking the first surface as an example.
  • the material of the insulating layer can be silicides such as silicon nitride and silicon oxide, or organic materials such as polyimide and acrylic.
  • the embodiment of the present disclosure does not limit the thickness of the insulating layer.
  • the thickness of the insulating layer is 4000 angstroms.
  • Step S202 Prepare a sacrificial layer on the surface of the insulating layer facing away from the substrate, and pattern the sacrificial layer to form a guide trench.
  • the sacrificial layer can be prepared using a coating process or other suitable processes.
  • the material of the sacrificial layer includes one of positive photoresist and negative photoresist. Photoresist has low cost and simple process, which can reduce the production cost of the sacrificial layer.
  • a positive photoresist is prepared on the surface of the insulating layer facing away from the substrate through a coating process, and then the sacrificial layer is patterned through exposure, development and etching processes to form guide trenches.
  • the sacrificial layer when etching the sacrificial layer, only the sacrificial layer is etched, and the insulating layer does not need to be etched, so that the bottom of the guide trench is the insulating layer and there is no sacrificial layer material. Except for the guide trench, other positions on the surface of the insulating layer facing away from the substrate are covered by the sacrificial layer.
  • the embodiment of the present disclosure does not limit the thickness of the sacrificial layer.
  • the thickness of the sacrificial layer is 1.5 microns.
  • Step S203 prepare induction particles in the guide groove.
  • the inducer particles include indium particles or other suitable elemental particles. Among them, the induced particles are conducive to the precipitation of nanowire materials to improve the generation efficiency of nanowires.
  • nanowires in the embodiments of the disclosure refer to the active layer nanowires.
  • the nanowires in the embodiments of the disclosure replace the active layer nanowires.
  • step S203 preparing induction particles in the guide groove, includes:
  • Step S31 deposit a catalytic layer on the surface of the sacrificial layer facing away from the substrate and in the guide trench, and pattern the catalytic layer.
  • a strip-shaped catalytic layer is obtained, and the length of the strip-shaped catalytic layer spans the width of the guide groove to facilitate the formation of induced particles in the guide groove.
  • the catalytic layer is deposited through a physical vapor deposition process, and the material of the catalytic layer is indium tin oxide.
  • the thickness of the catalytic layer is not limited in the embodiments of the present disclosure.
  • the thickness of the catalytic layer may be 100-500 angstroms.
  • the catalytic layer can be patterned through coating, exposure, development, and etching processes to obtain a strip-shaped catalytic layer.
  • the embodiments of the present disclosure do not limit the width and length of the strip-shaped catalytic layer.
  • Step S32 Use a plasma-enhanced chemical vapor deposition process to reduce the patterned catalytic layer to obtain induced particles.
  • indium tin oxide is reduced by hydrogen plasma (H plasma) of a plasma enhanced chemical vapor deposition process to obtain indium induced particles.
  • H plasma hydrogen plasma
  • Step S204 prepare a precipitation layer on the surface of the sacrificial layer facing away from the substrate and in the guide groove, and the precipitation layer covers the induction particles.
  • the precipitation layer is for forming nanowires, and the material of the precipitation layer includes nanowire materials.
  • the material of the precipitation layer includes amorphous silicon (a-Si).
  • the embodiment of the present disclosure does not limit the thickness of the precipitation layer.
  • the thickness of the precipitation layer is 300 angstroms.
  • Step S205 The precipitation layer is processed so that the preset elements in the precipitation layer are induced by the induction particles to precipitate along the guide groove to form nanowires.
  • the silicon element in the amorphous silicon layer is precipitated along the guide trench under the induction of induction particles through an annealing process to generate nanowires.
  • step S205 the precipitation layer is processed so that the preset elements in the precipitation layer are induced by the induction particles to precipitate along the guide groove to form nanowires, including:
  • the precipitated layer is annealed so that the silicon in the precipitated layer is induced by the inducing particles to precipitate along the guide trench to obtain silicon nanowires.
  • the annealing temperature can be selected from 350°C to 400°C, and the annealing time can be from 30 to 60 minutes.
  • Step S206 remove the sacrificial layer.
  • the sacrificial layer is removed through a lift-off process.
  • the disorderly grown nanowires attached to the surface of the sacrificial layer are also removed. That is, when the guide trench is removed, the disordered nanowires generated on the surface of the sacrificial layer are also removed. Only nanowires are retained on the surface of the layer, thereby improving the yield of nanowires, and can eliminate the influence of step differences in the guide trench, improve the overlap between nanowires and electrodes, reduce the contact barrier of metal-semiconductor contacts, and enhance tunneling at the interface.
  • the penetration effect increases the mobility of silicon nanowires.
  • step S203 before preparing induction particles in the guide trench, also includes processing the sacrificial layer through ion implantation to form a porous structure on the surface of the sacrificial layer on the side facing away from the substrate, that is, performing the sacrificial layer on Carbonization treatment.
  • the surface of the sacrificial layer facing away from the substrate is treated by ion implantation, and a porous structure is formed on the surface of the sacrificial layer facing away from the substrate.
  • This structure is similar to the molecular structure of diamond or graphite, has high stability, and can avoid subsequent processes.
  • the chemical solvent can diffuse into the interior of the sacrificial layer through the surface layer of the porous structure, causing the interior of the sacrificial layer to dissolve, thereby causing the surface layer of the sacrificial layer to fall off, facilitating the removal of the sacrificial layer.
  • a porous structure is formed on the surface of the sacrificial layer on the side facing away from the substrate through ion implantation, and the implanted ions include at least one of phosphorus ions (P + ) and boron ions (B + ).
  • the thickness of the porous structure accounts for one thousandth to one percent of the total thickness of the sacrificial layer.
  • the accelerating voltage of ion implantation is 10-70keV
  • the implantation dose is 1 ⁇ 10 13 -5 ⁇ 10 14 ions/cm 2 .
  • Figure 3 is a cross-sectional view of the sacrificial layer when phosphorus ions are implanted into the sacrificial layer using an accelerating voltage of 20keV and the implantation dose is 3 ⁇ 10 14 ions/cm 2 according to an embodiment of the present disclosure. It can be seen from the figure that the structure of the sacrificial layer has changed after carbonization, and the color changes from the surface to the inside of the sacrificial layer to light yellow-yellow-dark brown. In Figure 3, the thickness of the carbonized layer is 124nm, and the thickness of the uncarbonized sacrificial layer is 1.25 ⁇ m.
  • the photoresist when the material of the sacrificial layer is photoresist, after modification through ion implantation, the photoresist is carbonized, and the carbonized photoresist has a diamond-like/graphite molecular structure, which is stable in structure and can reduce Subsequent processes contaminate the chamber due to volatilization of the sacrificial layer.
  • step S206 before removing the sacrificial layer, also includes: modifying the sacrificial layer to facilitate removal of the sacrificial layer.
  • the sacrificial layer is modified through an ashing process and oxygen plasma (O 2 plasma) to facilitate subsequent removal of the sacrificial layer, and the modification process will not damage the nanowires.
  • O 2 plasma oxygen plasma
  • step S206 before removing the sacrificial layer, further includes: using an etching solution to remove impurities in the induced particles, and using an etching process to remove excess amorphous silicon.
  • the impurities include ion-implanted boron ions and phosphorus ions.
  • an etching solution is used to remove impurities in the induced particles, for example, an indium tin oxide etching solution is used to remove impurities such as boron ions and/or phosphorus ions in the indium ball.
  • a plasma etching process is used to remove the modified excess sacrificial layer.
  • amorphous silicon is removed using a hydrogen plasma etching process.
  • the impurities and excess amorphous silicon in the induced particles are removed through an etching process, and then the sacrificial layer is modified, which helps to improve the yield of the nanowires.
  • the nanowire preparation method provided by the embodiment of the present disclosure forms a guide trench in the sacrificial layer, prepares induction particles in the guide trench, prepares a precipitate layer on the surface of the sacrificial layer facing away from the substrate and in the guide trench, and makes the precipitate layer Cover the induction particles and process the precipitation layer so that the preset elements in the precipitation layer are induced by the induction particles to precipitate along the guide trench to form nanowires. Finally, the sacrificial layer is removed. When removing the guide trench, the sacrificial layer can be removed. The disordered nanowires on the surface are removed, so that only the nanowires remain on the surface of the insulating layer, which improves the yield of the nanowires. It is also helpful to improve the overlap between the nanowires and the electrodes, reduce the contact barrier of the metal-semiconductor contact, and enhance the interface. The tunneling effect increases the mobility of silicon nanowires.
  • FIG. 4 is a flow chart of a thin film transistor manufacturing method provided by an embodiment of the present disclosure.
  • the thin film transistor preparation method includes:
  • Step S401 prepare an insulating layer on the first surface of the substrate.
  • the substrate includes but is not limited to a glass substrate and a silicon substrate, and the present disclosure does not limit the material of the substrate.
  • the substrate includes a first surface and a second surface arranged oppositely.
  • the first surface is used to carry various components of the electronic device, and the second surface is arranged opposite to the first surface.
  • the second surface may also be used to carry electronic devices.
  • the embodiments of the present disclosure are described using the first surface.
  • the material of the insulating layer can be silicides such as silicon nitride and silicon oxide, or organic materials such as polyimide and acrylic.
  • the thickness of the insulating layer can be preset according to the situation, for example, the thickness of the insulating layer is 4000 angstroms.
  • Step S402 Prepare a sacrificial layer on the surface of the insulating layer facing away from the substrate, and pattern the sacrificial layer to form a guide trench.
  • the sacrificial layer can be prepared using a coating process or other suitable processes.
  • the material of the sacrificial layer includes one of positive photoresist and negative photoresist. Photoresist has low cost and simple process, which can reduce the production cost of the sacrificial layer.
  • a positive photoresist is prepared on the surface of the insulating layer facing away from (away from) the substrate through a coating process, and then the sacrificial layer is patterned through exposure, development and etching processes to form guide trenches.
  • the sacrificial layer when etching the sacrificial layer, only the sacrificial layer is etched, and the insulating layer does not need to be etched, so that the bottom of the guide trench is the insulating layer and there is no sacrificial layer material. Except for the guide trench, other positions on the surface of the insulating layer facing away from the substrate are covered by the sacrificial layer.
  • the embodiment of the present disclosure does not limit the thickness of the sacrificial layer.
  • the thickness of the sacrificial layer is 1.5 microns.
  • Step S403 prepare induction particles in the guide groove.
  • the inducer particles include indium particles or other suitable elemental particles. Among them, the induced particles are conducive to the precipitation of nanowire materials to improve the generation efficiency of nanowires.
  • step S403, preparing induced particles in the guide trench includes: depositing a catalytic layer on the surface of the sacrificial layer facing away from the substrate and in the guide trench, patterning the catalyzed layer, and then using plasma The volume-enhanced chemical vapor deposition process is used to reduce the patterned catalytic layer to obtain induced particles.
  • a strip-shaped catalytic layer is obtained, and the length of the strip-shaped catalytic layer spans the width of the guide groove to facilitate the formation of induced particles in the guide groove.
  • the catalytic layer is deposited through a physical vapor deposition process, and the material of the catalytic layer is indium tin oxide.
  • the thickness of the catalytic layer is not limited in the embodiments of the present disclosure.
  • the thickness of the catalytic layer may be 100-500 angstroms.
  • the catalytic layer can be patterned through coating, exposure, development, and etching processes to obtain a strip-shaped catalytic layer.
  • the embodiments of the present disclosure do not limit the width and length of the strip-shaped catalytic layer.
  • indium tin oxide is reduced by hydrogen plasma (H plasma) of a plasma enhanced chemical vapor deposition process to obtain indium induced particles.
  • H plasma hydrogen plasma
  • Step S404 Prepare a precipitation layer on the surface of the sacrificial layer facing away from the substrate and in the guide groove, and the precipitation layer covers the induction particles.
  • the precipitation layer is for forming nanowires, and the material of the precipitation layer includes nanowire materials.
  • the material of the precipitation layer includes amorphous silicon (a-Si).
  • the embodiment of the present disclosure does not limit the thickness of the precipitation layer.
  • the thickness of the precipitation layer is 300 angstroms.
  • step S405 the precipitation layer is processed so that the preset elements in the precipitation layer are induced by the induction particles to precipitate along the guide groove to form nanowires.
  • the silicon element in the amorphous silicon layer is precipitated along the guide trench under the induction of induction particles through an annealing process to generate nanowires.
  • the annealing temperature can be selected from 350°C to 400°C, and the annealing time can be from 30 to 60 minutes.
  • step S405 the precipitation layer is processed so that the preset elements in the precipitation layer are induced by the induction particles to precipitate along the guide groove to form nanowires, including:
  • the precipitated layer is annealed so that the silicon in the precipitated layer is induced by the inducing particles to precipitate along the guide trench to obtain silicon nanowires.
  • Step S406 Remove the modified sacrificial layer.
  • step S406 the modified sacrificial layer is removed through a stripping process.
  • step S403 before preparing the induction particles in the guide trench, also includes processing the sacrificial layer through ion implantation to form a porous structure on the surface of the sacrificial layer on the side facing away from the substrate, that is, performing the sacrificial layer treatment. Carbonization treatment.
  • the surface of the sacrificial layer facing away from the substrate is treated by ion implantation, and a porous structure is formed on the surface of the sacrificial layer facing away from the substrate.
  • This structure is similar to the molecular structure of diamond or graphite, has high stability, and can avoid subsequent processes.
  • the chemical solvent can diffuse into the interior of the sacrificial layer through the surface layer of the porous structure, causing the interior of the sacrificial layer to dissolve, thereby causing the surface layer of the sacrificial layer to fall off, facilitating the removal of the sacrificial layer.
  • a porous structure is formed on the surface of the sacrificial layer on the side facing away from the substrate through ion implantation, and the implanted ions include at least one of phosphorus ions (P + ) and boron ions (B + ).
  • the thickness of the porous structure accounts for one thousandth to one percent of the total thickness of the sacrificial layer.
  • the accelerating voltage of ion implantation is 10-70keV
  • the implantation dose is 1 ⁇ 10 13 -5 ⁇ 10 14 ions/cm 2 .
  • the photoresist when the material of the sacrificial layer is photoresist, after modification through ion implantation, the photoresist is carbonized, and the carbonized photoresist has a diamond-like/graphite molecular structure, which is stable in structure and can reduce Subsequent processes contaminate the chamber due to volatilization of the sacrificial layer.
  • step S406, before removing the modified sacrificial layer further includes: modifying the sacrificial layer.
  • the sacrificial layer is modified through an ashing process and oxygen plasma (O 2 plasma) to facilitate subsequent removal of the sacrificial layer, and the modification process does not damage the nanowires.
  • O 2 plasma oxygen plasma
  • step S406, before removing the modified sacrificial layer also includes: using an etching solution to remove impurities in the induced particles, and using an etching process to remove excess amorphous silicon.
  • the impurities include ion-implanted boron ions and phosphorus ions.
  • an etching solution is used to remove impurities in the induced particles, for example, an indium tin oxide etching solution is used to remove impurities such as boron ions and/or phosphorus ions in the indium sphere.
  • a plasma etching process is used to remove the modified excess sacrificial layer.
  • amorphous silicon is removed using a hydrogen plasma etching process.
  • the impurities and excess amorphous silicon in the induced particles are removed through an etching process, and then the sacrificial layer is modified, which helps to improve the yield of the nanowires.
  • step S406 after removing the modified sacrificial layer, also includes:
  • Step S407 sequentially prepare a transition layer and an electrode layer on the surface of the insulating layer and the nanowire facing away from the substrate; pattern the transition layer and the electrode layer to obtain the first electrode and the second electrode of the transistor on the electrode layer, and obtain the first electrode and the second electrode of the transistor on the transition layer. with a first transition electrode and a second transition electrode.
  • the material of the transition layer includes N + amorphous silicon, or other materials with good conductive properties.
  • the N + atom can be a group V element, such as arsenic and phosphorus.
  • the embodiments of the present disclosure do not limit the thickness of the transition layer, as long as the thickness of the transition layer can cover the nanowires, for example, the thickness of the transition layer can be 500 angstroms.
  • the material of the electrode layer can be conductive metal materials, such as molybdenum, copper and aluminum.
  • the thickness of the conductive layer is not limited in the embodiments of the present disclosure. For example, the thickness of the conductive layer is 2200 angstroms.
  • a mask when patterning the transition layer and the conductive layer, a mask can be used, that is, a mask is used to pattern the transition layer and the electrode layer, and the transition electrode is obtained on the transition layer, and the transition electrode is obtained on the electrode layer.
  • first electrode and second electrode are two electrodes of the transistor, for example, the first electrode is the drain electrode and the second electrode is the source electrode.
  • the embodiment of the present disclosure uses a mask to pattern the transition layer and the electrode layer, which can simplify the preparation process of the transistor and reduce the cost of the transistor.
  • the transition layer can improve the abnormal overlap problem between the conductive layer and the nanowire, reduce the contact barrier of the metal-semiconductor contact, enhance the tunneling effect at the interface, reduce the maximum resistance of the transistor, and even avoid The problem of low on-state current of thin film transistors caused by the large resistance of the transistors.
  • step S407, after patterning the transition layer and the electrode layer also includes:
  • Step S408 Deposit a passivation layer, which covers the exposed surfaces of the insulating layer, the nanowire, the first electrode and the second electrode.
  • the materials of the passivation layer include but are not limited to silicon oxide (SiOx) and silicon nitride (SiNx).
  • the thickness of the passivation layer only needs to cover the conductive layer.
  • the embodiment of the present disclosure does not limit the thickness of the passivation layer.
  • the thickness of the passivation layer may be 800 angstroms or 400 angstroms.
  • step S408, after depositing the passivation layer further includes:
  • Step S409 pattern the passivation layer to expose at least part of the surface of the first electrode and the second electrode facing away from the substrate.
  • the passivation layer can be patterned through coating, exposure, and development processes to expose at least part of the surface of the first electrode and the second electrode facing away from the substrate.
  • Step S410 prepare a third electrode of the transistor on the surface of the passivation layer facing away from the substrate.
  • the material of the third electrode may be conductive metal, such as molybdenum or copper.
  • the embodiment of the present disclosure does not limit the thickness of the third electrode.
  • the thickness of the third electrode is 500 angstroms or 2200 angstroms.
  • the third electrode may serve as a gate electrode of the thin film transistor, and the first electrode, the second electrode, and the third electrode constitute the transistor. Since the gate is on top of the passivation layer, the thin film transistor may be called a top-gate structure transistor.
  • the thin film transistor can also adopt a bottom gate structure.
  • the thin film transistor with a bottom gate structure before preparing an insulating layer on the first surface of the substrate in step S401, it also includes: preparing an insulating layer on the first surface of the substrate. The third electrode of the transistor.
  • the third electrode serves as the gate of the transistor.
  • the material of the third electrode can be conductive metal such as molybdenum and copper.
  • the thickness of the third electrode can be 500 angstroms or 2200 angstroms. The embodiment of the present disclosure does not limit the thickness of the third electrode.
  • the transistor preparation method provided by the embodiment of the present disclosure forms a guide trench in the sacrificial layer, prepares induction particles in the guide trench, prepares a precipitate layer on the surface of the sacrificial layer facing away from the substrate and in the guide trench, and covers the precipitate layer Induced particles are used to process the precipitation layer so that the preset elements in the precipitation layer are induced by the induction particles to precipitate along the guide trench to form nanowires. Finally, the sacrificial layer is removed. When removing the guide trench, the surface of the sacrificial layer can be The disordered nanowires are removed, so that only the nanowires remain on the surface of the insulating layer, which improves the yield of the nanowires. It is also helpful to improve the overlap between the nanowires and the electrodes, reduce the contact barrier of the metal-semiconductor contact, and enhance the interface. The tunneling effect improves the mobility of silicon nanowires.
  • Embodiments of the present disclosure also provide a thin film transistor that improves the overlapping performance of electrodes and nanowires and increases the mobility of nanowires.
  • FIG. 5 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present disclosure. As shown in Figure 5, thin film transistors include:
  • Substrate 1 the substrate includes a first surface.
  • the substrate includes but is not limited to a glass substrate and a silicon substrate, and the present disclosure does not limit the material of the substrate.
  • the substrate includes a first surface and a second surface arranged oppositely, and both the first surface and the second surface can be used to carry various components of the electronic device.
  • Insulating layer 2 is provided on the first surface of the substrate 1 .
  • the material of the insulating layer 2 may be a silicide such as silicon nitride or silicon oxide, or an organic material such as polyimide or acrylic.
  • the embodiment of the present disclosure does not limit the thickness of the insulating layer.
  • Nanowire 3 is disposed on the surface of the insulating layer 2 facing away from the substrate 1 .
  • the material of the nanowire 3 can be silicon, or other materials can be used. After the nanowires 3 are prepared, the sacrificial layer required to prepare the nanowires and the randomly grown nanowires on the surface of the sacrificial layer facing away from the substrate 1 are removed. Therefore, only nanometers remain on the surface of the insulating layer 2 facing away from the substrate 1. Wire.
  • Electrode layer the electrode layer is stacked on the surface of the insulating layer 2 facing away from the substrate 1, and the first electrode 41 provided on the electrode layer is electrically connected to the source region of the nanowire 3, and the second electrode 42 provided on the electrode layer is electrically connected to the nanowire.
  • the drain region is electrically connected.
  • the material of the electrode layer may be a conductive metal material.
  • the material of the electrode layer 4 includes at least one of molybdenum, copper, and aluminum.
  • the first electrode 41 and the second electrode 42 can respectively serve as the source electrode and the drain electrode of the thin film transistor.
  • a first transition electrode 51 is provided between the first electrode 41 and the source region of the nanowire 3
  • a second transition electrode is provided between the second electrode 42 and the drain region of the nanowire 3 52.
  • the first transition electrode 51 can improve the abnormal overlap problem between the first electrode 41 and the nanowire 3, reduce the contact barrier of the metal-semiconductor contact, enhance the tunneling effect at the interface, and reduce the large resistance phenomenon of the transistor.
  • the electrode layer 4 is stacked on the surface of the insulating layer 2 facing away from the substrate 1 , that is, there is no sacrificial layer when preparing the nanowire 3 and disorderly growth between the electrode layer 4 and the insulating layer 2 Nanowires, this can eliminate the influence of step differences caused by the guide trench, improve the overlap between the electrode layer 4 and the nanowires 3, and increase the mobility of the nanowires. Moreover, there are no randomly grown nanowires between the electrode layer 4 and the insulating layer 2, which can improve the yield of the nanowires.
  • the insulating layer includes a first portion whose orthographic projection on the substrate coincides with the orthographic projection of the nanowire on the substrate, and the first portion is doped with at least one of phosphorus ions and boron ions. .
  • phosphorus ions and boron ions are ions implanted during carbonization of the sacrificial layer.
  • the maximum depth of doped ions in the insulating layer is between 1000 Angstroms and 3000 Angstroms.
  • ions can pass through the guide trench and enter the bottom of the guide trench. Since the bottom of the guide trench is an insulating layer, ions are injected into the sacrificial layer and are also injected into the first part of the insulating layer.
  • the material of the first transition electrode 51 and the second transition electrode 52 is N + type amorphous silicon (N + a-Si).
  • the thin film transistor further includes a passivation layer 6 covering the exposed surfaces of the insulating layer 2 , the electrode layer and the nanowire 3 .
  • the passivation layer 6 can protect the insulating layer 2, the electrode layer and the nanowire 3, and improve the service life of the thin film transistor.
  • the thin film transistor further includes a third electrode 43 disposed between the substrate 1 and the insulating layer 2 .
  • the third electrode 43 may be a gate electrode of a thin film transistor, and the first electrode 41 , the second electrode 42 and the third electrode 43 constitute a thin film transistor. Since the third electrode 43 is disposed at the bottom of the thin film transistor, that is, the gate electrode is disposed at the bottom of the thin film transistor, therefore, the thin film transistor may be called a transistor with a bottom gate structure.
  • the thin film transistor further includes a passivation layer 6 and a third electrode 43 .
  • the passivation layer 6 covers the exposed surface of the insulating layer 2 and the nanowire 3 ; the third electrode 43 is disposed on the passivation layer 6 .
  • the surface of the chemical layer 6 facing away from the substrate 1 . Since the third electrode 43 is disposed on the top of the thin film transistor, that is, the gate electrode is on the top of the passivation layer, the thin film transistor may be called a top-gate structure transistor.
  • the electrode layer 4 is stacked on the surface of the insulating layer 2 facing away from the substrate 1 , that is, there is no sacrificial layer when preparing the nanowire 3 and disorderly growth between the electrode layer 4 and the insulating layer 2 Nanowires, this can eliminate the influence of the step difference caused by the guide trench, improve the overlap between the electrode layer 4 and the nanowire 3, reduce the contact barrier between the electrode layer and the nanowire contact, enhance the tunneling effect at the interface, and improve the nanowire migration rate. Moreover, there are no randomly grown nanowires between the electrode layer 4 and the insulating layer 2, which can improve the yield of the nanowires.
  • FIGS. 7 to 24 are the cross-sectional views along the line A-A in the corresponding perspective views.
  • Step S701 prepare a metal layer, such as a molybdenum metal layer, on the first surface of the substrate 1.
  • the thickness of the molybdenum metal layer may be 500 Angstroms, and then pattern the metal layer to obtain the third electrode 43, that is, the gate electrode, as shown in Figure 7 and Figure 8.
  • Step S702 deposit the insulating layer 2 so that the insulating layer covers the third electrode 43 and the exposed surface of the substrate 1; then, coat the sacrificial layer 7 on the surface of the insulating layer 2, and then undergo exposure and development to obtain a patterned sacrificial layer. layer to form guide trenches 71, as shown in Figures 9 and 10.
  • the material of the insulating layer 2 can be SiOx, the thickness of the insulating layer 2 can be 4000 Angstroms, and the sacrificial layer can be made of photoresist, and the thickness of the photoresist can be. It should be noted that when patterning the sacrificial layer, there is no need to etch the insulating layer 2 .
  • the sacrificial layer 7 is provided with a plurality of guide grooves 71, the plurality of guide grooves 71 are spaced apart.
  • Step S703 ion implantation is performed on the sacrificial layer to carbonize the sacrificial layer to obtain the carbonized sacrificial layer 7', which can reduce the contamination of the chamber by the sacrificial layer in subsequent processes, as shown in Figures 11 and 12.
  • step S703 phosphorus ions are implanted into the sacrificial layer using an accelerating voltage of 70 kev, and the implanted dose is 5 ⁇ 10 14 ions/cm 2 .
  • Step S704 prepare a precipitation layer 8 on the surface of the sacrificial layer 7 facing away from the substrate 1 and in the guide trench 71, and pattern the precipitation layer 8, as shown in Figures 13 and 14.
  • step S704 indium tin oxide is deposited on the surface of the sacrificial layer 7 away from the substrate 1 and in the guide trench 71 through a deposition process to obtain a catalytic layer. Then, the catalytic layer is processed through coating, exposure, development and etching processes. 72 for graphics.
  • the patterned catalytic layer may have a strip structure, and the length of the strip catalytic layer is such that it covers a plurality of guide grooves 71 arranged at intervals to ensure that induced particles can be obtained in each guide groove 71 .
  • step S705 the patterned catalytic layer is reduced using a plasma enhanced chemical vapor deposition process to obtain induction particles 81, and then a precipitate layer 8 is deposited, and the precipitate layer covers the induction particles, as shown in Figures 15 and 16.
  • the material of the catalytic layer includes indium tin oxide.
  • the plasma enhanced chemical vapor deposition process is used and hydrogen plasma is used to reduce the catalytic layer to obtain indium induced particles, and then an a-Si layer is deposited as a precipitation layer. . Since the sacrificial layer has been carbonized in step S703 so that the sacrificial layer forms a diamond-like/graphite molecular structure, the sacrificial layer will not contaminate the chamber when the catalytic layer is reduced.
  • step S706 the precipitated layer is annealed so that the silicon in the precipitated layer is induced by the inducing particles to precipitate along the guide trench to obtain silicon nanowires, as shown in Figures 17 and 18.
  • the annealing temperature can be selected from 350°C to 400°C, and the annealing time is from 30 to 60 minutes.
  • Step S707 use an indium tin oxide etching solution to remove impurities in the indium induced particles, such as phosphorus and/or boron; remove the precipitation layer 8 through an etching process, that is, through a plasma enhanced chemical vapor deposition process and using hydrogen plasma Excess a-Si is removed, and then the carbonized sacrificial layer is modified through an ashing process and oxygen plasma, and then the sacrificial layer is removed, as shown in Figures 19 and 20.
  • an indium tin oxide etching solution to remove impurities in the indium induced particles, such as phosphorus and/or boron
  • remove the precipitation layer 8 through an etching process, that is, through a plasma enhanced chemical vapor deposition process and using hydrogen plasma Excess a-Si is removed, and then the carbonized sacrificial layer is modified through an ashing process and oxygen plasma, and then the sacrificial layer is removed, as shown in Figures 19 and 20.
  • Step S708 sequentially prepare a transition layer and an electrode layer on the surface of the insulating layer 2 and the nanowire 3 facing away from the substrate 1; pattern the transition layer and the electrode layer to obtain the first electrode 41 and the second electrode 42 of the transistor on the electrode layer. , the transition layer is obtained with the first transition electrode 51 and the second transition electrode 52, as shown in Figures 21 and 22.
  • N + type amorphous silicon (N + a-Si) is sequentially prepared on the surface of the insulating layer 2 and the nanowire 3 facing away from the substrate 1 to obtain a transition layer, and then metal molybdenum is deposited to obtain a metal layer, and then the After internal coating, exposure, and development, the mask is etched to obtain the first transition electrode 51 and the second transition electrode 52 on the transition layer, and the first electrode 41 and the second electrode on the electrode layer. 42.
  • step S709 a passivation layer is deposited, and the passivation layer covers the exposed surfaces of the insulating layer, the nanowire, the first electrode and the second electrode, as shown in Figures 21 and 22.
  • step S709 silicon oxide is deposited as a passivation layer 9 through a physical vapor deposition process.
  • the passivation layer 9 covers the insulating layer 2, the nanowire 3, the first electrode 41, the second electrode 42, the first transition electrode 51 and the second
  • the exposed surface of transition electrode 52 is shown in FIGS. 23 and 24 .
  • Embodiments of the present disclosure also provide a semiconductor device, which includes the thin film transistor provided by embodiments of the present disclosure. Since the sacrificial layer is removed, the influence of the step difference in the guide trench can be eliminated, the overlapping situation between the nanowires and the electrodes can be improved, and the metal-semiconductor The contact barrier of the contact enhances the tunneling effect at the interface and increases the mobility of silicon nanowires, thereby improving the overall performance of the semiconductor device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

本公开提供一种纳米线、薄膜晶体管制备方法、薄膜晶体管及半导体器件，属于半导体技术领域，可解决纳米线问题。本公开纳米线制备方法，其包括：在衬底的第一表面制备绝缘层；在绝缘层背离衬底的表面制备牺牲层，并对牺牲层进行图案化，形成引导沟槽；在引导沟槽内制备诱导颗粒；在牺牲层背离衬底的表面和引导沟槽内制备析出层，析出层覆盖诱导颗粒；对析出层进行处理，使析出层内的预设元素在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线；将牺牲层去除。

Description

纳米线、薄膜晶体管制备方法、薄膜晶体管及半导体器件 技术领域
本公开属于半导体技术领域，具体涉及一种纳米线、薄膜晶体管制备方法、薄膜晶体管及半导体器件。
背景技术
硅纳米线是一维纳米结构，具有显著的量子效应、超大的比表面积等特性，使得基于硅纳米线的场效应晶体管(MOS)器件具有良好的栅控能力和电流特性。平面固-液-固(IP-SLS)生长技术是一种金属催化生长纳米线的技术，通过该技术形成的硅基纳米线具有类单晶的特质，同时生长温度低于400℃，并与显示面板产线具有较高兼容性，可作为未来产线升级的潜在应用技术。
发明内容
本公开旨在提供一种纳米线、薄膜晶体管制备方法、薄膜晶体管及半导体器件。
本公开第一方面提供一种纳米线制备方法，其包括：
在衬底的第一表面制备绝缘层；
在所述绝缘层背离所述衬底的表面制备牺牲层，并对所述牺牲层进行图案化，形成引导沟槽；
在所述引导沟槽内制备诱导颗粒；
在所述牺牲层背离衬底的表面和所述引导沟槽内制备析出层，所述析出层覆盖所述诱导颗粒；
对所述析出层进行处理，使所述析出层内的预设元素在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成纳米线；
将所述牺牲层去除。
其中，所述诱导颗粒包括铟颗粒；
在所述引导沟槽内制备诱导颗粒，包括：
在所述牺牲层背离衬底的表面和所述引导沟槽内沉积催化层，并对所催化层进行图形化处理；
利用等离子体增强的化学气相沉积工艺对图形化后的所述催化层进行还原处理，获得所述诱导颗粒。
其中，所述催化层的材料为铟锡氧化物，所述析出层的材料包括非晶硅；
所述对所述析出层进行处理，使预设元素在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成纳米线，包括：
对所述析出层进行退火处理，使所述析出层内的硅在所述诱导颗粒的诱导下沿所述引导沟槽析出，获得硅纳米线。
其中，所述牺牲层的材料包括正性光刻胶和负性光刻胶之一。
其中，所述在所述引导沟槽内制备诱导颗粒之前，还包括：
通过离子注入方式对所述牺牲层进行处理，至少在所述牺牲层背离所述衬底一侧的表层形成多孔结构。
其中，所述多孔结构的厚度占所述牺牲层的总厚度的千分之一至百分之一。
其中，注入所述牺牲层的离子包括磷离子和硼离子中的至少一种；
所述离子注入的加速电压为10-70keV，注入剂量为1×1013-5×1014ions/cm2。
其中，所述将所述牺牲层去除之前，包括：
通过灰化工艺并利用氧等离子体对所述牺牲层进行改性处理；
其中，所述将所述牺牲层去除，包括：
通过剥离工艺将改性后的所述牺牲层去除。
其中，所述将所述牺牲层去除之前，还包括：
使用刻蚀液去除所述诱导颗粒中的杂质；
利用刻蚀工艺将所述析出层去除。
第二方面，本公开实施例提供一种薄膜晶体管的制备方法，薄膜晶体管包括有源层，所述有源层包括纳米线，其中，所述纳米线的制备方法包括本公开实施例提供的所述的方法。
其中，所述将所述牺牲层去除之后，还包括：
在所述绝缘层和所述纳米线背离所述衬底的表面依次制备过渡层和电极层；所述过渡层的材料包括N+型非晶硅；
对所述过渡层和电极层进行图形化，在所述电极层获得晶体管的第一电极和第二电极，在所述过渡层获得与第一过渡电极和第二过渡电极。
其中，采用一个掩膜对所述过渡层和电极层进行图形化，在所述过渡层获得过渡电极，在所述电极层获得第一电极和第二电极。
其中，所述对所述过渡层和电极层进行图形化之后，还包括：
沉积钝化层，所述钝化层覆盖所述绝缘层、所述纳米线、所述第一电极和所述第二电极裸露的表面。
其中，所述沉积钝化层之后，还包括：
对所述钝化层进行图形化，至少将所述第一电极和所述第二电极背离所述衬底的部分表面露出；
在所述钝化层背离所述衬底表面制备所述晶体管的第三电极。
其中，所述在衬底的第一表面制备绝缘层之前，还包括：
在所述衬底的第一表面制备晶体管的第三电极。
其中，所述衬底包括玻璃衬底和硅衬底中的一种。
第四方面，本公开实施例提供一种薄膜晶体管，其包括：
衬底，所述衬底包括第一表面；
绝缘层，所述绝缘层设置于所述衬底的第一表面；
纳米线，所述纳米线设置于所述绝缘层背离所述衬底的表面；
电极层，所述电极层叠置于所述绝缘层背离所述衬底的表面，且设置于所述电极层的第一电极与所述纳米线的源极区域电连接，设置于所述电极层的第二电极与所述纳米线的漏极区域电连接。
其中，位于所述纳米线下方的所述绝缘层内设置有磷离子和硼离子中的至少一种。
其中，掺杂的离子在所述绝缘层中的最大深度为1000埃-3000埃。
其中，在所述第一电极与所述纳米线的源极区域之间设置有第一过渡电极，在所述第二电极与所述纳米线的漏极区域之间设置有第二过渡电极。
其中，所述第一过渡电极和所述第二过渡电极的材料为N+型非晶硅。
其中，还包括第三电极，所述第三电极设置于所述衬底和所述绝缘层之间。
其中，还包括钝化层，所述钝化层覆盖所述绝缘层、所述电极层和所述纳米线的裸露表面。
其中，还包括钝化层和第三电极，所述钝化层覆盖所述绝缘层和所述纳米线的裸露表面；
所述第三电极设置于所述钝化层背离所述衬底的表面。
第四方面，本公开实施例提供一种半导体器件，其包括本公开实施例提供的所述的薄膜晶体管。
附图说明
图1为纳米线生长的原理图；
图2为本公开实施例提供的一种纳米线制备方法的流程图；
图3为本公开实施例通过20keV的加速电压将磷离子注入牺牲层，而且，注入剂量为3×10 14ions/cm 2的情况下，牺牲层的截面图；
图4为本公开实施例提供的一种薄膜晶体管的制备方法的流程图；
图5为本公开实施例提供的一种薄膜晶体管的结构示意图；
图6为本公开实施例提供的另一种薄膜晶体管的结构示意图；
图7为本公开实施例中实施步骤S701后的薄膜晶体管的结构立体示意图；
图8为本公开实施例中实施步骤S701后的薄膜晶体管的界面示意图；
图9为本公开实施例中实施步骤S702后的薄膜晶体管的结构立体示意图；
图10为本公开实施例中实施步骤S702后的薄膜晶体管的界面示意图；
图11为本公开实施例中实施步骤S703后的薄膜晶体管的结构立体示意图；
图12为本公开实施例中实施步骤S703后的薄膜晶体管的界面示意图；
图13为本公开实施例中实施步骤S704后的薄膜晶体管的结构立体示意图；
图14为本公开实施例中实施步骤S704后的薄膜晶体管的界面示意图；
图15为本公开实施例中实施步骤S705后的薄膜晶体管的结构立体示意图；
图16为本公开实施例中实施步骤S705后的薄膜晶体管的界面示意图；
图17为本公开实施例中实施步骤S706后的薄膜晶体管的结构立体示意图；
图18为本公开实施例中实施步骤S706后的薄膜晶体管的界面示意图；
图19为本公开实施例中实施步骤S707后的薄膜晶体管的结构立体示意图；
图20为本公开实施例中实施步骤S707后的薄膜晶体管的界面示意图；
图21为本公开实施例中实施步骤S708后的薄膜晶体管的结构立体示意图；
图22为本公开实施例中实施步骤S708后的薄膜晶体管的界面示意图；
图23为本公开实施例中实施步骤S709后的薄膜晶体管的结构立体示意图；
图24为本公开实施例中实施步骤S709后的薄膜晶体管的界面示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为纳米线生长的原理图。如图1所示，纳米线生长的原理包括以下步骤：
步骤S11，在衬底1表面制备的绝缘层2，在绝缘层2的表面制备催化层，金属颗粒经过原位处理形成纳米颗粒81，如图1(a)所示。
步骤S12，在衬底1的表面沉积前驱体a-Si，然后加热衬底，形成合金液滴，如铟合金液滴82，如图1(b)所示。
步骤S13，合金液滴中的硅浓度过饱和时析出晶核83，如图1(c)所示。
步骤S14，在吉布斯自由能驱使下，合金液滴牵引晶核生长，形成纳米 线84。
在纳米线生长过程中，纳米线受吉布斯自由能的驱动沿着引导沟槽的槽底侧壁横向生长，位于槽顶的纳米线由于无引导而无序生长，这些无序生长的纳米线高低不平。由于工艺的限制，这些无序生长的纳米线无法去除，影响源漏(S/D)电极层与纳米线的搭接。
本公开实施例提供一种纳米线制备方法，该方法可以去除纳米线区域之外的无序生长的纳米线，提高纳米线的良率；以及将制备纳米线过程中引导沟槽去除，改善电极与纳米线的搭接性能，提高纳米线的迁移率。
图2为本公开实施例提供一种纳米线制备方法的流程图。如图2所示，纳米线制备方法包括：
步骤S201，在衬底的第一表面制备绝缘层。
其中，衬底可以用于承载晶体管等电子器件。衬底包括但不限于玻璃衬底和硅衬底，本公开对衬底的材料不作限定。
在本公开实施例中，衬底包括相对设置的第一表面和第二表面，第一表面用于承载电子器件的各组成部分。在一些实施例中，第二表面也可以用于承载电子器件。为便于描述，本公开实施例以第一表面为例进行说明。
其中，绝缘层的材料可以为氮化硅、氧化硅等硅化物，或者为聚酰亚胺、亚克力等有机材料。本公开实施例对绝缘层的厚度不作限定，如绝缘层的厚度为4000埃。
步骤S202，在绝缘层背离衬底的表面制备牺牲层，并对牺牲层进行图案化，形成引导沟槽。
其中，牺牲层可以采用涂覆工艺或其它适合的工艺制备。在一些实施例中，牺牲层的材料包括正性光刻胶和负性光刻胶之一。光刻胶成本低，工艺简单，可以降低牺牲层的制作成本。
示例地，通过涂覆工艺在绝缘层背离衬底的表面制备正性光刻胶，然后通过曝光、显影和刻蚀工艺对牺牲层进行图案化，形成引导沟槽。
需要说明的是，在刻蚀牺牲层时，仅刻蚀牺牲层，无需刻蚀绝缘层，以使引导沟槽的底部为绝缘层，无牺牲层的材料。在绝缘层背离衬底的表面除引导沟槽之外，其它位置被牺牲层覆盖。
本公开实施例对牺牲层的厚度不作限定，例如，牺牲层的厚度为1.5微米。
步骤S203，在引导沟槽内制备诱导颗粒。
在一些实施例中，诱导颗粒包括铟颗粒或其它适合的元素颗粒。其中，诱导颗粒有利于纳米线材料的析出，以提高纳米线的生成效率。
需要说明的是，本公开实施例中的纳米线是指有源层纳米线，为方便表述，本公开实施例以纳米线代替有源层纳米线。
在一些实施例中，步骤S203，在引导沟槽内制备诱导颗粒，包括：
步骤S31，在牺牲层背离衬底的表面和引导沟槽内沉积催化层，并对所催化层进行图形化处理。
对所催化层进行图形化处理后，获得条形催化层，且条形催化层的长度跨越引导沟槽的宽度，以便于在引导沟槽内形成诱导颗粒。
在一些实施例中，通过物理气相沉积工艺沉积催化层，催化层的材料为铟锡氧化物，本公开实施例对催化层的厚度不作限定，例如，催化层的厚度可以为100-500埃。
本公开实施例可以通过涂覆、曝光、显影、刻蚀工艺对催化层进行图形化，获得条形催化层。本公开实施例对条形催化层的宽度和长度不作限定。
步骤S32，利用等离子体增强化学气相沉积工艺对图形化后的催化层进行还原处理，获得诱导颗粒。
在本公开实施例中，通过等离子体增强化学气相沉积工艺的氢等离子(H plasma)还原铟锡氧化物，获得铟诱导颗粒。
步骤S204，在牺牲层背离衬底的表面和引导沟槽内制备析出层，析出 层覆盖诱导颗粒。
其中，析出层是为了形成纳米线，析出层的材料包括纳米线材料。例如，析出层的材料包括非晶硅(a-Si)。本公开实施例对析出层的厚度不作限定，例如，析出层的厚度为300埃。
步骤S205，对析出层进行处理，使析出层内预设元素在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线。
在一些实施例中，通过退火工艺使非晶硅层的硅元素在诱导颗粒的诱导下沿引导沟槽析出，生成纳米线。
在一些实施例中，步骤S205，对析出层进行处理，使析出层内预设元素在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线，包括：
对析出层进行退火处理，使析出层内的硅在诱导颗粒的诱导下沿引导沟槽析出，获得硅纳米线。
在一些实施例中，退火温度可以选择350℃～400℃，退火时间为30～60min。
步骤S206，将牺牲层去除。
在一些实施例中，通过剥离工艺将牺牲层去除。
在本公开实施例中，牺牲层去除后，附着在牺牲层表面的无序生长的纳米线也被去除，即去除引导沟槽时将牺牲层表面生成的无序的纳米线一同去除，在绝缘层的表面仅保留纳米线，从而提高纳米线的良率，而且可以消除引导沟槽的段差影响，改善纳米线与电极搭接情况，降低金属-半导体接触的接触势垒，增强界面处的隧穿效应，提高硅纳米线的迁移率。
在一些实施例中，步骤S203，在引导沟槽内制备诱导颗粒之前，还包括通过离子注入方式对牺牲层进行处理，在牺牲层背离衬底一侧的表层形成多孔结构，即对牺牲层进行碳化处理。
其中，通离子注入方式对牺牲层背离衬底的表面进行处理，在牺牲层背离衬底一侧的表层形成多孔结构，该结构类似金刚石或石墨的分子结构，稳 定性高，可以避免后续工艺过程中牺牲层对腔室的污染；而且，化学溶剂可以通过多孔结构的表层扩散至牺牲层的内部，使牺牲层的内部溶解，进而使牺牲层的表层脱落，方便牺牲层的去除。
在一些实施例中，通过离子注入方式在牺牲层背离衬底一侧的表层形成多孔结构，注入的离子包括磷离子(P +)和硼离子(B +)中的至少一种。在一些实施例中，多孔结构的厚度占牺牲层的总厚度的千分之一至百分之一。
在一些实施例中，离子注入的加速电压为10-70keV，注入剂量为1×10 13-5×10 14ions/cm 2。通过10-70keV的加速电压将磷离子和/或硼离子注入牺牲层，使磷离子和/或硼离子位于牺牲层表面的深度，既可以使牺牲层改性，减少牺牲层对后续工艺的影响，又便于后续牺牲层的去除，减少牺牲层材料的残留。
图3为本公开实施例通过20keV的加速电压将磷离子注入牺牲层，而且，注入剂量为3×10 14ions/cm 2的情况下，牺牲层的截面图。从图中可以看出，碳化处理后的牺牲层的结构发生了变化，从表面向牺牲层内部的颜色变化为浅黄-黄-深棕。在图3中，碳化层的厚度为124nm，未被碳化的牺牲层的厚度为1.25μm。
在本公开实施例中，牺牲层的材料为光刻胶时，通过离子注入改性后，光刻胶被碳化，而且碳化后的光刻胶具有类金刚石/石墨分子结构，结构稳定，可以减少后续工艺因牺牲层挥发而污染腔室。
在一些实施例中，步骤S206，将牺牲层去除之前，还包括：对牺牲层进行改性，以便于去除牺牲层。
通过灰化(Ashing)工艺并利用氧等离子体(O 2plasma)对牺牲层进行改性处理，以便于后续对牺牲层的去除，而且该改性工艺不会损伤纳米线。
在一些实施例中，步骤S206，将牺牲层去除之前，还包括：使用刻蚀液去除诱导颗粒中的杂质，利用刻蚀工艺将多余的非晶硅去除。
其中，杂质包括离子注入的硼离子和磷离子。在一些实施例中，使用刻 蚀液去除诱导颗粒中的杂质，例如通过铟锡氧化物刻蚀液去除铟球内的硼离子和/或磷离子等杂质。
在一些实施例中，利用等离子刻蚀工艺将改性后的多余的牺牲层去除。例如，利用氢等离子体刻蚀工艺将非晶硅去除。
在本公开实施例中，在去除牺牲层之前，通过刻蚀工艺将诱导颗粒中的杂质和多余的非晶硅去除，然后对牺牲层进行改性处理，有助于提高纳米线的良率。
本公开实施例提供的纳米线制备方法，在牺牲层形成引导沟槽，并在引导沟槽内制备诱导颗粒，在牺牲层背离衬底的表面和引导沟槽内制备析出层，并使析出层覆盖诱导颗粒，对析出层进行处理，使析出层内的预设元素在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线，最后将牺牲层去除，在去除引导沟槽时可以将牺牲层表面无序的纳米线去除，从而在绝缘层的表面仅保留纳米线，提高纳米线的良率，而且有利于改善纳米线与电极搭接情况，降低金属-半导体接触的接触势垒，增强界面处的隧穿效应，提高硅纳米线的迁移率。
本公开实施例还提供一种薄膜晶体管制备方法，图4为本公开实施例提供的一种薄膜晶体管制备方法的流程图。
如图4所示，薄膜晶体管制备方法包括：
步骤S401，在衬底的第一表面制备绝缘层。
衬底包括但不限于玻璃衬底和硅衬底，本公开对衬底的材料不作限定。
在本公开实施例中，衬底包括相对设置的第一表面和第二表面，第一表面用于承载电子器件的各组成部分，第二表面与第一表面相对设置。在一些实施例中，第二表面也可以用于承载电子器件。为便于描述，本公开实施例以第一表面进行说明。
其中，绝缘层的材料可以为氮化硅、氧化硅等硅化物，或者为聚酰亚胺、亚克力等有机材料。绝缘层的厚度可以根据情况预先设定，如绝缘层的厚度 为4000埃。
步骤S402，在绝缘层背离衬底的表面制备牺牲层，并对牺牲层进行图案化，形成引导沟槽。
其中，牺牲层可以采用涂覆工艺或其它适合的工艺制备。在一些实施例中，牺牲层的材料包括正性光刻胶和负性光刻胶之一。光刻胶成本低，工艺简单，可以降低牺牲层的制作成本。
示例地，通过涂覆工艺在绝缘层背离(远离)衬底的表面制备正性光刻胶，然后通过曝光、显影和刻蚀工艺对牺牲层进行图案化，形成引导沟槽。
需要说明的是，在刻蚀牺牲层时，仅刻蚀牺牲层，无需刻蚀绝缘层，以使引导沟槽的底部为绝缘层，无牺牲层的材料。在绝缘层背离衬底的表面除引导沟槽之外，其它位置被牺牲层覆盖。
本公开实施例对牺牲层的厚度不作限定，例如，牺牲层的厚度为1.5微米。
步骤S403，在引导沟槽内制备诱导颗粒。
在一些实施例中，诱导颗粒包括铟颗粒或其它适合的元素颗粒。其中，诱导颗粒有利于纳米线材料的析出，以提高纳米线的生成效率。
在一些实施例中，步骤S403，在引导沟槽内制备诱导颗粒，包括：在牺牲层背离衬底的表面和引导沟槽内沉积催化层，并对所催化层进行图形化处理，再利用等离子体增强化学气相沉积工艺对图形化后的催化层进行还原处理，获得诱导颗粒。
其中，对所催化层进行图形化处理后，获得条形催化层，且条形催化层的长度跨越引导沟槽的宽度，以便于在引导沟槽内形成诱导颗粒。
在一些实施例中，通过物理气相沉积工艺沉积催化层，催化层的材料为铟锡氧化物，本公开实施例对催化层的厚度不作限定，例如，催化层的厚度可以为100-500埃。
本公开实施例可以通过涂覆、曝光、显影、刻蚀工艺对催化层进行图形 化，获得条形催化层。本公开实施例对条形催化层的宽度和长度不作限定。
在本公开实施例中，通过等离子体增强化学气相沉积工艺的氢等离子(H plasma)还原铟锡氧化物，获得铟诱导颗粒。
步骤S404，在牺牲层背离衬底的表面和引导沟槽内制备析出层，析出层覆盖诱导颗粒。
其中，析出层是为了形成纳米线，析出层的材料包括纳米线材料。例如，析出层的材料包括非晶硅(a-Si)。本公开实施例对析出层的厚度不作限定，例如，析出层的厚度为300埃。
步骤S405，对析出层进行处理，使析出层内的预设元素在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线。
在一些实施例中，通过退火工艺使非晶硅层的硅元素在诱导颗粒的诱导下沿引导沟槽析出，生成纳米线。
在一些实施例中，退火温度可以选择350℃～400℃，退火时间为30～60min。
在一些实施例中，步骤S405，对析出层进行处理，使析出层内预设元素在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线，包括：
对析出层进行退火处理，使析出层内的硅在诱导颗粒的诱导下沿引导沟槽析出，获得硅纳米线。
步骤S406，将改性后的牺牲层去除。
在步骤S406中，通过剥离工艺将改性处理后的牺牲层去除。
在一些实施例中，步骤S403，在引导沟槽内制备诱导颗粒之前，还包括通过离子注入方式对牺牲层进行处理，在牺牲层背离衬底一侧的表层形成多孔结构，即对牺牲层进行碳化处理。
其中，通离子注入方式对牺牲层背离衬底的表面进行处理，在牺牲层背离衬底一侧的表层形成多孔结构，该结构类似金刚石或石墨的分子结构，稳 定性高，可以避免后续工艺过程中牺牲层对腔室的污染；而且，化学溶剂可以通过多孔结构的表层扩散至牺牲层的内部，使牺牲层的内部溶解，进而使牺牲层的表层脱落，方便牺牲层的去除。
在一些实施例中，通过离子注入方式在牺牲层背离衬底一侧的表层形成多孔结构，注入的离子包括磷离子(P +)和硼离子(B +)中的至少一种。在一些实施例中，多孔结构的厚度占牺牲层的总厚度的千分之一至百分之一。
在一些实施例中，离子注入的加速电压为10-70keV，注入剂量为1×10 13-5×10 14ions/cm 2。通过10-70keV的加速电压将磷离子和/或硼离子注入牺牲层，使磷离子和/或硼离子位于牺牲层表面的深度，既可以使牺牲层改性，减少牺牲层对后续工艺的影响，又便于后续牺牲层的去除，减少牺牲层材料的残留。
在本公开实施例中，牺牲层的材料为光刻胶时，通过离子注入改性后，光刻胶被碳化，而且碳化后的光刻胶具有类金刚石/石墨分子结构，结构稳定，可以减少后续工艺因牺牲层挥发而污染腔室。
在一些实施例中，步骤S406，将改性后的牺牲层去除之前，还包括：对牺牲层进行改性。
例如，通过灰化(Ashing)工艺并利用氧等离子体(O 2plasma)对牺牲层进行改性处理，以便于后续对牺牲层的去除，而且该改性工艺不会损伤纳米线。
在一些实施例中，步骤S406，将改性后的牺牲层去除之前，还包括：使用刻蚀液去除诱导颗粒中的杂质，利用刻蚀工艺将多余的非晶硅去除。
其中，杂质包括离子注入的硼离子和磷离子。在一些实施例中，使用刻蚀液去除诱导颗粒中的杂质，例如通过铟锡氧化物刻蚀液去除铟球内的硼离子和/或磷离子等杂质。
在一些实施例中，利用等离子刻蚀工艺将改性后的多余的牺牲层去除。例如，利用氢等离子体刻蚀工艺将非晶硅去除。
在本公开实施例中，在去除牺牲层之前，通过刻蚀工艺将诱导颗粒中的杂质和多余的非晶硅去除，然后对牺牲层进行改性处理，有助于提高纳米线的良率。
在一些实施例中，步骤S406，将改性后的牺牲层去除之后，还包括：
步骤S407，在绝缘层和纳米线背离衬底的表面依次制备过渡层和电极层；对过渡层和电极层进行图形化，在电极层获得晶体管的第一电极和第二电极，在过渡层获得与第一过渡电极和第二过渡电极。
其中，过渡层的材料包括N +非晶硅，或者采用其它导电性能良好的材料。其中N +原子可以采用V族元素，如砷、磷。本公开实施例对过渡层的厚度不作限定，过渡层的厚度只要能够覆盖纳米线，例如过渡层的厚度可以为500埃。电极层的材料可以采用导电金属材料，例如钼、铜和铝。本公开实施例对导电层的厚度不作限定，例如导电层的厚度为2200埃。
在一些实施例中，在对过渡层和导电层进行图形化时，可以采用一个掩膜，即采用一个掩膜对过渡层和电极层进行图形化，在过渡层获得过渡电极，在电极层获得第一电极和第二电极。其中，第一电极和第二电极是晶体管的两个电极，如第一电极为漏极，第二电极为源极。
本公开实施例采用一个掩膜对过渡层和电极层进行图形化，可以简化晶体管的制备工艺，降低晶体管的成本。
在本公开实施例中，过渡层可以改善导电层与纳米线的搭接异常问题，降低金属-半导体接触的接触势垒，增强界面处的隧穿效应，降低晶体管的最大阻值，甚至可以避免晶体管出现大阻值而导致的薄膜晶体管开态电流较低的问题。
在一些实施例中，步骤S407，对过渡层和电极层进行图形化之后，还包括：
步骤S408，沉积钝化层，钝化层覆盖绝缘层、纳米线、第一电极和第二电极裸露的表面。
其中，钝化层的材料包括但不限于氧化硅(SiOx)、氮化硅(SiNx)。钝化层的厚度覆盖导电层即可，本公开实施例对钝化层的厚度不作限定，例如，钝化层的厚度可以为800埃或400埃。
在一些实施例中，步骤S408，沉积钝化层之后，还包括：
步骤S409，对钝化层进行图形化，至少将第一电极和第二电极背离衬底的部分表面露出。
在一些实施例中，可以通过涂覆、曝光、显影工艺对钝化层进行图形化，至少将第一电极和第二电极背离衬底的部分表面露出。
步骤S410，在钝化层背离衬底表面制备晶体管的第三电极。
其中，第三电极的材料可以为导电金属，例如钼或铜。本公开实施例对第三电极的厚度不作限定，例如，第三电极的厚度为500埃或2200埃。
在一些实施例中，第三电极可以作为薄膜晶体管的栅极，第一电极、第二电极和第三电极构成晶体管。由于栅极在钝化层的顶部，该薄膜晶体管可以被称为顶栅结构的晶体管。
在一些实施例中，薄膜晶体管也可以采用底栅结构，对于底栅结构的薄膜晶体管，在步骤S401，在衬底的第一表面制备绝缘层之前，还包括：在衬底的第一表面制备晶体管的第三电极。
其中，第三电极作为晶体管的栅极，第三电极的材料可以为钼、铜等导电金属，第三电极的厚度可以为500埃或2200埃。本公开实施例对第三电极的厚度不作限定。
本公开实施例提供的晶体管制备方法，在牺牲层形成引导沟槽，并在引导沟槽内制备诱导颗粒，在牺牲层背离衬底的表面和引导沟槽内制备析出层，并使析出层覆盖诱导颗粒，对析出层进行处理，使析出层内的预设元素在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线，最后将牺牲层去除，在去除引导沟槽时可以将牺牲层表面无序的纳米线去除，从而在绝缘层的表面仅保留纳米线，提高纳米线的良率，而且有利于改善纳米线与电极搭接情况， 降低金属-半导体接触的接触势垒，增强界面处的隧穿效应，提高硅纳米线的迁移率。
本公开实施例还提供一种薄膜晶体管，该晶体管改善电极与纳米线的搭接性能，提高纳米线的迁移率。
图5为本公开实施例提供的一种薄膜晶体管的结构示意图。如图5所示，薄膜晶体管包括：
衬底1，衬底包括第一表面。
其中，衬底包括但不限于玻璃衬底和硅衬底，本公开对衬底的材料不作限定。衬底包括相对设置的第一表面和第二表面，第一表面和第二表面均可以用于承载电子器件的各组成部分。
绝缘层2，绝缘层2设置于衬底1的第一表面。绝缘层2的材料可以为氮化硅、氧化硅等硅化物，或者为聚酰亚胺、亚克力等有机材料。本公开实施例对绝缘层的厚度不作限定。
纳米线3，纳米线3设置于绝缘层2背离衬底1的表面。
纳米线3的材料可以为硅，也可以采用其它材料。在纳米线3制备完毕后，将制备纳米线所需的牺牲层以及在牺牲层背离衬底1的表面的杂乱生长的纳米线去除，因此，在绝缘层2背离衬底1的表面仅保留纳米线。
电极层，电极层叠置于绝缘层2背离衬底1的表面，且设置于电极层的第一电极41与纳米线3的源极区域电连接，设置于电极层的第二电极42与纳米线的漏极区域电连接。
在一些实施例中，电极层的材料可以采用导电金属材料，例如，电极层4的材料包括钼、铜、铝中的至少一种。其中，第一电极41和第二电极42可以分别作为薄膜晶体管的源极和漏极。在一些实施例中，在第一电极41与纳米线3的源极区域之间设置有第一过渡电极51，在第二电极42与纳米线3的漏极区域之间设置有第二过渡电极52。第一过渡电极51可以改善第一电极41与纳米线3的搭接异常问题，降低金属-半导体接触的接触势垒， 增强界面处的隧穿效应，减少晶体管的大阻值现象。
本公开实施例提供的薄膜晶体管，电极层4叠置于绝缘层2背离衬底1的表面，即在电极层4与绝缘层2之间没有制备纳米线3时的牺牲层以及无序生长的纳米线，这样可以消除引导沟槽引起的段差影响，使得电极层4与纳米线3搭接得到改善，提高纳米线的迁移率。而且，在电极层4与绝缘层2之间没有无序生长的纳米线，可以提高纳米线的良率。
在一些实施例中，绝缘层包括在衬底上的正投影与所述纳米线在衬底上的正投影重合的第一部分，在第一部分中掺杂有磷离子和硼离子中的至少一种。其中，磷离子和硼离子是对牺牲层进行碳化处理时注入的离子。
在一些实施例中，掺杂的离子在所述绝缘层中的最大深度为1000埃-3000埃。
在牺牲层注入离子过程中，离子可以穿过引导沟槽进入引导沟槽的底部，由于引导沟槽的底部为绝缘层，因此，离子被注入牺牲层的同时也被注入绝缘层的第一部分。
在一些实施例中，第一过渡电极51和第二过渡电极52的材料为N +型非晶硅(N +a-Si)。
在一些实施例中，薄膜晶体管还包括钝化层6，钝化层6覆盖绝缘层2、电极层和纳米线3的裸露表面。钝化层6可以对绝缘层2、电极层和纳米线3进行保护，提高薄膜晶体管使用寿命。
在一些实施例中，薄膜晶体管还包括第三电极43，第三电极43设置于衬底1和绝缘层2之间。
第三电极43可以为作为薄膜晶体管的栅极，第一电极41、第二电极42和第三电极43构成薄膜晶体管。由于第三电极43设置在薄膜晶体管的底部，即栅极设置在薄膜晶体管的底部，因此，该薄膜晶体管可以被称为底栅结构的晶体管。
在另一些实施例中，如图6所示，薄膜晶体管还包括钝化层6和第三电 极43，钝化层6覆盖绝缘层2和纳米线3的裸露表面；第三电极43设置于钝化层6背离衬底1的表面。由于第三电极43设置在薄膜晶体管的顶部，即栅极在钝化层的顶部，该薄膜晶体管可以被称为顶栅结构的晶体管。
本公开实施例提供的薄膜晶体管，电极层4叠置于绝缘层2背离衬底1的表面，即在电极层4与绝缘层2之间没有制备纳米线3时的牺牲层以及无序生长的纳米线，这样可以消除引导沟槽引起的段差影响，使得电极层4与纳米线3搭接得到改善，降低电极层-纳米线接触的接触势垒，增强界面处的隧穿效应，提高纳米线的迁移率。而且，在电极层4与绝缘层2之间没有无序生长的纳米线，可以提高纳米线的良率。
为了更好地理解本公开薄膜晶体管及制备方法，下面结合图7至图24，并以顶栅结构的薄膜晶体管为例详细介绍。需要说明的是，在图7至图24中的截面图是与之对应的立体图中A-A线的截面图。
步骤S701，在衬底1的第一表面制备金属层，如钼金属层，钼金属层的厚度可以为500埃，然后对金属层进行图形化，获得第三电极43，即栅极，如图7和图8所示。
步骤S702，沉积绝缘层2，使绝缘层覆盖第三电极43和衬底1的裸露表面；然后，在绝缘层2的表面涂覆牺牲层7，再经过曝光、显影，获得图形化后的牺牲层，形成引导沟槽71，如图9和图10所示。
在步骤S702中，绝缘层2的材料可以采用SiOx，绝缘层2的厚度可以为4000埃，牺牲层采用光刻胶，光刻胶的厚度。需要说明的是，在对牺牲层进行图形化时，无需刻蚀绝缘层2。
当牺牲层7设置有多个引导沟槽71时，多个引导沟槽71间隔设置。
步骤S703，对牺牲层进行离子注入，使牺牲层碳化，获得碳化后的牺牲层7′，这样可以减少后续工艺中牺牲层对腔室的污染，如图11和图12所示。
在步骤S703中，利用70kev的加速电压将磷离子注入牺牲层，注入的 剂量为5×10 14ions/cm 2。
步骤S704，在牺牲层7背离衬底1的表面和引导沟槽71内制备析出层8，并对析出层8进行图形化，如图13和图14所示。
在步骤S704中，通过沉积工艺在牺牲层7背离衬底1的表面以及引导沟槽71内沉积铟锡氧化物，获得催化层，然后，通过涂覆、曝光、显影和刻蚀工艺对催化层72进行图形化。图形化后的催化层可为条形结构，条形催化层的长度以覆盖间隔设置的多个引导沟槽71，以确保每个引导沟槽71内均能获得诱导颗粒。
步骤S705，利用等离子体增强化学气相沉积工艺对图形化后的催化层进行还原处理，获得诱导颗粒81，然后沉积析出层8，析出层覆盖诱导颗粒，如图15和图16所示。
在步骤S705中，催化层的材料包括铟锡氧化物，利用等离子体增强化学气相沉积工艺并采用氢等离子体对催化层进行还原处理，获得铟诱导颗粒，然后沉积a-Si层，作为析出层。由于在步骤S703已经对牺牲层进行了碳化处理，使得牺牲层形成类金刚石/石墨分子结构，因此，在对催化层进行还原处理时，不会因牺牲层而污染腔室。
步骤S706，对析出层进行退火处理，使析出层内的硅在诱导颗粒的诱导下沿引导沟槽析出，获得硅纳米线，如图17和图18所示。
在本公开实施例中，退火温度可以选择350℃～400℃，退火时间为30～60min。
步骤S707，使用铟锡氧化物刻蚀液去除铟诱导颗粒中的杂质，如磷和/或硼；通过刻蚀工艺将析出层8去除，即通过等离子体增强化学气相沉积工艺并利用氢等离子体去除多余的a-Si，再通过灰化工艺并利用氧等离子体对碳化的牺牲层进行改性处理，然后将牺牲层去除，如图19和图20所示。
步骤S708，在绝缘层2和纳米线3背离衬底1的表面依次制备过渡层 和电极层；对过渡层和电极层进行图形化，在电极层获得晶体管的第一电极41和第二电极42，在过渡层获得与第一过渡电极51和第二过渡电极52，如图21和图22所示。
在步骤S708中，在绝缘层2和纳米线3背离衬底1的表面依次制备N +型非晶硅(N +a-Si)，获得过渡层，然后沉积金属钼，获得金属层，再通内涂覆、曝光、显影后的掩膜，对过渡层和电极层进行刻蚀，在过渡层获得第一过渡电极51和第二过渡电极52，在电极层获得第一电极41和第二电极42。
步骤S709，沉积钝化层，钝化层覆盖绝缘层、纳米线、第一电极和第二电极裸露的表面，如图21和图22所示。
在步骤S709中，通过物理气相沉积工艺沉积氧化硅作为钝化层9，钝化层9覆盖绝缘层2、纳米线3、第一电极41、第二电极42、第一过渡电极51和第二过渡电极52裸露的表面，如图23和图24所示。
本公开实施例还提供一种半导体器件，其包括本公开实施例提供的薄膜晶体管，由于牺牲层被去除，可以消除引导沟槽的段差影响，改善纳米线与电极搭接情况，降低金属-半导体接触的接触势垒，增强界面处的隧穿效应，提高硅纳米线的迁移率，从而可以提高半导体器件的整体性能。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (26)

  1. 一种纳米线制备方法，其包括：
    在衬底的第一表面制备绝缘层；
    在所述绝缘层背离所述衬底的表面制备牺牲层，并对所述牺牲层进行图案化，形成引导沟槽；
    在所述引导沟槽内制备诱导颗粒；
    在所述牺牲层背离衬底的表面和所述引导沟槽内制备析出层，所述析出层覆盖所述诱导颗粒；
    对所述析出层进行处理，使所述析出层内预设元素在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成纳米线；
    将所述牺牲层去除。
  2. 根据权利要求1所述的方法，其中，所述诱导颗粒包括铟颗粒；
    在所述引导沟槽内制备诱导颗粒，包括：
    在所述牺牲层背离衬底的表面和所述引导沟槽内沉积催化层，并对所催化层进行图形化处理；
    利用等离子体增强的化学气相沉积工艺对图形化后的所述催化层进行还原处理，形成所述诱导颗粒。
  3. 根据权利要求2所述的方法，其中，所述催化层的材料为铟锡氧化物，所述析出层的材料包括非晶硅；
    所述对所述析出层进行处理，使所述析出层内预设元素在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成纳米线，包括：
    对所述析出层进行退火处理，使所述析出层内的硅在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成硅纳米线。
  4. 根据权利要求1所述的方法，其中，所述牺牲层的材料包括正性光刻胶和负性光刻胶之一。
  5. 根据权利要求4所述的方法，其中，所述在所述引导沟槽内制备诱导颗粒之前，还包括：
    通过离子注入方式对所述牺牲层进行处理，以使在所述牺牲层背离所述衬底一侧的表层形成多孔结构。
  6. 根据权利要求5所述的方法，其中，所述多孔结构的厚度占所述牺牲层的总厚度的千分之一至百分之一。
  7. 根据权利要求5所述的方法，其中，注入所述牺牲层的离子包括磷离子和硼离子中的至少一种；
    所述离子注入的加速电压为10-70keV，注入剂量为1×1013-5×1014ions/cm2。
  8. 根据权利要求4所述的方法，其中，所述将所述牺牲层去除之前，还包括：
    通过灰化工艺并利用氧等离子体对所述牺牲层进行改性处理。
  9. 根据权利要求8所述的方法，其中，所述将所述牺牲层去除，包括：
    通过剥离工艺将改性后的所述牺牲层去除。
  10. 根据权利要求1所述的方法，其中，所述将所述牺牲层去除之前，还包括：
    使用刻蚀液去除所述诱导颗粒中的杂质；
    利用刻蚀工艺将所述析出层去除。
  11. 一种薄膜晶体管的制备方法，薄膜晶体管包括有源层，所述有源层包括纳米线，其中，所述纳米线的制备方法包括权利要求1-10中任意一项所述的方法。
  12. 根据权利要求11所述的方法，其中，所述将所述牺牲层去除之后，还包括：
    在所述绝缘层和所述纳米线背离所述衬底的表面依次制备过渡层和电极层；所述过渡层的材料包括N+型非晶硅；
    对所述过渡层和电极层进行图形化，在所述电极层获得晶体管的第一电极和第二电极，在所述过渡层获得第一过渡电极和第二过渡电极。
  13. 根据权利要求12所述的方法，其中，采用一个掩膜对所述过渡层和电极层进行图形化，在所述过渡层获得第一过渡电极和第二过渡电极，在所述电极层获得第一电极和第二电极，所述第一过渡电极与所述第一电极叠置，所述第二过渡电极与所述第二电极叠置。
  14. 根据权利要求12所述的方法，其中，所述对所述过渡层和电极层进行图形化之后，还包括：
    沉积钝化层，所述钝化层覆盖所述绝缘层、所述纳米线、所述第一电极和所述第二电极裸露的表面。
  15. 根据权利要求14所述的方法，其中，所述沉积钝化层之后，还包括：
    对所述钝化层进行图形化，至少将所述第一电极和所述第二电极背离所述衬底的部分表面露出；
    在所述钝化层背离所述衬底表面制备所述晶体管的第三电极。
  16. 根据权利要求11所述的方法，其中，包括：所述在衬底的第一表面制备绝缘层之前，还包括：
    在所述衬底的第一表面制备晶体管的第三电极。
  17. 根据权利要求11所述的方法，其中，所述衬底包括玻璃衬底和硅衬底中的一种。
  18. 一种薄膜晶体管，其包括：
    衬底，所述衬底包括第一表面；
    绝缘层，所述绝缘层设置于所述衬底的第一表面；
    纳米线，所述纳米线设置于所述绝缘层背离所述衬底的表面；
    电极层，所述电极层叠置于所述绝缘层背离所述衬底的表面，且设置于所述电极层的第一电极与所述纳米线的源极区域电连接，设置于所述电 极层的第二电极与所述纳米线的漏极区域电连接。
  19. 根据权利要求18所述的薄膜晶体管，其中，所述绝缘层包括在衬底上的正投影与所述纳米线在衬底上的正投影重合的第一部分，在所述第一部分中掺杂有磷离子和硼离子中的至少一种。
  20. 根据权利要求19所述的薄膜晶体管，其中，掺杂的离子在所述绝缘层中的最大深度为1000埃-3000埃。
  21. 根据权利要求18所述的薄膜晶体管，其中，在所述第一电极与所述纳米线的源极区域之间设置有第一过渡电极，在所述第二电极与所述纳米线的漏极区域之间设置有第二过渡电极。
  22. 根据权利要求21所述的薄膜晶体管，其中，所述第一过渡电极和所述第二过渡电极的材料为N+型非晶硅。
  23. 根据权利要求18-22任意一项所述的薄膜晶体管，其中，还包括第三电极，所述第三电极设置于所述衬底和所述绝缘层之间。
  24. 根据权利要求23所述的薄膜晶体管，其中，还包括钝化层，所述钝化层覆盖所述绝缘层、所述电极层和所述纳米线的裸露表面。
  25. 根据权利要求18-22任意一项所述的薄膜晶体管，其中，还包括钝化层和第三电极，所述钝化层覆盖所述绝缘层和所述纳米线的裸露表面；
    所述第三电极设置于所述钝化层背离所述衬底的表面。
  26. 一种半导体器件，其包括权利要求18-25任意一项所述的薄膜晶体管。
PCT/CN2022/094188 2022-05-20 2022-05-20 纳米线、薄膜晶体管制备方法、薄膜晶体管及半导体器件 WO2023221110A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2022/094188 WO2023221110A1 (zh) 2022-05-20 2022-05-20 纳米线、薄膜晶体管制备方法、薄膜晶体管及半导体器件
CN202280001313.1A CN117461144A (zh) 2022-05-20 2022-05-20 纳米线、薄膜晶体管制备方法、薄膜晶体管及半导体器件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/094188 WO2023221110A1 (zh) 2022-05-20 2022-05-20 纳米线、薄膜晶体管制备方法、薄膜晶体管及半导体器件

Publications (1)

Publication Number Publication Date
WO2023221110A1 true WO2023221110A1 (zh) 2023-11-23

Family

ID=88834404

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/094188 WO2023221110A1 (zh) 2022-05-20 2022-05-20 纳米线、薄膜晶体管制备方法、薄膜晶体管及半导体器件

Country Status (2)

Country Link
CN (1) CN117461144A (zh)
WO (1) WO2023221110A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090230400A1 (en) * 2008-03-14 2009-09-17 Chunghwa Picture Tubes, Ltd. Thin film transistor and fabricating method thereof
CN105047819A (zh) * 2015-06-23 2015-11-11 福州大学 一种有机半导体纳米线阵列导电沟道薄膜晶体管制备方法
CN111785635A (zh) * 2020-07-16 2020-10-16 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN113314615A (zh) * 2021-06-04 2021-08-27 华南理工大学 一种薄膜晶体管以及制备方法
CN113394299A (zh) * 2021-06-16 2021-09-14 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制备方法、显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090230400A1 (en) * 2008-03-14 2009-09-17 Chunghwa Picture Tubes, Ltd. Thin film transistor and fabricating method thereof
CN105047819A (zh) * 2015-06-23 2015-11-11 福州大学 一种有机半导体纳米线阵列导电沟道薄膜晶体管制备方法
CN111785635A (zh) * 2020-07-16 2020-10-16 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN113314615A (zh) * 2021-06-04 2021-08-27 华南理工大学 一种薄膜晶体管以及制备方法
CN113394299A (zh) * 2021-06-16 2021-09-14 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制备方法、显示面板

Also Published As

Publication number Publication date
CN117461144A (zh) 2024-01-26

Similar Documents

Publication Publication Date Title
JP4309967B2 (ja) 半導体装置およびその製造方法
JP3915180B2 (ja) トレンチ型ｍｏｓ半導体装置およびその製造方法
US8178409B2 (en) Semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same
TW200425509A (en) Stop structure of trench type DMOS device and its formation method
JP5442921B2 (ja) ゲート酸化膜の完全性を向上させた半導体トレンチ素子
CN108172563B (zh) 一种带有自对准接触孔的沟槽形器件及其制造方法
TW201344900A (zh) 具有超接面結構的半導體裝置及其製造方法
US6620669B2 (en) Manufacture of trench-gate semiconductor devices
CN104966720B (zh) Tft基板结构及其制作方法
TW201351640A (zh) 元件與其形成方法
CN113206015A (zh) 薄膜晶体管及其制作方法、阵列基板及显示装置
TW202137570A (zh) 半導體元件及其製造方法
WO2023221110A1 (zh) 纳米线、薄膜晶体管制备方法、薄膜晶体管及半导体器件
US4477963A (en) Method of fabrication of a low capacitance self-aligned semiconductor electrode structure
CN104617151B (zh) 低温多晶硅薄膜晶体管及制作方法、阵列基板及显示装置
CN111081778A (zh) 一种碳化硅沟槽型mosfet器件及其制造方法
CN104347639A (zh) 薄膜晶体管基板及其制作方法
JP4135838B2 (ja) 半導体装置及びその製造方法
CN103872095B (zh) P型ldmos器件的沟槽及工艺方法
US10672623B2 (en) Transistor and method of manufacturing the same
CN104617112B (zh) 阵列基板及其制作方法、显示装置
CN112838126A (zh) 带屏蔽区的非对称碳化硅umosfet器件及制备方法
CN106356304A (zh) 半导体制作工艺
CN103187292B (zh) 一种制造沟槽型半导体功率器件的方法
WO2023225831A1 (zh) 纳米线、阵列基板制备方法、阵列基板及电子设备

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280001313.1

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22942149

Country of ref document: EP

Kind code of ref document: A1