WO2023225831A1 - 纳米线、阵列基板制备方法、阵列基板及电子设备 - Google Patents

纳米线、阵列基板制备方法、阵列基板及电子设备 Download PDF

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WO2023225831A1
WO2023225831A1 PCT/CN2022/094587 CN2022094587W WO2023225831A1 WO 2023225831 A1 WO2023225831 A1 WO 2023225831A1 CN 2022094587 W CN2022094587 W CN 2022094587W WO 2023225831 A1 WO2023225831 A1 WO 2023225831A1
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layer
guide
trench
electrode
area
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PCT/CN2022/094587
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English (en)
French (fr)
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吴昊
关峰
吕杨
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京东方科技集团股份有限公司
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Priority to CN202280001387.5A priority Critical patent/CN117461119A/zh
Priority to PCT/CN2022/094587 priority patent/WO2023225831A1/zh
Publication of WO2023225831A1 publication Critical patent/WO2023225831A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present disclosure belongs to the field of semiconductor technology, and specifically relates to a nanowire, an array substrate preparation method, an array substrate and electronic equipment.
  • Silicon nanowires have broad application prospects in the fields of micro-nano electronic equipment, optoelectronic devices, chemical and biological sensing devices, energy conversion and storage devices, etc. Silicon nanowires are one-dimensional nanostructures with significant quantum effects, large specific surface areas and other characteristics, which enable field-effect transistor (MOS) devices based on silicon nanowires to have good gate control capabilities and current characteristics.
  • Planar solid-liquid-solid (IP-SLS) growth technology is a metal-catalyzed growth technology for nanowires.
  • the silicon-based nanowires formed through this technology have single-crystal-like characteristics and are highly compatible with display panel production lines. , which can be used as a potential application technology for future production line upgrades.
  • the present disclosure aims to provide a nanowire, an array substrate preparation method, an array substrate and an electronic device.
  • the present disclosure provides a method for preparing nanowires, which includes:
  • a trench layer having a guide groove is formed on the surface of the insulating layer facing away from the substrate; the width of the guide groove is 0.8 to 1.2 times the particle diameter of the induction particles of a specified particle size;
  • the precipitation layer is processed so that specified atoms in the precipitation layer are induced by the induction particles to precipitate along the guide groove to form nanowires.
  • forming a trench layer with a guide trench on a surface of the insulating layer facing away from the substrate includes:
  • the trench dielectric layer is processed using electron beam lithography technology to form a trench layer with guide trenches.
  • the trench layer includes an activation area and a growth area
  • the spacing of the guide trenches in the activation area is greater than the spacing of the guide trenches in the growth area
  • the guide trenches in the activation area are connected to the guide trenches through transition trenches.
  • the guide grooves in the growth area are connected correspondingly.
  • the spacing of the guide trenches located in the active region is 0.2-2 ⁇ m; the spacing of the guide trenches located in the growth region is 50-500 nm.
  • the activation area includes a first activation area and a second activation area
  • the growth area includes a first growth area and a second growth area, and the guide trench of the first growth area and the first activation area The guide trenches are connected, and the guide trenches of the second growth area are connected with the guide trenches of the second activation area.
  • the width of the guide trench in the first active area is greater than the width of the guide trench in the first active area, and the width of the guide trench in the first growth area is the same as the width of the guide trench in the first active area.
  • the width of the guide trench in the second growth area is the same as the width of the guide trench in the second activation area.
  • the guide trenches of the activation area and the growth area are formed in one process
  • the induction particles in the guide grooves of the first activation area and the second activation area are formed through one process
  • the nanowires in the first growth area and the second growth area are formed through one process.
  • the material of the precipitation layer includes amorphous silicon
  • Processing the precipitation layer so that specified atoms in the precipitation layer are induced by the induction particles to precipitate along the guide groove to form nanowires includes:
  • the precipitation layer is annealed so that the silicon atoms in the precipitation layer are induced by the induction particles to precipitate along the guide trench to form silicon nanowires.
  • the step of processing the precipitation layer so that specified atoms in the precipitation layer are induced by the induction particles to precipitate along the guide groove to form nanowires includes:
  • the induced particles outside the nanowires are removed by etching liquid.
  • embodiments of the present disclosure also provide an array substrate preparation method, which includes forming nanowires.
  • the preparation method of the nanowires includes the method provided by the embodiments of the disclosure.
  • the step of processing the precipitation layer so that specified atoms in the precipitation layer are induced by the induction particles to precipitate along the guide groove to form nanowires also includes:
  • the transition layer is patterned, and a first transition electrode and a second transition electrode are formed on the transition layer.
  • the method further includes:
  • the first electrode layer to obtain a first electrode and a second electrode, the first electrode is stacked on the first transition electrode, and the second electrode is stacked on the second transition electrode;
  • a passivation layer is deposited covering the exposed surfaces of the nanowire, the first transition electrode, the second transition electrode, the first electrode and the second electrode.
  • the substrate includes one of a glass substrate and a silicon substrate.
  • an array substrate which includes:
  • the substrate including a first surface
  • An insulating layer, the insulating layer is disposed on the first surface of the substrate;
  • a trench layer is provided on the surface of the insulating layer facing away from the substrate, the trench layer is provided with a guide trench, and the width of the guide trench is 50 to 250 nm;
  • a nanowire layer is provided on a surface of the insulating layer facing away from the substrate.
  • the nanowire layer is provided with nanowires, and the nanowires are embedded in the guide trench.
  • the trench layer includes an activation area and a growth area
  • the spacing of the guide trenches in the activation area is greater than the spacing of the guide trenches in the growth area
  • the guide trenches in the activation area are connected to the guide trenches through transition trenches.
  • the guide grooves in the growth area are connected correspondingly.
  • the spacing of the guide trenches located in the active region is 0.2-2 ⁇ m; the spacing of the guide trenches located in the growth region is 50-500 nm.
  • the activation area includes a first activation area and a second activation area
  • the growth area includes a first growth area and a second growth area, and the guide trench of the first growth area and the first activation area The guide trenches are connected, and the guide trenches of the second growth area are connected with the guide trenches of the second activation area.
  • the width of the guide trench in the first active area is greater than the width of the guide trench in the first active area, and the width of the guide trench in the first growth area is the same as the width of the guide trench in the first active area.
  • the width of the guide trench in the second growth area is the same as the width of the guide trench in the second activation area.
  • the nanowire layer includes multiple groups of nanowire groups, and each group of the nanowire group includes a plurality of nanowires arranged at intervals; the spacing between the nanowires in the nanowire groups corresponding to the active area is 0.2 to 2 ⁇ m, and the spacing of the nanowires in the nanowire group corresponding to the growth area is 50 to 500 nm.
  • the line width of the nanowires in the nanowire group corresponding to the first activation area and the first growth area is 60-80 nm
  • the nanowire group corresponding to the second activation area and the second growth area The line width of the nanowires in is 20 ⁇ 30nm.
  • the array substrate further includes: a first electrode layer, the first electrode layer is stacked on a surface of the nanowire layer facing away from the substrate, and the first electrode provided on the first electrode layer and the nanowire layer are The source region of the wire is electrically connected, and the second electrode provided on the first electrode layer is electrically connected to the drain region of the nanowire.
  • the array substrate further includes: a transition layer, the transition layer is disposed on a surface of the nanowire layer facing away from the substrate, and a first transition electrode disposed on the transition layer is stacked between the first electrode and the substrate. Between the source regions of the nanowires, a second transition electrode provided on the transition layer is stacked between the second electrode and the drain regions of the nanowires.
  • the array substrate further includes: a third electrode, the third electrode is disposed between the substrate and the insulating layer.
  • the array substrate further includes a passivation layer covering the exposed surfaces of the trench layer, the nanowire layer and the first electrode layer.
  • It also includes a passivation layer and a third electrode, the passivation layer covering the insulating layer and the exposed surface of the nanowire;
  • the third electrode is disposed on a surface of the passivation layer facing away from the substrate.
  • an embodiment of the present disclosure provides an electronic device, which includes the array substrate provided by an embodiment of the present disclosure.
  • Figure 1 is a schematic diagram of nanowire growth using IP-SLS technology
  • Figure 2 is a flow chart of a nanowire preparation method provided by an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of limiting growth on both sides of the guide groove in an embodiment of the present disclosure
  • Figure 4 is a schematic diagram of limiting growth on one side of a guide trench in an embodiment of the present disclosure
  • Figure 5 is a schematic structural diagram after forming guide grooves in an embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of a guide groove in an embodiment of the present disclosure.
  • Figure 7 is a schematic diagram of another guide groove in an embodiment of the present disclosure.
  • Figure 8 is a flow chart of an array substrate preparation method provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • Figure 10 is a partial structural schematic diagram of an array substrate provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram after step S1101 in an embodiment of the present disclosure.
  • Figure 12 is a schematic structural diagram after step S1102 in an embodiment of the present disclosure.
  • Figure 13 is a cross-sectional view along line A-A' in Figure 12 in an embodiment of the present disclosure
  • Figure 14 is a cross-sectional view along line B-B' in Figure 12 in an embodiment of the present disclosure
  • Figure 15 is a cross-sectional view along line C-C′ in Figure 12 in an embodiment of the present disclosure
  • Figure 16 is a schematic structural diagram after step S1103 in the embodiment of the present disclosure.
  • Figure 17 is a schematic structural diagram after step S1104 in the embodiment of the present disclosure.
  • Figure 18 is a cross-sectional view along line A-A' in Figure 17 in an embodiment of the present disclosure
  • Figure 19 is a cross-sectional view along line B-B' in Figure 17 in an embodiment of the present disclosure.
  • Figure 20 is a cross-sectional view along line C-C′ in Figure 17 in an embodiment of the present disclosure
  • Figure 21 is a schematic structural diagram after step S1105 in the embodiment of the present disclosure.
  • Figure 22 is a schematic structural diagram after step S1106 in the embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of nanowire growth using IP-SLS technology. As shown in Figure 1, the principle of nanowire growth includes the following steps:
  • step S11 the insulating layer 2 is prepared on the surface of the substrate 1, and a catalytic layer is prepared on the surface of the insulating layer 2 facing away from the substrate 1.
  • the metal particles are processed in situ to form nanoparticles 81, as shown in Figure 1(a).
  • step S12 a precursor layer 80 is deposited on the surface of the substrate 1, and then the substrate is heated to form alloy droplets 82, such as indium alloy droplets, at the three-phase interface, as shown in Figure 1(b).
  • alloy droplets 82 such as indium alloy droplets
  • step S13 the predetermined atoms absorbed by the alloy droplet interface are transported to the alloy droplet-nanowire interface to precipitate seed crystals 83, as shown in Figure 1(c).
  • Step S14 driven by Gibbs free energy, the largest seed crystal tilts the alloy droplets to move in the opposite direction, forming a new absorption interface, and finally obtains nanowires 84.
  • a trench layer is prepared before preparing the nanowires, and a guide trench is prepared in the trench layer, and the nanowires are formed in the guide trench.
  • the width of the guide trench affects the width of the nanowire, thereby affecting the on-state current and leakage current of the array substrate, and also affects the area of the active area.
  • Embodiments of the present disclosure provide a nanowire preparation method, which determines guide grooves based on induction particles of a specified particle size, thereby obtaining induction particles of a specified particle size in the guide trench, and uses the width of the guide trench to define the width of the nanowire. width to obtain ultrafine nanowires.
  • FIG. 2 is a flow chart of a nanowire preparation method provided by an embodiment of the present disclosure. As shown in Figure 2, the nanowire preparation method includes:
  • Step S201 prepare an insulating layer on the first surface of the substrate.
  • the substrate includes but is not limited to a glass substrate and a silicon substrate, and the present disclosure does not limit the material of the substrate.
  • the substrate includes a first surface and a second surface arranged oppositely, and both the first surface and the second surface can be used to carry the thin film transistor.
  • the embodiments of the present disclosure are described by taking the first surface as an example.
  • the material of the insulating layer may be a silicide such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic material such as polyimide or acrylic.
  • the insulating layer may be prepared by a deposition process, such as a physical vapor deposition or chemical vapor deposition process.
  • a deposition process such as a physical vapor deposition or chemical vapor deposition process.
  • the embodiment of the present disclosure does not limit the thickness of the insulating layer.
  • the thickness of the insulating layer is 3000 angstroms.
  • Step S202 Form a trench layer with a guide trench on the surface of the insulating layer facing away from the substrate.
  • the width of the guide groove is 0.8 to 1.2 times the particle diameter of the induction particles of a specified particle size, so that each guide groove can only accommodate one induction particle of a specified particle size in the width direction.
  • the nanowires are constrained by the guide grooves to form nanowires consistent with the size of the inducing particles of a specified particle size.
  • step S202 forming a trench layer with a guide trench on the surface of the insulating layer facing away from the substrate, includes: forming a trench dielectric layer on the surface of the insulating layer facing away from the substrate; using electron beam lithography technology to The trench dielectric layer is processed to form a trench layer with guide trenches.
  • the material of the trench dielectric layer can be silicides such as silicon nitride (SiNx), silicon oxide (SiOx), or organic materials such as polyimide and acrylic.
  • the thickness of the trench dielectric layer can be 1000-1500 Angstroms, for example, the thickness of the trench layer is 1200 Angstroms.
  • the trench dielectric layer is patterned through electron beam lithography (E-Beam Lithography, referred to as EBL) technology to form a trench layer with guide trenches.
  • EBL electron beam lithography
  • EBL technology can obtain ultra-fine guide trenches, such as guide trenches below 0.5 microns, such as 20 nanometer guide trenches. The smaller the width of the guide trench, the more closely the subsequently formed nanowires can be arranged, reducing the active area area of a single array substrate, thereby improving the resolution of the array substrate.
  • the trench layer is provided with multiple guide trenches.
  • the multiple guide trenches are arranged at intervals.
  • the spacing between adjacent guide trenches can be set as needed.
  • adjacent guide trenches are The spacing between grooves is not limited.
  • the widths of the multiple guide grooves can be all the same or partially the same, or multiple groups can be set according to requirements, and the widths of the guide grooves in each group are different.
  • Step S203 prepare induction particles in the guide groove.
  • the induced particles may be silicon induced particles, obtained by reducing indium tin oxide. Indium induced particles can also be obtained in other ways.
  • the inducing particles can also be other elements, and any element that can promote the formation of nanowires can be used as inducing particles.
  • the material of the catalytic layer includes indium tin oxide, and the induction particles include indium particles; the indium tin oxide is reduced using a plasma enhanced chemical vapor deposition (PECVD) process and hydrogen plasma to obtain the induction particles.
  • PECVD plasma enhanced chemical vapor deposition
  • Step S204 prepare a precipitation layer on the surface of the trench layer facing away from the substrate.
  • the precipitation layer is to generate nanowires. Under the catalytic action of the induced particles, the materials constituting the nanowires are precipitated from the extraction layer.
  • the precipitation layer can be prepared by a deposition process, such as a physical vapor deposition or chemical vapor deposition process.
  • the thickness of the precipitated layer may be 300-500 angstroms, for example, the thickness of the precipitated layer is 400 angstroms.
  • the material of the precipitation layer can be determined according to the material of the nanowire.
  • the material of the precipitation layer is amorphous silicon.
  • step S205 the precipitation layer is processed so that designated atoms in the precipitation layer are induced by the induction particles to precipitate along the guide groove to form nanowires.
  • designated atoms in the precipitation layer are induced by inducing particles to precipitate along the guide trench through processes such as annealing to form nanowires.
  • the width of the nanowire depends on the particle size (diameter) of the inducing particles.
  • the particle size of the inducing particles can be controlled, thereby accurately controlling the width of the nanowire.
  • the mobility of carriers is higher, while for nanowires with smaller diameters, the mobility of carriers is lower. Therefore, by precisely controlling the width of the nanowires, different carrier mobility can be precisely controlled. mobility of currents.
  • the width of the guide trench 41 When the width of the guide trench 41 is relatively wide, for example, when the width of the guide trench 41 exceeds the particle size of the inducing particles 52 , the nanowires will grow along the single side wall of the guide trench 41 , as shown in FIG. 3 .
  • the width of the guide trench 41 is narrow, the width of the guide trench 41 is used to limit the particle size of the induction particles 52, and the nanowires will grow along the double side walls of the guide trench, as shown in Figure 4.
  • the width of the nanowire can be limited by using double sidewalls to limit the size of the induced particles. Therefore, by determining the width of the guide trench according to the desired nanowire diameter, nanowires with the desired diameter can be obtained when preparing nanowires.
  • the width of the guide trench is determined based on the induction particles of a specified particle size, so as to obtain the induction particles of the specified particle size in the guide trench, using
  • the width of the guide trench defines the width of the nanowire to obtain ultra-fine nanowires, obtain densely packed nanowires, reduce the area of the active area of a single array substrate, improve resolution, and control the on-state current and leakage current and improve the performance of the array substrate.
  • step S203 preparing induction particles in the guide trench, includes: preparing a catalytic layer at a preset position; processing the catalytic layer to obtain induction particles in the guide trench.
  • a catalytic layer is used to generate inducing particles, and the material of the catalytic layer includes but is not limited to indium tin oxide (ITO).
  • ITO indium tin oxide
  • preparing a catalytic layer at a predetermined position includes: preparing a catalytic layer between an insulating layer and a trench layer.
  • the preset position is between the insulating layer and the trench layer, that is, the catalytic layer is disposed below the trench layer.
  • a catalytic layer is prepared on the surface of the insulating layer facing away from the substrate. The area where the catalytic layer covers the insulating layer can be set as needed.
  • the catalytic layer is disposed under the trench layer.
  • the area of the catalytic layer covered by the trench layer cannot grow induced particles. Therefore, the induced particles can only be generated in the guide trench, and in the trench layer facing away from the substrate The surface will not be generated, which can avoid the generation of disordered nanowires on the surface of the trench layer facing away from the substrate in subsequent processes, thus improving the yield of nanowires.
  • the trench layer 4 includes an activation area 71 and a growth area 72 .
  • the activation area 71 corresponds to the position of the catalytic layer 6
  • the guide trench 41 of the activation area 71 is consistent with the growth area 72 .
  • the guide trenches 41 have different spacings, and the guide trenches 41 of the activation area 71 are connected to the guide trenches 41 of the growth area 72 through transition trenches 42 .
  • the spacing of the guide trenches 41 located in the active region 71 is greater than the spacing of the guide trenches 41 located in the growth region 72 .
  • 41 have the same number, and each guide trench 14 extends from the activation area 71 to the growth area 72 through a transition trench 42 .
  • the distance between the guide trenches in the growth area provided by the embodiments of the present disclosure is smaller than the distance between the guide trenches in the active area, which can reduce the area of the growth area, thereby reducing the area of the active layer, thereby improving the resolution of the array substrate.
  • the spacing of the guide trenches located in the active region is 0.2-2 ⁇ m; the spacing of the guide trenches located in the growth region is 50-500 nm.
  • the shape of the transition trench 42 projected on the surface of the insulating layer 2 facing away from the substrate 1 may be an arc. , any kind of straight line.
  • Figure 6 is a schematic diagram of a guide groove in an embodiment of the present disclosure.
  • the shape of the transition trench 42 is an arc, that is, the guide trench 41 of the activation area 71 is connected to the guide trench 41 of the growth area 72 through the arc-shaped transition trench 42 .
  • Figure 7 is a schematic diagram of another guide groove in an embodiment of the present disclosure.
  • the shape of the transition trench 42 is a straight line, that is, the guide trench 41 of the active area 71 is connected to the guide trench 41 of the growth area 72 through the linear transition trench 42 .
  • the activation area 71 includes a first activation area 71a and a second activation area 71b; the growth area 72 includes a first growth area 72a and a second growth area 72b, and the guide trench of the first growth area 71a is in contact with the first growth area 72a.
  • the guide trenches of the active area 71a are connected to each other, and the guide trenches of the second growth area 72b are connected to the guide trenches of the second active area 72b.
  • the first growth region 72a and the second growth region 72b are respectively located on both sides of the activation region 71, and the guide trench of the activation region 71 extends to the first growth region 72a and the second growth region 72b, and is connected with the first growth region 72a and the second growth region 72b.
  • the guide trenches of the first growth area 72a and the second growth area 72b are connected.
  • the width of the guide trench of the first activation region 71a is greater than the width of the guide trench of the second activation region 71b, and the width of the guide trench of the first growth region 72a is the same as that of the guide trench of the first activation region 71a.
  • the width of the grooves is the same, and the width of the guide groove of the second growth region 72b is the same as the width of the guide groove of the second active region 71b.
  • the width of the guide trench 41 of the first growth region 72a is different from the width of the guide trench 41 of the second growth region 72b. In some embodiments, the width of the guide trench 41 in the first activation region 71a and the first growth region 72a is 60-80 nm, and the width of the guide trench 41 in the second activation region 71b and the second growth region 72b is 20-80 nm. 30nm.
  • the guide trenches in the activation region 71 and the growth region 72 are formed through one process, that is, the trench layer is processed through one mask process, and corresponding guide trenches are formed in the activation region 71 and the growth region 72 . Forming guide trenches in the activation region 71 and the growth region 72 in one process can reduce the manufacturing cost of the array substrate.
  • the induction particles in the guide grooves of the first activation region 71a and the second activation region 71b are formed through one process, that is, when the catalytic layer is reduced, the induction particles in the guide grooves of the first activation region 71a and the second activation region 71b are formed in one process.
  • the guide grooves of the activation area 71b simultaneously form induction particles. Since the width of the guide groove in the first activation region 71a is greater than the width of the guide groove in the second activation region 71b, the size of the induction particles precipitated in the first activation region 71a is larger than the size of the induction particles precipitated in the second activation region 71b.
  • the material of the precipitation layer includes amorphous silicon (a-Si) or other suitable materials.
  • Step S205 processing the precipitation layer so that designated atoms in the precipitation layer are induced by the induction particles to precipitate along the guide groove to form nanowires, including: annealing the precipitation layer so that the silicon atoms in the precipitation layer are induced The particles are induced to precipitate along the guide trench to form silicon nanowires.
  • the annealing temperature may be 350-400°C, and the annealing time may be 30-60 minutes.
  • the silicon atoms in the precipitated layer are induced by the induction particles to precipitate along the guide trench, and are converted from amorphous to crystal, thereby forming silicon nanowires.
  • the nanowires in the first growth region 72a and the second growth region 72b are formed in one process, that is, annealing the precipitation layer, and the nanowires are simultaneously generated in the first growth region 72a and the second growth region 72b. .
  • step S205 is to process the precipitation layer so that designated atoms in the precipitation layer are induced by the induction particles to precipitate along the guide groove. After forming the nanowires, the process includes: removing the residues of the precipitation layer and the nanowires. inducing particles outside.
  • Removing the residues of the precipitation layer and the induction particles outside the nanowires can avoid the influence of the residues of the precipitation layer and the induction particles on the overlap between the first electrode layer and the nanowires, improve the overlap performance of the electrodes and the nanowires, and improve Nanowire mobility.
  • a plasma-enhanced chemical vapor deposition process is used to etch the residue of the precipitated layer using hydrogen plasma, and excess indium particles are removed using an ITO etching solution.
  • the width of the guide trench is determined based on the induction particles of a specified particle size, so that the width direction of the guide trench can only accommodate one particle of induction particles. Moreover, the particle size of the induced particles can be limited to prevent the particle size of the induced particles from being too large.
  • the two side walls of the guide trench can be used to limit the growth of nanowires and reduce the line width of the nanowires, thereby reducing the size of a single thin film transistor.
  • the area of the active area improves the resolution of the thin film transistor, and can reduce the excessive leakage current caused by the hot carrier effect and the short channel effect, thereby reducing the power consumption of the transistor and thereby reducing the power consumption of the backplane. .
  • Embodiments of the present disclosure provide an array substrate preparation method that determines guide grooves based on induced particles of a specified particle size, thereby obtaining induced particles of a specified particle size within the guide trench, and uses the width of the guide trench to define nanowires width, thereby obtaining ultrafine nanowires.
  • FIG. 8 is a flow chart of an array substrate preparation method provided by an embodiment of the present disclosure. As shown in Figure 8, the array substrate preparation method provided by the embodiment of the present disclosure includes:
  • Step S801 prepare an insulating layer on the first surface of the substrate.
  • the substrate includes but is not limited to a glass substrate and a silicon substrate, and the present disclosure does not limit the material of the substrate.
  • the substrate includes a first surface and a second surface arranged oppositely, and both the first surface and the second surface can be used to carry the array substrate.
  • the embodiments of the present disclosure are described by taking the first surface as an example.
  • the material of the insulating layer may be a silicide such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic material such as polyimide or acrylic.
  • the insulating layer may be prepared by a deposition process, such as a physical vapor deposition or chemical vapor deposition process.
  • a deposition process such as a physical vapor deposition or chemical vapor deposition process.
  • the embodiment of the present disclosure does not limit the thickness of the insulating layer.
  • the thickness of the insulating layer is 3000 angstroms.
  • Step S802 Form a trench layer with a guide trench on the surface of the insulating layer facing away from the substrate.
  • the width of the guide groove is 0.8 to 1.2 times the particle diameter of the induction particles of a specified particle size, so that each guide groove can only accommodate one induction particle of a specified particle size in the width direction.
  • the nanowires are constrained by the guide grooves to form nanowires consistent with the size of the inducing particles of a specified particle size.
  • step S802 forming a trench layer with a guide trench on the surface of the insulating layer facing away from the substrate, includes: forming a trench dielectric layer on the surface of the insulating layer facing away from the substrate; using electron beam lithography technology to The trench dielectric layer is processed to form a trench layer with guide trenches.
  • the material of the trench dielectric layer can be silicides such as silicon nitride (SiNx), silicon oxide (SiOx), or organic materials such as polyimide and acrylic.
  • the thickness of the trench dielectric layer can be 1000-1500 Angstroms, for example, the thickness of the trench layer is 1200 Angstroms.
  • the trench dielectric layer is patterned through electron beam lithography (E-Beam Lithography, referred to as EBL) technology to form a trench layer with guide trenches.
  • EBL electron beam lithography
  • EBL technology can obtain ultra-fine guide trenches, such as guide trenches below 0.5 microns, such as 20 nanometer guide trenches. The smaller the width of the guide trench, the more closely the subsequently formed nanowires can be arranged, reducing the active area area of a single array substrate, thereby improving the resolution of the array substrate.
  • the trench dielectric layer is patterned, and multiple guide trenches are obtained in the trench dielectric layer.
  • the multiple guide trenches can be arranged at intervals, and the spacing between adjacent guide trenches can be as needed. It is assumed that the embodiment of the present disclosure does not limit the spacing between adjacent guide grooves.
  • the widths of the multiple guide grooves can be all the same or partially the same, or multiple groups can be set according to requirements, and the widths of the guide grooves in each group are different.
  • Step S803 prepare induction particles in the guide groove.
  • step S803, preparing induction particles in the guide groove includes: preparing a catalytic layer at a preset position; and processing the catalytic layer to obtain induction particles in the guide groove.
  • a catalytic layer is used to generate inducing particles, and the material of the catalytic layer includes but is not limited to indium tin oxide (ITO).
  • ITO indium tin oxide
  • the preset position may be between the insulating layer and the trench layer, and preparing the catalytic layer at the preset position includes: preparing the catalytic layer between the insulating layer and the trench layer, that is, the catalytic layer is disposed in the trench. Below the layer, after preparing the insulating layer, a catalytic layer is prepared on the surface of the insulating layer facing away from the substrate. The area where the catalytic layer covers the insulating layer can be set as needed.
  • the catalytic layer is disposed under the trench layer.
  • the area of the catalytic layer covered by the trench layer cannot grow induced particles. Therefore, the induced particles can only be generated in the guide trench, and in the trench layer facing away from the substrate The surface will not be generated, which can avoid the generation of disordered nanowires on the surface of the trench layer facing away from the substrate in subsequent processes, thus improving the yield of nanowires.
  • the material of the catalytic layer includes indium tin oxide, and the induction particles include indium particles; the indium tin oxide is reduced using a plasma enhanced chemical vapor deposition (PECVD) process and hydrogen plasma to obtain the induction particles.
  • PECVD plasma enhanced chemical vapor deposition
  • Step S804 Prepare a precipitation layer on the surface of the trench layer facing away from the substrate.
  • the precipitation layer is to generate nanowires. Under the catalytic action of the induced particles, the materials constituting the nanowires are precipitated from the extraction layer.
  • the precipitation layer can be prepared by a deposition process, such as a physical vapor deposition or chemical vapor deposition process.
  • the thickness of the precipitated layer may be 300-500 angstroms, for example, the thickness of the precipitated layer is 400 angstroms.
  • the material of the precipitation layer can be determined according to the material of the nanowire.
  • the material of the precipitation layer is amorphous silicon.
  • the precipitation layer 7 includes an activation region 71 and a growth region 72 .
  • the activation region 71 corresponds to the position of the catalytic layer 6
  • the guide groove 41 of the activation region 71 corresponds to the guide groove 41 of the growth region 72 .
  • the spacing of the trenches 41 is different, and the guide trenches 41 of the activation area 71 are connected to the guide trenches 41 of the growth area 72 through transition trenches 42 .
  • the spacing of the guide trenches 41 located in the active region 71 is greater than the spacing of the guide trenches 41 located in the growth region 72 .
  • 41 have the same number, and each guide trench 14 extends from the activation area 71 to the growth area 72 through a transition trench 42 .
  • the spacing of the guide trenches located in the active region is 0.2-2 ⁇ m; the spacing of the guide trenches located in the growth region is 50-500 nm.
  • the shape of the transition trench 42 projected on the surface of the insulating layer 2 facing away from the substrate 1 may be an arc. , any kind of straight line.
  • the activation area 71 includes a first activation area 71a and a second activation area 71b; the growth area 72 includes a first growth area 72a and a second growth area 72b, and the guide trench of the first growth area 71a is in contact with the first growth area 72a.
  • the guide trenches of the active area 71a are connected to each other, and the guide trenches of the second growth area 72b are connected to the guide trenches of the second active area 72b.
  • the growth area 72 includes a first growth area 72a and a second growth area 72b.
  • the first growth area 72a and the second growth area 72b are respectively located on both sides of the activation area 71.
  • the guide grooves of the activation area 71 are directed toward The first growth area 72a and the second growth area 72b extend and are connected with the guide trenches of the first growth area 72a and the second growth area 72b.
  • the width of the guide trench of the first activation region 71a is greater than the width of the guide trench of the second activation region 71b, and the width of the guide trench of the first growth region 72a is the same as that of the first activation region 71a.
  • the width of the grooves is the same, and the width of the guide groove of the second growth region 72b is the same as the width of the guide groove of the second active region 71b.
  • the width of the guide trench 41 of the first growth region 72a is different from the width of the guide trench 41 of the second growth region 72b. In some embodiments, the width of the guide trench 41 in the first activation region 71a and the first growth region 72a is 60-80 nm, and the width of the guide trench 41 in the second activation region 71b and the second growth region 72b is 20-80 nm. 30nm.
  • the guide trenches in the activation region 71 and the growth region 72 are formed through one process, that is, the trench layer is processed through one mask process, and corresponding guide trenches are formed in the activation region 71 and the growth region 72 . Forming guide trenches in the activation region 71 and the growth region 72 in one process can reduce the manufacturing cost of the array substrate.
  • the induction particles in the guide grooves of the first activation region 71a and the second activation region 71b are formed through one process, that is, when the catalytic layer is reduced, the induction particles in the guide grooves of the first activation region 71a and the second activation region 71b are formed in one process.
  • the guide grooves of the activation area 71b simultaneously form induction particles. Since the width of the guide groove in the first activation region 71a is greater than the width of the guide groove in the second activation region 71b, the size of the induction particles precipitated in the first activation region 71a is larger than the size of the induction particles precipitated in the second activation region 71b.
  • the material of the precipitation layer includes amorphous silicon (a-Si) or other suitable materials.
  • Step S805 process the precipitation layer so that designated atoms in the precipitation layer are induced by the induction particles to precipitate along the guide groove to form nanowires.
  • designated atoms in the precipitation layer are induced by inducing particles to precipitate along the guide trench through processes such as annealing to form nanowires.
  • Nanowires can serve as the active layer of transistors for conductive channels.
  • the width of the nanowire depends on the particle size (diameter) of the induced particles.
  • the particle size of the induced particles can be controlled, thereby precisely controlling the width of the nanowire.
  • the mobility of carriers is higher, while for nanowires with smaller diameters, the mobility of carriers is lower. Therefore, by precisely controlling the width of the nanowires, different carrier mobility can be precisely controlled. mobility of currents.
  • the nanowires in the first growth region 72a and the second growth region 72b are formed in one process, that is, annealing the precipitation layer, and the nanowires are simultaneously generated in the first growth region 72a and the second growth region 72b. .
  • step S805 is to process the precipitation layer so that designated atoms in the precipitation layer are induced by the induction particles to precipitate along the guide groove to form nanowires, including: annealing the precipitation layer to make the precipitation layer The silicon atoms inside are precipitated along the guide trench under the induction of the induction particles, forming silicon nanowires.
  • the annealing temperature may be 350-400°C, and the annealing time may be 30-60 minutes.
  • the silicon atoms in the precipitated layer are induced by the induction particles to precipitate along the guide trench, and are converted from amorphous to crystal, thereby forming silicon nanowires.
  • step S805 the precipitation layer is processed so that designated atoms in the precipitation layer are induced by the induction particles to precipitate along the guide trench.
  • the process includes:
  • Step S806 Remove residues of the precipitation layer and induced particles other than the nanowires.
  • Removing the residues of the precipitation layer and the induction particles outside the nanowires can avoid the influence of the residues of the precipitation layer and the induction particles on the overlap between the first electrode layer and the nanowires, improve the overlap performance of the electrodes and the nanowires, and improve Nanowire mobility.
  • a plasma-enhanced chemical vapor deposition process is used to etch the residue of the precipitated layer using hydrogen plasma, and excess indium particles are removed using an ITO etching solution.
  • Step S807 prepare a sacrificial layer on the surface of the trench layer facing away from the substrate, prepare a transition layer on the surface of the sacrificial layer facing away from the substrate, pattern the transition layer, and form a first transition electrode and a second transition electrode on the transition layer .
  • the material of the sacrificial layer may be amorphous silicon, and the thickness may be 300 to 500 angstroms.
  • the embodiments of the present disclosure do not limit the preparation method of the sacrificial layer.
  • the sacrificial layer can be prepared through a deposition process.
  • the material of the transition layer may be N + amorphous silicon, and the thickness of the transition layer is 500-1000A.
  • the embodiments of the present disclosure do not limit the preparation method of the transition layer.
  • the transition layer can be prepared through a deposition process.
  • the sacrificial layer is disposed between the transition layer and the nanowire, when patterning the transition layer, the problem of reducing the leakage current due to damage to the nanowire can be avoided.
  • step S807, after patterning the transition layer also includes:
  • Step S808 Prepare a first electrode layer on the surface of the transition layer facing away from the substrate; pattern the first electrode layer to obtain a first electrode and a second electrode.
  • the first electrode is stacked on the first transition electrode
  • the second electrode is stacked on the first transition electrode. placed on the second transition electrode.
  • the material of the first electrode layer includes at least any one of conductive metals such as molybdenum, copper, aluminum, etc., and the thickness of the first electrode layer is more than 2000 angstroms, for example, the thickness of the first electrode layer is 2200 angstroms.
  • the embodiment of the present disclosure does not limit the preparation method of the first electrode layer.
  • the first electrode layer may be prepared through a physical vapor deposition process.
  • the first electrode layer is patterned through coating, exposure, and development processes to obtain the first electrode and the second electrode.
  • the first electrode may be the drain electrode of the thin film transistor, and the second electrode may be the source electrode of the thin film transistor; or, the first electrode may be the source electrode of the thin film transistor, and the second electrode may be the drain electrode of the thin film transistor.
  • the first transition electrode since the first electrode is stacked on the first transition electrode, that is, the first transition electrode is disposed between the first electrode and the nanowire, the first transition electrode forms an ohmic contact with the nanowire, thereby reducing the The contact resistance between an electrode and the nanowire improves the characteristics of the thin film transistor.
  • the second electrode is stacked on the second transition electrode, that is, the second transition electrode is provided between the second electrode and the nanowire. The second transition electrode forms ohmic contact with the nanowire, thereby reducing the friction between the second electrode and the nanowire. The contact resistance improves the characteristics of thin film transistors.
  • the method further includes:
  • Step S809 deposit a passivation layer, pattern the passivation layer, expose at least part of the surface of the first electrode and the second electrode facing away from the substrate, and prepare a third electrode on the surface of the passivation layer facing away from the substrate, wherein passivation The layer covers the nanowire, the first transition electrode, the second transition electrode, the exposed surfaces of the first electrode and the second electrode.
  • the materials of the passivation layer include but are not limited to silicon oxide (SiOx) and silicon nitride (SiNx).
  • the thickness of the passivation layer only needs to cover the conductive layer.
  • the embodiment of the present disclosure does not limit the thickness of the passivation layer.
  • the thickness of the passivation layer may be 800 angstroms or 400 angstroms.
  • the embodiments of the present disclosure do not limit the preparation method of the passivation layer.
  • the passivation layer can be prepared by deposition or other processes.
  • the method further includes:
  • the passivation layer can be patterned through coating, exposure, and development processes to expose at least part of the surface of the first electrode and the second electrode facing away from the substrate.
  • the material of the third electrode may be conductive metal, such as molybdenum or copper.
  • the embodiment of the present disclosure does not limit the thickness of the third electrode.
  • the thickness of the third electrode is 500 angstroms or 2200 angstroms.
  • the third electrode may serve as a gate electrode of the thin film transistor, and the first electrode, the second electrode, and the third electrode constitute the transistor. Since the gate is on top of the passivation layer, the thin film transistor may be called a top-gate structure transistor.
  • step S801 when the thin film transistor adopts a bottom gate structure, before step S801 prepares an insulating layer on the first surface of the substrate, it also includes: preparing a third electrode of the transistor on the first surface of the substrate, that is, the third electrode of the transistor. Three electrodes are arranged between the substrate and the insulating layer. At this time, the passivation layer covers the exposed surfaces of the trench layer, the nanowire layer and the first electrode layer.
  • the third electrode serves as the gate of the transistor.
  • the material of the third electrode can be conductive metal such as molybdenum and copper.
  • the thickness of the third electrode can be 500 angstroms or 2200 angstroms. The embodiment of the present disclosure does not limit the thickness of the third electrode.
  • the width of the guide trench is determined based on the induction particles of a specified particle size, so that the width direction of the guide trench can only accommodate one particle of induction particles, and The particle size of the induced particles can be limited to prevent the induced particles from being too large.
  • the two side walls of the guide trench can be used to limit the growth of the nanowires and reduce the line width of the nanowires, thereby reducing the efficiency of a single thin film transistor.
  • the area of the source area improves the resolution of the thin film transistor, and can reduce the excessive leakage current caused by the hot carrier effect and the short channel effect, thereby reducing the power consumption of the transistor and thereby reducing the power consumption of the backplane.
  • Embodiments of the present disclosure also provide an array substrate.
  • the nanowires of the array substrate limit the width of the nanowires by guiding grooves, so that ultrafine nanowires can be obtained, thereby improving the resolution of the array substrate.
  • FIG. 9 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a partial structural schematic diagram of an array substrate provided by an embodiment of the present disclosure. As shown in Figure 9 and Figure 10, the array substrate includes:
  • Substrate 1 the substrate includes a first surface.
  • the substrate includes but is not limited to a glass substrate and a silicon substrate, and the present disclosure does not limit the material of the substrate.
  • the substrate includes a first surface and a second surface arranged oppositely, and both the first surface and the second surface can be used to carry various components of the electronic device.
  • Insulating layer 2 is provided on the first surface of the substrate 1 .
  • the material of the insulating layer 2 can be silicides such as silicon nitride and silicon oxide, or organic materials such as polyimide and acrylic.
  • the thickness of the insulating layer is not limited in the embodiments of the present disclosure.
  • the trench layer 4 is provided on the surface of the insulating layer facing away from the substrate.
  • the trench layer is provided with a guide trench, and the width of the guide trench is 50 to 250 nm.
  • the trench layer 4 includes an activation region 71 and a growth region 72.
  • the spacing of the guide trenches of the activation region 71 is greater than the spacing of the guide trenches of the growth region 72.
  • the spacing of the guide trenches of the activation region 71 is The trenches are correspondingly connected to the guide trenches of the growth region 72 through transition trenches 42 .
  • the spacing of the guide trenches located in the active region is 0.2-2 ⁇ m; the spacing of the guide trenches located in the growth region is 50-500 nm.
  • the activation area 71 includes a first activation area 71a and a second activation area 71b; the growth area 72 includes a first growth area 72a and a second growth area 72b, and the guide groove of the first growth area 72a The groove is connected to the guide trench of the first activation area 71a, and the guide trench of the second growth area 72b is connected to the guide trench of the second activation area 71b.
  • the width of the guide trench of the first activation region 71a is greater than the width of the guide trench of the first activation region 71b, and the width of the guide trench of the first growth region 72a is the same as that of the first growth region 72a.
  • the width of the guide trench in the active area 71a is the same, and the width of the guide trench in the second growth area 72b is the same as the width of the guide trench in the second active area 71b.
  • the material of the trench layer 4 includes silicon oxide, silicon nitride, etc., and the thickness of the trench layer 4 is 1000-1500 angstroms.
  • the number of guide grooves can be one or more as required.
  • the nanowire layer 5 is provided on the surface of the insulating layer 2 facing away from the substrate 1 .
  • the nanowire layer 5 is provided with nanowires 51 , and the nanowires 51 are embedded in the guide trenches 41 .
  • the nanowire layer 5 includes multiple groups of nanowire groups, each group of nanowire groups includes a plurality of spaced apart nanowires; the spacing of the nanowires in the nanowire groups corresponding to the active area is 0.2 to 2 ⁇ m, and the growth rate is 0.2 to 2 ⁇ m. The spacing of the nanowires in the corresponding nanowire group is 50 to 500nm.
  • the line width of the nanowires in the nanowire group corresponding to the first activation region and the first growth region is 60 to 80 nm
  • the nanowires in the nanowire group corresponding to the second activation region and the second growth region have a line width of 60 to 80 nm.
  • the line width of the line is 20 ⁇ 30nm.
  • the array substrate further includes a first electrode layer, the first electrode layer is stacked on a surface of the nanowire layer facing away from the substrate, and the first electrode provided on the first electrode layer is electrically connected to the source region of the nanowire. , the second electrode provided on the first electrode layer is electrically connected to the drain region of the nanowire.
  • the material of the first electrode layer may be a conductive metal material.
  • the material of the first electrode layer 4 includes at least one of molybdenum, copper, and aluminum.
  • the first electrode 21 and the second electrode 22 can respectively serve as the source electrode and the drain electrode of the array substrate.
  • the array substrate further includes a transition layer, the transition layer is disposed on a surface of the nanowire layer facing away from the substrate, and the first transition electrode 91 disposed on the transition layer is stacked on the first electrode 21 and the source of the nanowire 51 Between the electrode regions, a second transition electrode 92 provided in the transition layer is stacked between the second electrode 22 and the drain region of the nanowire 51 .
  • the material of the first transition electrode 91 and the second transition electrode 92 is N + type amorphous silicon (N + a-Si).
  • a first transition electrode 91 is disposed between the first electrode 21 and the source region of the nanowire 51
  • a second transition electrode is disposed between the second electrode 22 and the drain region of the nanowire 51 92.
  • the first transition electrode 91 can improve the abnormal overlap problem between the first electrode 21 and the nanowire 51, reduce the contact barrier of the metal-semiconductor contact, enhance the tunneling effect at the interface, and reduce the large resistance phenomenon of the array substrate.
  • the array substrate further includes: a third electrode 23 disposed between the substrate and the insulating layer.
  • the third electrode 23 may be a gate electrode of a thin film transistor, and the first electrode 21 , the second electrode 22 and the third electrode 23 constitute a thin film transistor. Since the third electrode 23 is disposed at the bottom of the thin film transistor, that is, the gate electrode is disposed at the bottom of the thin film transistor, therefore, the thin film transistor may be called a transistor with a bottom gate structure.
  • the array substrate further includes a passivation layer 11 covering the trench layer, the nanowire layer and the exposed surfaces of the first electrode layer.
  • the passivation layer 11 can protect the insulating layer 2, the first electrode layer 10 and the nanowires 51, and improve the service life of the array substrate.
  • the array substrate further includes a passivation layer 11 and a third electrode 23.
  • the passivation layer 11 covers the insulating layer 2 and the exposed surface of the nanowire 51; the third electrode 23 is disposed on the passivation layer 11 facing away from the substrate. 1 surface. Since the third electrode is disposed on the top of the array substrate, that is, the gate electrode is on the top of the passivation layer, the array substrate may be called a top-gate structure transistor.
  • the width of the guide trench is determined based on the induction particles of a specified particle size, so that the width direction of the guide trench can only accommodate one particle of induction particles to avoid the particle size of the induction particles being too large.
  • the two sidewalls of the guide trench are used to limit the growth of nanowires and reduce the line width of the nanowires, thereby reducing the area of the active area of a single array substrate, improving the resolution of the array substrate, and reducing hot carriers.
  • the phenomenon of excessive leakage current caused by the effect and the short channel effect reduces the power consumption of the transistor and thereby reduces the power consumption of the backplane.
  • Step S1101 prepare an insulating layer 2 on the substrate 1, then prepare a catalytic layer 6 on the surface of the insulating layer 2 facing away from the substrate 1, and pattern the catalytic layer 6, as shown in Figure 11.
  • the substrate 1 is a glass substrate
  • the material of the insulating layer 2 is silicon nitride (SiNx)
  • the thickness of the insulating layer 2 is 3000 angstroms
  • the insulating layer 2 can be obtained on the substrate 1 through a deposition process.
  • the material of the catalytic layer 6 is indium tin oxide
  • the thickness of the catalytic layer 6 is 150-400 angstroms.
  • the catalytic layer 6 can be obtained on the surface facing away from the substrate 1 through a deposition process, and the catalytic layer 6 can be patterned through a coating, exposure, and development process.
  • indium tin oxide is opposite the active region.
  • Step S1102 prepare the trench layer 4, and use EBL technology to form guide trenches 41 through the thickness of the trench layer 4, so that the bottom of the guide trench 41 exposes the catalytic layer, as shown in Figure 12 .
  • the spacing between the guide trenches in the activation region 71 is larger, and the spacing between the guide trenches in the growth region 72 is smaller.
  • the pitch of the guide trenches in the active region 71 is 0.2-2 ⁇ m, and the pitch of the guide trenches in the growth region 72 is 50-500 nm.
  • the width of the guide trench 41 is determined based on the width of the nanowire. After the width of the guide trench 41 is determined, the diameter of the induced particles can be determined and the width of the nanowire can be determined.
  • the width of the guide trench in the first growth region 43 is 60-80 nm
  • the width of the guide trench in the second growth region 44 is 20-30 nm. That is, the width of the guide trench in the first growth region 43 is 60-80 nm.
  • the guide trench, the guide trench of the second growth region 44 is a narrow trench.
  • the first growth area 43 corresponds to the DTFT (DISCRETE-TIME FOURIER TRANSFORM, discrete time Fourier transform) area
  • the second growth area 44 corresponds to the STFT (SHORT-TIME FOURIER TRANSFORM, short-time Fourier transform) area.
  • FIG. 13 is a cross-sectional view along line A-A' in FIG. 12 in an embodiment of the present disclosure. As shown in FIG. 13 , the depths of the guide trenches 41 in the first growth area 43 and the guide trenches 41 in the second growth area 44 are the same as the thickness of the trench layer 4 .
  • FIG. 14 is a cross-sectional view along line B-B′ in FIG. 12 in an embodiment of the present disclosure
  • FIG. 15 is a cross-sectional view along line C-C′ in FIG. 12 in an embodiment of the present disclosure. As shown in FIGS. 14 and 15 , the width of the guide trench 41 in the first growth region 43 is larger, and the width of the guide trench 41 in the second growth region 44 is smaller.
  • the bottom of the guide trench is the catalytic layer 6 .
  • Step S1103 process the activation area to obtain induction particles in the guide groove, as shown in Figure 16.
  • the material of the active region is indium tin oxide, and a plasma enhanced chemical vapor deposition process (PECVD) and hydrogen plasma (H Plasma) are used to reduce the indium tin oxide to obtain indium induced particles 52. Since the catalytic layer 6 is located below the trench layer 4, during the reduction process, the indium-induced particles 52 are only generated in the guide trench, and the indium-induced particles 52 are not generated on the surface of the trench layer 4 facing away from the substrate 1. This can avoid the formation of nanowires on the surface of the trench layer 4 facing away from the substrate 1 in the subsequent nanowire preparation process.
  • PECVD plasma enhanced chemical vapor deposition process
  • H Plasma hydrogen plasma
  • step S1103 there are two guide grooves with different widths in the active area.
  • the guide grooves with different widths generate induced particles with different diameters. In the wider guide groove, larger induced particles are formed. In the narrow guide groove, smaller induced particles are formed.
  • the activation area 71 includes a first activation area 71a and a second activation area 71b; the growth area 72 includes a first growth area 72a and a second growth area 72b, and the guide trench of the first growth area 72a is in contact with the first growth area 72a.
  • the guide trenches of the first activation area 71a are connected to each other, and the guide trenches of the second growth area 72b are connected to the guide trenches of the second activation area 71b.
  • the width of the guide trench in the first activation area 71a is greater than the width of the guide trench in the second activation area 72a, and the width of the guide trench in the first growth area 72a is the same as the width of the guide trench in the first activation area 71a.
  • the width of the guide trench in the second growth region 72b is the same as the width of the guide trench in the second activation region 71b.
  • Step S1104 prepare a precipitation layer 7 on the surface of the trench layer 6 facing away from the substrate 1, and process the precipitation layer 7 so that the silicon atoms in the precipitation layer 7 are induced by the induction particles 52 to precipitate along the guide trench to form silicon.
  • Nanowires as shown in Figure 17.
  • amorphous silicon is prepared on the surface of the trench layer facing away from the substrate through a deposition process.
  • the thickness of the amorphous silicon may be 300 to 500 angstroms.
  • the amorphous silicon is annealed at a temperature of 390° C. for 30 to 60 minutes, so that the silicon atoms are precipitated along the guide trench 41 under the guidance of the indium induction particles to form silicon nanowires.
  • the different induction particles are formed on the double side walls of the corresponding guide trenches.
  • nanowires of different widths are formed. For example, nanowires with a wider width, such as nanowires with a width of 60 nm, are formed in the first growth region 43 ; nanowires with a narrower width, such as nanowires with a width of 30 nm, are formed in the second growth region 44 .
  • FIG. 18 is a cross-sectional view along line A-A' in FIG. 17 in an embodiment of the present disclosure.
  • the silicon nanowires formed in the guide trenches 41 of the first growth region 43 have a larger line width
  • the silicon nanowires formed in the guide trenches 41 of the second growth region 44 have a larger line width.
  • FIG. 19 is a cross-sectional view along line B-B′ in FIG. 17 in an embodiment of the present disclosure
  • FIG. 20 is a cross-sectional view along line C-C′ in FIG. 17 in an embodiment of the present disclosure. As shown in FIGS.
  • the nanowires in the guide trench 41 of the first growth area 43 are in close contact with the two sidewalls of the guide trench 41 of the first growth area 43 , and the guide trench 44 of the second growth area The nanowires in 41 are in close contact with the two side walls of the guide trench 41 in the second growth region 44 .
  • Step S1105 remove the residue of the precipitation layer and the induced particles outside the nanowires, then sequentially prepare a sacrificial layer and a transition layer on the surface of the trench layer facing away from the substrate, and then pattern the sacrificial layer and transition layer, as shown in Figure 21 shown.
  • step S1105 the residue of the deposition layer is etched using a plasma enhanced chemical vapor deposition process and using hydrogen plasma. Remove excess indium induced particles through indium tin oxide etching solution.
  • a sacrificial layer 8 and a transition layer 9 are sequentially prepared on the surface of the trench layer 4 facing away from the substrate 1 through a deposition process.
  • the material of the sacrificial layer 8 can be amorphous silicon, and the thickness can be 300 to 500 angstroms.
  • the material of the transition layer 9 can be N + amorphous silicon, and the thickness of the transition layer is 500-1000A.
  • the sacrificial layer 8 and the transition layer 9 are patterned using the same mask process to obtain the first transition electrode 91 and the second transition electrode 92 on the transition layer 9 .
  • the transition layer 9 serves as a transition layer between the electrodes of the thin film transistor and the nanowires, which can reduce the contact resistance, thereby improving the characteristics of the thin film transistor.
  • Step S1106 Prepare a first electrode layer on the surface of the transition layer facing away from the substrate, and pattern the first electrode layer, as shown in Figure 22.
  • step S1106 the first electrode layer 10 is prepared on the surface of the transition layer 9 facing away from the substrate 1, and then the first electrode layer 10 is patterned, and the first electrode 21 and the second electrode 22 are obtained on the first electrode layer 10. .
  • the material of the first electrode layer 10 includes at least any one of conductive metals such as molybdenum, copper, and aluminum, and the thickness of the first electrode layer is 2200 angstroms.
  • Step S1107 deposit a passivation layer, prepare a second electrode layer on the surface of the passivation layer facing away from the substrate, and pattern the second electrode layer to obtain a third electrode, as shown in Figure 9.
  • the material of the passivation layer 11 includes but is not limited to silicon oxide (SiOx) and silicon nitride (SiNx).
  • the passivation layer 11 covers the nanowire, the first transition electrode, the second transition electrode, the first electrode and The exposed surface of the second electrode is used to protect the exposed surfaces of the nanowire, the first transition electrode, the second transition electrode, the first electrode and the second electrode to improve the life of the thin film transistor.
  • the thickness of the passivation layer 11 may be 800 angstroms or 400 angstroms.
  • the material of the second electrode layer includes conductive metals such as molybdenum, copper, and aluminum, and the thickness may be 3100 angstroms.
  • the third electrode serves as the gate electrode of the thin film transistor.

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Abstract

本公开提供一种纳米线、阵列基板制备方法、阵列基板及电子设备，属于半导体技术领域，可解决有源区面积较大问题。纳米线制备方法包括：在衬底的第一表面制备绝缘层；在绝缘层背离衬底的表面形成具有引导沟槽的沟槽层；引导沟槽的宽度是指定粒径的诱导颗粒的粒径的0.8～1.2倍；在引导沟槽内制备诱导颗粒；在沟槽层背离衬底的表面制备析出层；对析出层进行处理，使析出层内的指定原子在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线。

Description

纳米线、阵列基板制备方法、阵列基板及电子设备 技术领域
本公开属于半导体技术领域，具体涉及一种纳米线、阵列基板制备方法、阵列基板及电子设备。
背景技术
硅纳米线在微纳电子设备、光电器件、化学及生物传感器件、能量转化及存储器件等领域有着广阔的应用前景。硅纳米线是一维纳米结构，具有显著的量子效应、超大的比表面积等特性，使得基于硅纳米线的场效应晶体管(MOS)器件具有良好的栅控能力和电流特性。平面固-液-固(IP-SLS)生长技术是一种金属催化生长纳米线的技术，通过该技术形成的硅基纳米线具有类单晶的特性，与显示面板产线具有较高兼容性，可作为未来产线升级的潜在应用技术。
发明内容
本公开旨在提供一种纳米线、阵列基板制备方法、阵列基板及电子设备。
第一方面，本公开提供一种纳米线制备方法，其包括：
在衬底的第一表面制备绝缘层；
在所述绝缘层背离所述衬底的表面形成具有引导沟槽的沟槽层；所述引导沟槽的宽度是指定粒径的诱导颗粒的粒径的0.8～1.2倍；
在所述引导沟槽内制备诱导颗粒；
在所述沟槽层背离所述衬底的表面制备析出层；
对所述析出层进行处理，使所述析出层内的指定原子在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成纳米线。
其中，所述在所述绝缘层背离所述衬底的表面形成具有引导沟槽的沟槽层，包括：
在所述绝缘层背离所述衬底的表面形成沟槽介质层；
利用电子束光刻技术对所述沟槽介质层进行处理，形成具有引导沟槽的沟槽层。
其中，所述沟槽层包括激活区和生长区，所述激活区的引导沟槽的间距大于所述生长区的引导沟槽的间距，所述激活区的引导沟槽通过过渡沟槽与所述生长区的引导沟槽对应连接。
其中，位于所述激活区的所述引导沟槽的间距为0.2～2μm；位于所述生长区的所述引导沟槽的间距为50～500nm。
其中，所述激活区包括第一激活区和第二激活区；所述生长区包括第一生长区和第二生长区，所述第一生长区的引导沟槽与所述第一激活区的引导沟槽连通，所述第二生长区的引导沟槽与所述第二激活区的引导沟槽连通。
其中，所述第一激活区的引导沟槽的宽度大于第一激活区的引导沟槽的宽度，所述第一生长区的引导沟槽的宽度与所述第一激活区的引导沟槽的宽度相同，所述第二生长区的引导沟槽的宽度与所述第二激活区的引导沟槽的宽度相同。
其中，所述激活区和所述生长区的引导沟槽通过一次工艺形成；
所述第一激活区和所述第二激活区的引导沟槽内的诱导颗粒通过一次工艺形成；
在所述第一生长区和所述第二生长区的纳米线通过一次工艺形成。
其中，所述析出层的材料包括非晶硅；
所述对所述析出层进行处理，使所述析出层内的指定原子在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成纳米线，包括：
对所述析出层进行退火处理，使所述析出层内的硅原子在所述诱导颗粒 的诱导下沿所述引导沟槽析出，形成硅纳米线。
其中，所述对所述析出层进行处理，使所述析出层内的指定原子在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成纳米线之后，包括：
通过等离子体增强化学气相沉积工艺并采用氢等离子体刻蚀所述析出层的残留物；
通过刻蚀液去除所述纳米线之外的所述诱导颗粒。
第二方面，本公开实施例还提供一种阵列基板制备方法，其包括形成纳米线，所述纳米线的制备方法包括本公开实施例提供的所述的方法。
其中，所述对所述析出层进行处理，使所述析出层内的指定原子在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成纳米线之后，还包括：
在所述沟槽层背离所述衬底的表面制备牺牲层；
在所述牺牲层背离所述衬底的表面制备过渡层；
对所述过渡层进行图形化，并在所述过渡层形成第一过渡电极和第二过渡电极。
其中，所述对所述过渡层进行图形化之后，还包括：
在所述过渡层背离所述衬底的表面制备第一电极层；
对所述第一电极层进行图形化，获得第一电极和第二电极，所述第一电极叠置于所述第一过渡电极，所述第二电极叠置于所述第二过渡电极；
沉积钝化层，所述钝化层覆盖所述纳米线、所述第一过渡电极、所述第二过渡电极、所述第一电极和所述第二电极的裸露表面。
其中，所述衬底包括玻璃衬底和硅衬底中的一种。
第三方面，本公开还提供一种阵列基板，其包括：
衬底，所述衬底包括第一表面；
绝缘层，所述绝缘层设置于所述衬底的第一表面；
沟槽层，所述沟槽层设置于所述绝缘层背离所述衬底的表面，所述沟槽 层设置有引导沟槽，所述引导沟槽的宽度是50～250nm；
纳米线层，所述纳米线层设置于所述绝缘层背离所述衬底的表面，所述纳米线层设置有纳米线，所述纳米线嵌置于所述引导沟槽内。
其中，所述沟槽层包括激活区和生长区，所述激活区的引导沟槽的间距大于所述生长区的引导沟槽的间距，所述激活区的引导沟槽通过过渡沟槽与所述生长区的引导沟槽对应连接。
其中，位于所述激活区的所述引导沟槽的间距为0.2～2μm；位于所述生长区的所述引导沟槽的间距为50～500nm。
其中，所述激活区包括第一激活区和第二激活区；所述生长区包括第一生长区和第二生长区，所述第一生长区的引导沟槽与所述第一激活区的引导沟槽连通，所述第二生长区的引导沟槽与所述第二激活区的引导沟槽连通。
其中，所述第一激活区的引导沟槽的宽度大于第一激活区的引导沟槽的宽度，所述第一生长区的引导沟槽的宽度与所述第一激活区的引导沟槽的宽度相同，所述第二生长区的引导沟槽的宽度与所述第二激活区的引导沟槽的宽度相同。
其中，所述纳米线层包括多组纳米线组，每组所述纳米线组包括多条间隔设置的纳米线；所述激活区对应的所述纳米线组中的纳米线的间距为0.2～2μm，所述生长区对应的纳米线组中的纳米线的间距为50～500nm。
其中，所述第一激活区和所述第一生长区对应的纳米线组中的纳米线的线宽为60～80nm，所述第二激活区和所述第二生长区对应的纳米线组中的纳米线的线宽为20～30nm。
其中，阵列基板还包括：第一电极层，所述第一电极层叠置于所述纳米线层背离所述衬底的表面，且设置于所述第一电极层的第一电极与所述纳米线的源极区域电连接，设置于所述第一电极层的第二电极与所述纳米线的漏极区域电连接。
其中，阵列基板还包括：过渡层，所述过渡层设置于所述纳米线层背离所述衬底的表面，且设置于所述过渡层的第一过渡电极叠置于所述第一电极与所述纳米线的源极区域之间，设置于所述过渡层的第二过渡电极叠置于所述第二电极与所述纳米线的漏极区域之间。
其中，阵列基板还包括：第三电极，所述第三电极设置于所述衬底和所述绝缘层之间。
其中，阵列基板还包括钝化层，所述钝化层覆盖所述沟槽层、所述纳米线层和所述第一电极层的裸露表面。
其中，还包括钝化层和第三电极，所述钝化层覆盖所述绝缘层和所述纳米线的裸露表面；
所述第三电极设置于所述钝化层背离所述衬底的表面。
第四方面，本公开实施例提供一种电子设备，其包括本公开实施例提供的所述的阵列基板。
附图说明
图1为利用IP-SLS技术生长纳米线的原理图；
图2为本公开实施例提供的一种纳米线制备方法的流程图；
图3为本公开实施例中引导沟槽双侧边限制生长原理图；
图4为本公开实施例中引导沟槽单侧边限制生长原理图；
图5为本公开实施例中形成引导沟槽后的结构示意图；
图6为本公开实施例中一种引导沟槽的示意图；
图7为本公开实施例中另一种引导沟槽的示意图；
图8为本公开实施例提供的一种阵列基板制备方法的流程图；
图9为本公开实施例提供的一种阵列基板的结构示意图；
图10为本公开实施例提供的一种阵列基板的部分结构示意图；
图11为本公开实施例中步骤S1101后的结构示意图；
图12为本公开实施例中步骤S1102后的结构示意图；
图13为本公开实施例中沿图12中的A-A′线的截面图；
图14为本公开实施例中沿图12中的B-B′线的截面图；
图15为本公开实施例中沿图12中的C-C′线的截面图；
图16为本公开实施例中步骤S1103后的结构示意图；
图17为本公开实施例中步骤S1104后的结构示意图；
图18为本公开实施例中沿图17中的A-A′线的截面图；
图19为本公开实施例中沿图17中的B-B′线的截面图；
图20为本公开实施例中沿图17中的C-C′线的截面图；
图21为本公开实施例中步骤S1105后的结构示意图；
图22为本公开实施例中步骤S1106后的结构示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、 “下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开实施例提供的纳米线制备方法是在IP-SLS技术基础上提出的。图1为利用IP-SLS技术生长纳米线的原理图。如图1所示，纳米线生长的原理包括以下步骤：
步骤S11，在衬底1表面制备的绝缘层2，在绝缘层2背离衬底1的表面制备催化层，金属颗粒经过原位处理形成纳米颗粒81，如图1(a)所示。
步骤S12，在衬底1的表面沉积前驱体层80，然后加热衬底，在三相界面处形成合金液滴82，如铟合金液滴，如图1(b)所示。
步骤S13，合金液滴界面吸收的预定原子向合金液滴-纳米线界面输送，析出籽晶83，如图1(c)所示。
步骤S14，在吉布斯自由能驱使下，颗粒最大的籽晶翘动合金液滴向相反方向运动，形成新的吸收界面，最终获得纳米线84。
在制备阵列基板时，为了在指定区域获得纳米线，在制备纳米线之前制备沟槽层，并在沟槽层制备引导沟槽，纳米线在引导沟槽形成。引导沟槽的宽度影响纳米线的宽度，从而影响阵列基板的开态电流和漏电流，也影响有源区的面积。
本公开实施例提供一种纳米线制备方法，该方法基于指定粒径的诱导颗粒确定引导沟槽，从而在引导沟槽内获得指定粒径的诱导颗粒，利用引导沟槽的宽度限定纳米线的宽度，以获得超细纳米线。
图2为本公开实施例提供的一种纳米线制备方法的流程图。如图2所示，纳米线制备方法包括：
步骤S201，在衬底的第一表面制备绝缘层。
其中，衬底包括但不限于玻璃衬底和硅衬底，本公开对衬底的材料不作限定。衬底包括相对设置的第一表面和第二表面，第一表面和第二表面均可用于承载薄膜晶体管。为便于描述，本公开实施例以第一表面为例进行说明。
在一些实施例中，绝缘层的材料可以为氮化硅(SiNx)、氧化硅(SiOx)等硅化物，或者为聚酰亚胺、亚克力等有机材料。
在一些实施例中，绝缘层可以通过沉积工艺制备，如物理气相沉积或化学气相沉积工艺。本公开实施例对绝缘层的厚度不作限定，如，绝缘层的厚度为3000埃。
步骤S202，在绝缘层背离衬底的表面形成具有引导沟槽的沟槽层。
其中，引导沟槽的宽度是指定粒径的诱导颗粒的粒径的0.8～1.2倍，以使得每个引导沟槽在宽度方向仅能容纳一个指定粒径的诱导颗粒。在诱导颗粒诱导下形成纳米线的过程中，纳米线受引导沟槽的约束，形成与指定粒径的诱导颗粒的尺寸一致的纳米线。
在一些实施例中，步骤S202，在绝缘层背离衬底的表面形成具有引导沟槽的沟槽层，包括：在绝缘层背离衬底的表面形成沟槽介质层；利用电子束光刻技术对沟槽介质层进行处理，形成具有引导沟槽的沟槽层。
其中，沟槽介质层的材料可以为氮化硅(SiNx)、氧化硅(SiOx)等硅化物，或者为聚酰亚胺、亚克力等有机材料。沟槽介质层的厚度可以为1000-1500埃，如沟槽层的厚度1200埃。
通过电子束光刻(E-Beam Lithography，简称EBL)技术，对沟槽介质层进行图形化，从而形成具有引导沟槽的沟槽层。其中，EBL技术可以获得超细引导沟槽，如可以获得0.5微米以下的引导沟槽，如获得20纳米的引导沟槽。引导沟槽的宽度越小，可以使后续形成的纳米线的排列越紧密，减少单个阵列基板的有源区面积，从而提高阵列基板的分辨率。
在一些实施例中，沟槽层设置多个引导沟槽，多个引导沟槽间隔设置，相邻的引导沟槽之间的间距可以根据需要设定，本公开实施例对相邻的引导沟槽之间的间距不作限定。
在一些实施例中，多个引导沟槽的宽度可以全部相同，也可以部分相同，也可以根据需求设置多个分组，每组中的引导沟槽的宽度不同。
步骤S203，在引导沟槽内制备诱导颗粒。
其中，诱导颗粒制备纳米线的原理可以参阅图1及对应部分的描述。
在一些实施例中，诱导颗粒可以硅诱导颗粒，通过还原铟锡氧化物获得。铟诱导颗粒也可以采用其他方式获得。诱导颗粒也可以是其他元素，只要能够促进纳米线生成的元素均可作为诱导颗粒。
在一些实施例中，催化层的材料包括铟锡氧化物，诱导颗粒包括铟颗粒；利用等离子体增强化学气相沉积(PECVD)工艺并采用氢等离子体对铟锡氧化物进行还原处理，获得诱导颗粒。
步骤S204，在沟槽层背离衬底的表面制备析出层。
其中，析出层是为了生成纳米线，在诱导颗粒的催化作用下，构成纳米线的材料从吸出层析出。
在一些实施例中，析出层可以通过沉积工艺制备，如物理气相沉积或化学气相沉积工艺。析出层的厚度可以为300-500埃，如析出层的厚度400埃。
在一些实施例中，析出层的材料可以根据纳米线的材料确定，例如，析出层的材料为非晶硅。
步骤S205，对析出层进行处理，使析出层内指定原子在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线。
在一些实施例中，通过退火等工艺使析出层内的指定原子在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线。
需要说明的是，纳米线的宽度取决于诱导颗粒的粒径(直径)，通过控制引导沟槽的宽度，可以控制诱导颗粒的粒径，从而精确控制纳米线的宽度。对于大直径的纳米线，其载流子的迁移率较高，而直径较细的纳米线，其载流子的迁移率较低，因此，通过精确控制纳米线的宽度，可以精确控制不同载流子的迁移率。
当引导沟槽41的宽度较宽时，如引导沟槽41的宽度超过诱导颗粒52的粒径时，纳米线会沿着引导沟槽41的单侧壁生长，如图3所示。当引导沟 槽41的宽度较窄时，利用引导沟槽41的宽度限制诱导颗粒52的粒径，纳米线会沿着引导沟槽的双侧壁生长，如图4所示。利用双侧壁限制诱导颗粒的粒径，从而可以限制纳米线的宽度。因此，根据所需的纳米线直径确定引导沟槽的宽度，可以在制备纳米线时获得所需直径的纳米线。
本公开实施例提供的纳米线制备方法，在对沟槽层进行图形化时，基于指定粒径的诱导颗粒确定引导沟槽的宽度，以在引导沟槽内获得指定粒径的诱导颗粒，利用引导沟槽的宽度限定纳米线的宽度，以获得超细的纳米线，可以获得密排的纳米线，减少单个阵列基板有源区的面积，提高分辨率，而且控制薄膜晶体管的开态电流和漏电流，提高阵列基板的性能。
在一些实施例中，步骤S203，在引导沟槽内制备诱导颗粒，包括：在预设位置制备催化层；对催化层进行处理，在引导沟槽内获得诱导颗粒。
在本公开实施例中，利用催化层生成诱导颗粒，催化层的材料包括但不限于铟锡氧化物(ITO)。
在一些实施例中，在预设位置制备催化层，包括：在绝缘层与沟槽层之间制备催化层。
预设位置为绝缘层与沟槽层之间，即催化层设置在沟槽层的下方，在制备绝缘层后，在绝缘层背离衬底的表面制备催化层。催化层覆盖绝缘层的区域可以根据需要设定。
本公开实施例将催化层设置在沟槽层的下层，催化层被沟槽层覆盖的区域无法生长诱导颗粒，因此，仅能在引导沟槽内生成诱导颗粒，而在沟槽层背离衬底的表面不会生成，可以避免后续工艺中在沟槽层背离衬底的表面生成无序的纳米线，从而提高了纳米线的良率。
在一些实施例中，如图5所示，沟槽层4包括激活区71和生长区72，激活区71与催化层6的位置相对应，激活区71的引导沟槽41与生长区72的引导沟槽41的间距不同，激活区71的引导沟槽41通过过渡沟槽42与生长区72的引导沟槽41对应连接。
在一些实施例中，位于激活区71的引导沟槽41的间距大于位于生长区72的引导沟槽41的间距，位于激活区71的引导沟槽41的数量和位于生长区72的引导沟槽41数量一致，每条引导沟槽14通过过渡沟槽42从激活区71向生长区72延伸。
本公开实施例提供的生长区的引导沟槽的间距小于激活区的引导沟槽的间距，可以减小生长区的面积，从而减少有源层的面积，进而提高阵列基板的分辨率。
在一些实施例中，位于激活区的引导沟槽的间距为0.2～2μm；位于生长区的引导沟槽的间距为50～500nm。
在一些实施例中，由于激活区71的引导沟槽41的间距与生长区72的引导沟槽41的间距不同，过渡沟槽42在绝缘层2背离衬底1的表面投影的形状可以弧线、直线中的任意一种。
图6为本公开实施例中一种引导沟槽的示意图。如图6所示，过渡沟槽42的形状为弧线，即激活区71的引导沟槽41通过弧形的过渡沟槽42与生长区72的引导沟槽41连通。
图7为本公开实施例中另一种引导沟槽的示意图。如图7所示，过渡沟槽42的形状为直线，即激活区71的引导沟槽41通过直线型的过渡沟槽42与生长区72的引导沟槽41连通。
如图5所示，激活区71包括第一激活区71a和第二激活区71b；生长区72包括第一生长区72a和第二生长区72b，第一生长区71a的引导沟槽与第一激活区71a的引导沟槽连通，第二生长区72b的引导沟槽与第二激活区72b的引导沟槽连通。
在一些实施例中，第一生长区72a和第二生长区72b分别位于激活区71的两侧，激活区71的引导沟槽向第一生长区72a和第二生长区72b延伸，并与第一生长区72a和第二生长区72b的引导沟槽连通。
在一些实施例中，第一激活区71a的引导沟槽的宽度大于第二激活区71b 的引导沟槽的宽度，第一生长区72a的引导沟槽的宽度与第一激活区71a的引导沟槽的宽度相同，第二生长区72b的引导沟槽的宽度与第二激活区71b的引导沟槽的宽度相同。
在一些实施例中，第一生长区72a的引导沟槽41的宽度与第二生长区72b的引导沟槽41的宽度不同。在一些实施例中，第一激活区71a和第一生长区72a的引导沟槽41的宽度为60～80nm，第二激活区71b和第二生长区72b的引导沟槽41的宽度为20～30nm。
在一些实施例中，激活区71和生长区72的引导沟槽通过一次工艺形成，即通过一次掩膜工艺对沟槽层进行处理，在激活区71和生长区72形成对应的引导沟槽。通过一次工艺在激活区71和生长区72形成引导沟槽可以降低阵列基板的制备成本。
在一些实施例中，第一激活区71a和第二激活区71b的引导沟槽内的诱导颗粒通过一次工艺形成，即在还原催化层时，在第一激活区71a的引导沟槽和第二激活区71b的引导沟槽同时形成诱导颗粒。由于第一激活区71a的引导沟槽的宽度大于第二激活区71b的引导沟槽的宽度，在第一激活区71a析出的诱导颗粒的尺寸大于第二激活区71b析出的诱导颗粒的尺寸。
在一些实施例中，析出层的材料包括非晶硅(a-Si)或者其它合适的材料。
步骤S205，对析出层进行处理，使析出层内的指定原子在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线，包括：对析出层进行退火处理，使析出层内的硅原子在诱导颗粒的诱导下沿引导沟槽析出，形成硅纳米线。
在一些实施例中，对析出层进行退火处理时，退火的温度可以是350～400℃，退火的时间可以是30～60min。在退火过程中，析出层内的硅原子在诱导颗粒的诱导下沿引导沟槽析出，并由非晶体转化为晶体，从而形成硅纳米线。
在一些实施例中，在第一生长区72a和第二生长区72b的纳米线通过一 次工艺形成，即对析出层进行退火处理，在第一生长区72a和第二生长区72b同时生成纳米线。
在一些实施例中，步骤S205，对析出层进行处理，使析出层内的指定原子在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线之后，包括：去除析出层的残留物和纳米线之外的诱导颗粒。
将析出层的残留物和纳米线之外的诱导颗粒去除，可以避免析出层的残留物和诱导颗粒对第一电极层与纳米线搭接的影响，改善电极与纳米线的搭接性能，提高纳米线的迁移率。
在一些实施例中，通过等离子体增强化学气相沉积工艺并采用氢等离子体刻蚀析出层的残留物，通过ITO刻蚀液去除多余的铟颗粒。
本公开实施例提供的纳米线制备方法，在对沟槽层进行图形化时，引导沟槽的宽度基于指定粒径的诱导颗粒确定，使得引导沟槽的宽度方向仅能容纳一粒诱导颗粒，而且可以限制该诱导颗粒的粒径，避免诱导颗粒的粒径过大，同时，利用引导沟槽的两个侧壁限制纳米线的生长，减小纳米线的线宽，从而减小单个薄膜晶体管有源区的面积，提高薄膜晶体管的分辨率，而且，可以降低热载流子效应和短沟道效应引起的漏电流过大的现象，从而降低晶体管的功耗，进而降低背板的功耗。
本公开实施例提供一种阵列基板制备方法，该方法基于指定粒径的诱导颗粒确定引导沟槽，从而在引导沟槽内获得指定粒径的诱导颗粒，以及利用引导沟槽的宽度限定纳米线的宽度，从而获得超细纳米线。
图8为本公开实施例提供的一种阵列基板制备方法的流程图。如图8所示，本公开实施例提供的阵列基板制备方法包括：
步骤S801，在衬底的第一表面制备绝缘层。
其中，衬底包括但不限于玻璃衬底和硅衬底，本公开对衬底的材料不作限定。衬底包括相对设置的第一表面和第二表面，第一表面和第二表面均可用于承载阵列基板。为便于描述，本公开实施例以第一表面为例进行说明。
在一些实施例中，绝缘层的材料可以为氮化硅(SiNx)、氧化硅(SiOx)等硅化物，或者为聚酰亚胺、亚克力等有机材料。
在一些实施例中，绝缘层可以通过沉积工艺制备，如物理气相沉积或化学气相沉积工艺。本公开实施例对绝缘层的厚度不作限定，如，绝缘层的厚度为3000埃。
步骤S802，在绝缘层背离衬底的表面形成具有引导沟槽的沟槽层。
其中，引导沟槽的宽度是指定粒径的诱导颗粒的粒径的0.8～1.2倍，以使得每个引导沟槽在宽度方向仅能容纳一个指定粒径的诱导颗粒。在诱导颗粒诱导下形成纳米线的过程中，纳米线受引导沟槽的约束，形成与指定粒径的诱导颗粒的尺寸一致的纳米线。
在一些实施例中，步骤S802，在绝缘层背离衬底的表面形成具有引导沟槽的沟槽层，包括：在绝缘层背离衬底的表面形成沟槽介质层；利用电子束光刻技术对沟槽介质层进行处理，形成具有引导沟槽的沟槽层。
其中，沟槽介质层的材料可以为氮化硅(SiNx)、氧化硅(SiOx)等硅化物，或者为聚酰亚胺、亚克力等有机材料。沟槽介质层的厚度可以为1000-1500埃，如沟槽层的厚度1200埃。
在一些实施例中，通过电子束光刻(E-Beam Lithography，简称EBL)技术，对沟槽介质层进行图形化，从而形成具有引导沟槽的沟槽层。其中，EBL技术可以获得超细引导沟槽，如可以获得0.5微米以下的引导沟槽，如获得20纳米的引导沟槽。引导沟槽的宽度越小，可以使后续形成的纳米线的排列越紧密，减少单个阵列基板的有源区面积，从而提高阵列基板的分辨率。
在一些实施例中，对沟槽介质层进行图形化，并在沟槽介质层获得多个引导沟槽，多个引导沟槽可以间隔设置，相邻的引导沟槽之间的间距可以根据需要设定，本公开实施例对相邻的引导沟槽之间的间距不作限定。
在一些实施例中，多个引导沟槽的宽度可以全部相同，也可以部分相同，也可以根据需求设置多个分组，每组中的引导沟槽的宽度不同。
步骤S803，在引导沟槽内制备诱导颗粒。
在一些实施例中，步骤S803，在引导沟槽内制备诱导颗粒，包括：在预设位置制备催化层；对催化层进行处理，以在引导沟槽内获得诱导颗粒。
在本公开实施例中，利用催化层生成诱导颗粒，催化层的材料包括但不限于铟锡氧化物(ITO)。
在一些实施例中，预设位置可以为绝缘层与沟槽层之间，在预设位置制备催化层，包括：在绝缘层与沟槽层之间制备催化层，即催化层设置在沟槽层的下方，在制备绝缘层后，在绝缘层背离衬底的表面制备催化层。催化层覆盖绝缘层的区域可以根据需要设定。
本公开实施例将催化层设置在沟槽层的下层，催化层被沟槽层覆盖的区域无法生长诱导颗粒，因此，仅能在引导沟槽内生成诱导颗粒，而在沟槽层背离衬底的表面不会生成，可以避免后续工艺中在沟槽层背离衬底的表面生成无序的纳米线，从而提高了纳米线的良率。
在一些实施例中，催化层的材料包括铟锡氧化物，诱导颗粒包括铟颗粒；利用等离子体增强化学气相沉积(PECVD)工艺并采用氢等离子体对铟锡氧化物进行还原处理，获得诱导颗粒。
步骤S804，在沟槽层背离衬底的表面制备析出层。
其中，析出层是为了生成纳米线，在诱导颗粒的催化作用下，构成纳米线的材料从吸出层析出。
在一些实施例中，析出层可以通过沉积工艺制备，如物理气相沉积或化学气相沉积工艺。析出层的厚度可以为300-500埃，如析出层的厚度400埃。
在一些实施例中，析出层的材料可以根据纳米线的材料确定，例如，析出层的材料为非晶硅。
在一些实施例中，如图5所示，析出层7包括激活区71和生长区72，激活区71与催化层6的位置相对应，激活区71的引导沟槽41与生长区72的引导沟槽41的间距不同，激活区71的引导沟槽41通过过渡沟槽42与生 长区72的引导沟槽41对应连接。
在一些实施例中，位于激活区71的引导沟槽41的间距大于位于生长区72的引导沟槽41的间距，位于激活区71的引导沟槽41的数量和位于生长区72的引导沟槽41数量一致，每条引导沟槽14通过过渡沟槽42从激活区71向生长区72延伸。
在一些实施例中，位于激活区的引导沟槽的间距为0.2～2μm；位于生长区的引导沟槽的间距为50～500nm。
在一些实施例中，由于激活区71的引导沟槽41的间距与生长区72的引导沟槽41的间距不同，过渡沟槽42在绝缘层2背离衬底1的表面投影的形状可以弧线、直线中的任意一种。
如图5所示，激活区71包括第一激活区71a和第二激活区71b；生长区72包括第一生长区72a和第二生长区72b，第一生长区71a的引导沟槽与第一激活区71a的引导沟槽连通，第二生长区72b的引导沟槽与第二激活区72b的引导沟槽连通。
在一些实施例中，生长区72包括第一生长区72a和第二生长区72b，第一生长区72a和第二生长区72b分别位于激活区71的两侧，激活区71的引导沟槽向第一生长区72a和第二生长区72b延伸，并与第一生长区72a和第二生长区72b的引导沟槽连通。
在一些实施例中，第一激活区71a的引导沟槽的宽度大于第二激活区71b的引导沟槽的宽度，第一生长区72a的引导沟槽的宽度与第一激活区71a的引导沟槽的宽度相同，第二生长区72b的引导沟槽的宽度与第二激活区71b的引导沟槽的宽度相同。
在一些实施例中，第一生长区72a的引导沟槽41的宽度与第二生长区72b的引导沟槽41的宽度不同。在一些实施例中，第一激活区71a和第一生长区72a的引导沟槽41的宽度为60～80nm，第二激活区71b和第二生长区72b的引导沟槽41的宽度为20～30nm。
在一些实施例中，激活区71和生长区72的引导沟槽通过一次工艺形成，即通过一次掩膜工艺对沟槽层进行处理，在激活区71和生长区72形成对应的引导沟槽。通过一次工艺在激活区71和生长区72形成引导沟槽可以降低阵列基板的制备成本。
在一些实施例中，第一激活区71a和第二激活区71b的引导沟槽内的诱导颗粒通过一次工艺形成，即在还原催化层时，在第一激活区71a的引导沟槽和第二激活区71b的引导沟槽同时形成诱导颗粒。由于第一激活区71a的引导沟槽的宽度大于第二激活区71b的引导沟槽的宽度，在第一激活区71a析出的诱导颗粒的尺寸大于第二激活区71b析出的诱导颗粒的尺寸。
在一些实施例中，析出层的材料包括非晶硅(a-Si)或者其它合适的材料。
步骤S805，对析出层进行处理，使析出层内的指定原子在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线。
在一些实施例中，通过退火等工艺使析出层内的指定原子在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线。纳米线可以作为晶体管的有源层，用于导电通道。纳米线的宽度取决于诱导颗粒的粒径(直径)，通过控制引导沟槽的宽度，可以控制诱导颗粒的粒径，从而精确控制纳米线的宽度。对于大直径的纳米线，其载流子的迁移率较高，而直径较细的纳米线，其载流子的迁移率较低，因此，通过精确控制纳米线的宽度，可以精确控制不同载流子的迁移率。
在一些实施例中，在第一生长区72a和第二生长区72b的纳米线通过一次工艺形成，即对析出层进行退火处理，在第一生长区72a和第二生长区72b同时生成纳米线。
在一些实施例中，步骤S805，对析出层进行处理，使析出层内的指定原子在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线，包括：对析出层进行退火处理，使析出层内的硅原子在诱导颗粒的诱导下沿引导沟槽析出，形成 硅纳米线。
在一些实施例中，对析出层进行退火处理时，退火的温度可以是350～400℃，退火的时间可以是30～60min。在退火过程中，析出层内的硅原子在诱导颗粒的诱导下沿引导沟槽析出，并由非晶体转化为晶体，从而形成硅纳米线。
在一些实施例中，步骤S805，对析出层进行处理，使析出层内的指定原子在诱导颗粒的诱导下沿引导沟槽析出，形成纳米线之后，包括：
步骤S806，去除析出层的残留物和纳米线之外的诱导颗粒。
将析出层的残留物和纳米线之外的诱导颗粒去除，可以避免析出层的残留物和诱导颗粒对第一电极层与纳米线搭接的影响，改善电极与纳米线的搭接性能，提高纳米线的迁移率。
在一些实施例中，通过等离子体增强化学气相沉积工艺并采用氢等离子体刻蚀析出层的残留物，通过ITO刻蚀液去除多余的铟颗粒。
步骤S807，在沟槽层背离衬底的表面的制备牺牲层，在牺牲层背离衬底的表面制备过渡层，对过渡层进行图形化，并在过渡层形成第一过渡电极和第二过渡电极。
在一些实施例中，牺牲层的材料可以是非晶硅，厚度可以为300～500埃。本公开实施例对牺牲层的制备方法不作限定，例如牺牲层可以通过沉积工艺制备。
在一些实施例中，过渡层的材料可以是N +非晶硅，过渡层的厚度为500～1000A。本公开实施例对过渡层的制备方法不作限定，例如过渡层可以通过沉积工艺制备。
在本公开实施例中，由于牺牲层设置于过渡层与纳米线之间，在对过渡层进行图形化时，可以避免损伤纳米线而导致漏电流降低的问题。
在一些实施例中，步骤S807，对过渡层进行图形化之后，还包括：
步骤S808，在过渡层背离衬底的表面制备第一电极层；对第一电极层进 行图形化，获得第一电极和第二电极，第一电极叠置于第一过渡电极，第二电极叠置于第二过渡电极。
其中，第一电极层的材料包括钼、铜、铝等导电金属中的至少任意一种，第一电极层的厚度2000埃以上，如第一电极层的厚度为2200埃。本公开实施例对第一电极层的制备方法不作限定，例如，通过物理气相沉积工艺制备第一电极层。
在一些实施例中，通过涂覆、曝光、显影工艺对第一电极层进行图形化，获得第一电极和第二电极。其中，第一电极可以是薄膜晶体管的漏极，第二电极可以是薄膜晶体管的源极；或者，第一电极可以是薄膜晶体管的源极，第二电极可以是薄膜晶体管的漏极。
在本公开实施例中，由于第一电极叠置于第一过渡电极，即在第一电极与纳米线之间设置第一过渡电极，第一过渡电极与纳米线形成欧姆接触，从而降低了第一电极与纳米线的接触电阻，改善了薄膜晶体管的特性。类似地，第二电极叠置于第二过渡电极，即在第二电极与纳米线之间设置第二过渡电极，第二过渡电极与纳米线形成欧姆接触，从而降低了第二电极与纳米线的接触电阻，改善了薄膜晶体管的特性。
在一些实施例中，对第一电极层进行图形化，获得第一电极和第二电极之后，还包括：
步骤S809，沉积钝化层，对钝化层进行图形化，至少将第一电极和第二电极背离衬底的部分表面露出，在钝化层背离衬底表面制备第三电极，其中，钝化层覆盖纳米线、第一过渡电极、第二过渡电极、第一电极和第二电极的裸露表面。
其中，钝化层的材料包括但不限于氧化硅(SiOx)、氮化硅(SiNx)。钝化层的厚度覆盖导电层即可，本公开实施例对钝化层的厚度不作限定，例如，钝化层的厚度可以为800埃或400埃。本公开实施例对钝化层的制备方法不作限定，如，钝化层可以通过沉积等工艺制备。
在一些实施例中，沉积钝化层之后，还包括：
在一些实施例中，可以通过涂覆、曝光、显影工艺对钝化层进行图形化，至少将第一电极和第二电极背离衬底的部分表面露出。
其中，第三电极的材料可以为导电金属，例如钼或铜。本公开实施例对第三电极的厚度不作限定，例如，第三电极的厚度为500埃或2200埃。
在一些实施例中，第三电极可以作为薄膜晶体管的栅极，第一电极、第二电极和第三电极构成晶体管。由于栅极在钝化层的顶部，该薄膜晶体管可以被称为顶栅结构的晶体管。
在一些实施例中，当薄膜晶体管采用底栅结构时，在步骤S801，在衬底的第一表面制备绝缘层之前，还包括：在衬底的第一表面制备晶体管的第三电极，即第三电极设置于衬底和绝缘层之间。此时，钝化层覆盖沟槽层、纳米线层和第一电极层的裸露表面。
其中，第三电极作为晶体管的栅极，第三电极的材料可以为钼、铜等导电金属，第三电极的厚度可以为500埃或2200埃。本公开实施例对第三电极的厚度不作限定。
本公开实施例提供的晶体管制备方法，在对沟槽层进行图形化时，引导沟槽的宽度基于指定粒径的诱导颗粒确定，使得引导沟槽的宽度方向仅能容纳一粒诱导颗粒，而且可以限制该诱导颗粒的粒径，避免诱导颗粒的粒径过大，同时，利用引导沟槽的两个侧壁限制纳米线的生长，减小纳米线的线宽，从而减小单个薄膜晶体管有源区的面积，提高薄膜晶体管的分辨率，而且，可以降低热载流子效应和短沟道效应引起的漏电流过大的现象，从而降低晶体管的功耗，进而降低背板的功耗。
本公开实施例还提供一种阵列基板，该阵列基板的纳米线通过引导沟槽来限制纳米线的宽度，可以获得超细纳米线，从而提高阵列基板的分辨率。
图9为本公开实施例提供的一种阵列基板的结构示意图，图10为本公开实施例提供的一种阵列基板的部分结构示意图。如图9和图10所示，阵列基 板包括：
衬底1，衬底包括第一表面。
其中，衬底包括但不限于玻璃衬底和硅衬底，本公开对衬底的材料不作限定。衬底包括相对设置的第一表面和第二表面，第一表面和第二表面均可以用于承载电子设备的各组成部分。
绝缘层2，绝缘层2设置于衬底1的第一表面。
在一些实施例中，绝缘层2的材料可以为氮化硅、氧化硅等硅化物，或者为聚酰亚胺、亚克力等有机材料，本公开实施例对绝缘层的厚度不作限定。
沟槽层4，沟槽层设置于绝缘层背离衬底的表面，沟槽层设置有引导沟槽，引导沟槽的宽度是50～250nm。
在一些实施例中，沟槽层4包括激活区71和生长区72，所述激活区71的引导沟槽的间距大于所述生长区72的引导沟槽的间距，所述激活区71的引导沟槽通过过渡沟槽42与所述生长区72的引导沟槽对应连接。
在一些实施例中，位于所述激活区的所述引导沟槽的间距为0.2～2μm；位于所述生长区的所述引导沟槽的间距为50～500nm。
在一些实施例中，激活区71包括第一激活区71a和第二激活区71b；所述生长区72包括第一生长区72a和第二生长区72b，所述第一生长区72a的引导沟槽与所述第一激活区71a的引导沟槽连通，所述第二生长区72b的引导沟槽与所述第二激活区71b的引导沟槽连通。
在一些实施例中，所述第一激活区71a的引导沟槽的宽度大于第一激活区71b的引导沟槽的宽度，所述第一生长区72a的引导沟槽的宽度与所述第一激活区71a的引导沟槽的宽度相同，所述第二生长区72b的引导沟槽的宽度与所述第二激活区71b的引导沟槽的宽度相同。
在一些实施例中，沟槽层4的材料包括氧化硅、氮化硅等，沟槽层4的厚度为1000～1500埃。引导沟槽的数量可以根据需要设置一条或多条。
纳米线层5，纳米线层设置于绝缘层2背离衬底1的表面，纳米线层5 设置有纳米线51，纳米线51嵌置于引导沟槽41内。
在一些实施例中，纳米线层5包括多组纳米线组，每组纳米线组包括多条间隔设置的纳米线；激活区对应的纳米线组中的纳米线的间距为0.2～2μm，生长区对应的纳米线组中的纳米线的间距为50～500nm。
在本公开实施例中，第一激活区和第一生长区对应的纳米线组中的纳米线的线宽为60～80nm，第二激活区和第二生长区对应的纳米线组中的纳米线的线宽为20～30nm。
在一些实施例中，阵列基板还包括第一电极层，第一电极层叠置于纳米线层背离衬底的表面，且设置于第一电极层的第一电极与纳米线的源极区域电连接，设置于第一电极层的第二电极与纳米线的漏极区域电连接。
在一些实施例中，第一电极层的材料可以采用导电金属材料，例如，第一电极层4的材料包括钼、铜、铝中的至少一种。其中，第一电极21和第二电极22可以分别作为阵列基板的源极和漏极。
在一些实施例中，阵列基板还包括过渡层，过渡层设置于纳米线层背离衬底的表面，且设置于过渡层的第一过渡电极91叠置于第一电极21与纳米线51的源极区域之间，设置于过渡层的第二过渡电极92叠置于第二电极22与纳米线51的漏极区域之间。
在一些实施例中，第一过渡电极91和第二过渡电极92的材料为N +型非晶硅(N +a-Si)。
在一些实施例中，在第一电极21与纳米线51的源极区域之间设置有第一过渡电极91，在第二电极22与纳米线51的漏极区域之间设置有第二过渡电极92。第一过渡电极91可以改善第一电极21与纳米线51的搭接异常问题，降低金属-半导体接触的接触势垒，增强界面处的隧穿效应，减少阵列基板的大阻值现象。
在一些实施例中，阵列基板还包括：第三电极23，第三电极23设置于衬底和绝缘层之间。
第三电极23可以为作为薄膜晶体管的栅极，第一电极21、第二电极22和第三电极23构成薄膜晶体管。由于第三电极23设置在薄膜晶体管的底部，即栅极设置在薄膜晶体管的底部，因此，该薄膜晶体管可以被称为底栅结构的晶体管。
在一些实施例中，阵列基板还包括钝化层11，钝化层覆盖沟槽层、纳米线层和第一电极层的裸露表面。钝化层11可以对绝缘层2、第一电极层10和纳米线51进行保护，提高阵列基板使用寿命。
在另一些实施例中，阵列基板还包括钝化层11和第三电极23，钝化层11覆盖绝缘层2和纳米线51的裸露表面；第三电极23设置于钝化层11背离衬底1的表面。由于第三电极设置在阵列基板的顶部，即栅极在钝化层的顶部，该阵列基板可以被称为顶栅结构的晶体管。
本公开实施例提供的晶体管，引导沟槽的宽度是基于指定粒径的诱导颗粒确定的，使得引导沟槽的宽度方向仅能容纳一粒诱导颗粒，避免诱导颗粒的粒径过大，同时，利用引导沟槽的两个侧壁限制纳米线的生长，减小纳米线的线宽，从而减小单个阵列基板有源区的面积，提高阵列基板的分辨率，而且，可以降低热载流子效应和短沟道效应引起的漏电流过大的现象，从而降低晶体管的功耗，进而降低背板的功耗。
为了更好地理解本公开阵列基板及制备方法，下面结合图11至图31，并以顶栅结构的阵列基板为例详细介绍。
步骤S1101，在衬底1上制备绝缘层2，然后在绝缘层2背离衬底1的表面制备催化层6，并对催化层6进行图形化，如图11所示。
在步骤S1101中，衬底1采用玻璃衬底，绝缘层2的材料为氮化硅(SiNx)，绝缘层2的厚度为3000埃，绝缘层2可以通过沉积工艺在衬底1上获得。催化层6的材料为铟锡氧化物，催化层6的厚度为150～400埃。催化层6可以通过沉积工艺在背离衬底1的表面获得，并通过涂覆、曝光、显影工艺对催化层6进行图形化。在本公开实施例中，铟锡氧化物与激活区相对。
步骤S1102，制备沟槽层4，并利用EBL技术在沟槽层4上形成贯穿沟槽层4的厚度的引导沟槽41，以使引导沟槽41的底部露出催化层，如图12所示。
其中，在激活区71的引导沟槽的间距较大，生长区72的引导沟槽的间距较小。例如，激活区71的引导沟槽的间距为0.2～2μm，位于生长区72的引导沟槽的间距为50～500nm。
在本公开实施例中，引导沟槽41的宽度基于纳米线的宽度确定，在引导沟槽41的宽度确定后，即可确定诱导颗粒的直径，并确定纳米线的宽度。
在一些实施例中，第一生长区43的引导沟槽的宽度为60～80nm，第二生长区44的引导沟槽的宽度为20～30nm，即第一生长区43的引导沟槽为宽引导沟槽，第二生长区44的引导沟槽为窄沟槽。其中，第一生长区43对应DTFT(DISCRETE-TIME FOURIER TRANSFORM，离散时间傅立叶变换)区，第二生长区44对应STFT(SHORT-TIME FOURIER TRANSFORM，短时傅立叶变换)区。
图13为本公开实施例中沿图12中的A-A′线的截面图。如图13所示，第一生长区43的引导沟槽41和第二生长区44的引导沟槽41的深度均为沟槽层4的厚度相同。图14为本公开实施例中沿图12中的B-B′线的截面图，图15为本公开实施例中沿图12中的C-C′线的截面图。如图14和图15所示，第一生长区43的引导沟槽41的宽度较大，第二生长区44的引导沟槽41的宽度较小。在激活区71，引导沟槽的底部为催化层6。
步骤S1103，对激活区进行处理，以在引导沟槽内获得诱导颗粒，如图16所示。
在步骤S1103中，激活区的材料为铟锡氧化物，利用等离子体增强化学气相沉积工艺(PECVD)并采用氢等离子体(H Plasma)对铟锡氧化物进行还原处理，获得铟诱导颗粒52。由于催化层6位于沟槽层4的下方，在还原处理过程中，仅在引导沟槽内生成铟诱导颗粒52，而不会在沟槽层4背离衬 底1的表面生成铟诱导颗粒52，这样可以避免后续的纳米线制备工艺中在沟槽层4的背离衬底1的表面生成纳米线。
在步骤S1103中，在激活区的存在两种不同宽度的引导沟槽，不同宽度的引导沟槽生成的诱导颗粒的直径不同，在较宽的引导沟槽内，形成颗粒较大的诱导颗粒，在较窄的引导沟槽内，形成颗粒较小的诱导颗粒。
具体地，激活区71包括第一激活区71a和第二激活区71b；所述生长区72包括第一生长区72a和第二生长区72b，所述第一生长区72a的引导沟槽与所述第一激活区71a的引导沟槽连通，所述第二生长区72b的引导沟槽与所述第二激活区71b的引导沟槽连通。第一激活区71a的引导沟槽的宽度大于第二激活区72a的引导沟槽的宽度，第一生长区72a的引导沟槽的宽度与所述第一激活区71a的引导沟槽的宽度相同，第二生长区72b的引导沟槽的宽度与所述第二激活区71b的引导沟槽的宽度相同。
步骤S1104，在沟槽层6背离衬底1的表面制备析出层7，并对析出层7进行处理，使得析出层7内的硅原子在诱导颗粒52的诱导下沿引导沟槽析出，形成硅纳米线，如图17所示。
在步骤S1104中，通过沉积工艺在沟槽层背离衬底的表面制备非晶硅，非晶硅的厚度可以为300～500埃。然后，在390℃的温度下，对非晶硅进行退火处理，退火时间为30～60分钟，使得硅原子铟诱导颗粒的引导下，沿引导沟槽41析出，形成硅纳米线。
在本公开实施例中，在激活区存在两种宽度不同的引导沟槽，生成两种尺寸不同的诱导颗粒，在退火处理过程中，不同的诱导颗粒在对应的引导沟槽的双侧壁的约束下，形成不同宽度的纳米线。例如，在第一生长区43形成了宽度较宽的纳米线，如宽度为60nm的纳米线；在第二生长区44形成了宽度较窄的纳米线，如宽度为30nm的纳米线。
图18为本公开实施例中沿图17中的A-A′线的截面图。如图18所示，在第一生长区43的引导沟槽41内形成的硅纳米线的线宽较大，在第二生长 区44的引导沟槽41内形成的硅纳米线的线宽较小。图19为本公开实施例中沿图17中的B-B′线的截面图，图20为本公开实施例中沿图17中的C-C′线的截面图。如图19和图20所示，第一生长区43的引导沟槽41内的纳米线紧贴第一生长区43的引导沟槽41的两个侧壁，第二生长区44的引导沟槽41内的纳米线紧贴第二生长区44的引导沟槽41的两个侧壁。
步骤S1105，去除析出层的残留物和纳米线之外的诱导颗粒，然后在沟槽层背离衬底的表面依次制备牺牲层和过渡层，再对牺牲层和过渡层进行图形化，如图21所示。
在步骤S1105中，通过等离子体增强化学气相沉积工艺并采用氢等离子体刻蚀析出层的残留物。通过铟锡氧化物刻蚀液将多余的铟诱导颗粒去除。通过沉积工艺在沟槽层4背离衬底1的表面依次制备牺牲层8和过渡层9。其中，牺牲层8的材料可以为非晶硅，厚度可以为300～500埃。过渡层9的材料可以是N +非晶硅，过渡层的厚度为500～1000A。
为了降低阵列基板的制作成本，利用同一道掩膜工艺对牺牲层8和过渡层9进行图形化，以在过渡层9获得第一过渡电极91和第二过渡电极92。
由于在纳米线51与过渡层9之间设置牺牲层8，降低了刻蚀过渡层9时损伤纳米线51的概率。过渡层9作为薄膜晶体管的电极与纳米线的搭接的过渡层，可以降低接触电阻，从而改善薄膜晶体管的特性。
步骤S1106，在过渡层背离衬底的表面制备第一电极层，并对第一电极层进行图形化，如图22所示。
在步骤S1106中，在过渡层9背离衬底1的表面制备第一电极层10，然后对第一电极层10进行图形化，并在第一电极层10获得第一电极21和第二电极22。
步骤S1106，第一电极层10的材料包括钼、铜、铝等导电金属中的至少任意一种，第一电极层的厚度为2200埃。
步骤S1107，沉积钝化层，并在钝化层背离衬底的表面制备第二电极层， 并对该第二电极层进行图形化，获得第三电极，如图9所示。
在步骤S1107中，钝化层11的材料包括但不限于氧化硅(SiOx)、氮化硅(SiNx)，钝化层11覆盖纳米线、第一过渡电极、第二过渡电极、第一电极和第二电极的裸露表面，用于保护纳米线、第一过渡电极、第二过渡电极、第一电极和第二电极的裸露表面，以提高薄膜晶体管的寿命。
在步骤S1107中，钝化层11的厚度可以为800埃或400埃，第二电极层的材料包括钼、铜、铝等导电金属，厚度可以为3100埃。第三电极作为薄膜晶体管的栅极。
通过上述步骤S1101至步骤S1107，获得顶栅结构的晶体管。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (26)

  1. 一种纳米线制备方法，其包括：
    在衬底的第一表面制备绝缘层；
    在所述绝缘层背离所述衬底的表面形成具有引导沟槽的沟槽层；所述引导沟槽的宽度是指定粒径的诱导颗粒的粒径的0.8～1.2倍；
    在所述引导沟槽内制备诱导颗粒；
    在所述沟槽层背离所述衬底的表面制备析出层；
    对所述析出层进行处理，使所述析出层内的指定原子在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成纳米线。
  2. 根据权利要求1所述的方法，其中，所述在所述绝缘层背离所述衬底的表面形成具有引导沟槽的沟槽层，包括：
    在所述绝缘层背离所述衬底的表面形成沟槽介质层；
    利用电子束光刻技术对所述沟槽介质层进行处理，形成具有引导沟槽的沟槽层。
  3. 根据权利要求1所述的方法，其中，所述沟槽层包括激活区和生长区，所述激活区的引导沟槽的间距大于所述生长区的引导沟槽的间距，所述激活区的引导沟槽通过过渡沟槽与所述生长区的引导沟槽对应连接。
  4. 根据权利要求3所述的方法，其中，位于所述激活区的所述引导沟槽的间距为0.2～2μm；位于所述生长区的所述引导沟槽的间距为50～500nm。
  5. 根据权利要求3所述的方法，其中，所述激活区包括第一激活区和第二激活区；所述生长区包括第一生长区和第二生长区，所述第一生长区的引导沟槽与所述第一激活区的引导沟槽连通，所述第二生长区的引导沟槽与所述第二激活区的引导沟槽连通。
  6. 根据权利要求5所述的方法，其中，所述第一激活区的引导沟槽的宽度大于第二激活区的引导沟槽的宽度，所述第一生长区的引导沟槽的宽度 与所述第一激活区的引导沟槽的宽度相同，所述第二生长区的引导沟槽的宽度与所述第二激活区的引导沟槽的宽度相同。
  7. 根据权利要求5所述的方法，其中，所述激活区和所述生长区的引导沟槽通过一次工艺形成；
    所述第一激活区和所述第二激活区的引导沟槽内的诱导颗粒通过一次工艺形成；
    在所述第一生长区和所述第二生长区的纳米线通过一次工艺形成。
  8. 根据权利要求1所述的方法，其中，所述析出层的材料包括非晶硅；
    所述对所述析出层进行处理，使所述析出层内的指定原子在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成纳米线，包括：
    对所述析出层进行退火处理，使所述析出层内的硅原子在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成硅纳米线。
  9. 根据权利要求8所述的方法，其中，所述对所述析出层进行处理，使所述析出层内的指定原子在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成纳米线之后，包括：
    通过等离子体增强化学气相沉积工艺并采用氢等离子体刻蚀所述析出层的残留物；
    通过刻蚀液去除所述纳米线之外的所述诱导颗粒。
  10. 一种阵列基板制备方法，其包括形成纳米线，所述纳米线的制备方法包括权利要求1-9任意一项所述的方法。
  11. 根据权利要求10所述的方法，其中，所述对所述析出层进行处理，使所述析出层内的指定原子在所述诱导颗粒的诱导下沿所述引导沟槽析出，形成纳米线之后，还包括：
    在所述沟槽层背离所述衬底的表面制备牺牲层；
    在所述牺牲层背离所述衬底的表面制备过渡层；
    对所述过渡层进行图形化，并在所述过渡层形成第一过渡电极和第二过 渡电极。
  12. 根据权利要求11所述的方法，其中，所述对所述过渡层进行图形化之后，还包括：
    在所述过渡层背离所述衬底的表面制备第一电极层；
    对所述第一电极层进行图形化，获得第一电极和第二电极，所述第一电极叠置于所述第一过渡电极，所述第二电极叠置于所述第二过渡电极；
    沉积钝化层，所述钝化层覆盖所述纳米线、所述第一过渡电极、所述第二过渡电极、所述第一电极和所述第二电极的裸露表面。
  13. 根据权利要求10所述的方法，其中，所述衬底包括玻璃衬底和硅衬底中的一种。
  14. 一种阵列基板，其包括：
    衬底，所述衬底包括第一表面；
    绝缘层，所述绝缘层设置于所述衬底的第一表面；
    沟槽层，所述沟槽层设置于所述绝缘层背离所述衬底的表面，所述沟槽层设置有引导沟槽，所述引导沟槽的宽度是50～250nm；
    纳米线层，所述纳米线层设置于所述绝缘层背离所述衬底的表面，所述纳米线层设置有纳米线，所述纳米线嵌置于所述引导沟槽内。
  15. 根据权利要求14所述的阵列基板，其中，所述沟槽层包括激活区和生长区，所述激活区的引导沟槽的间距大于所述生长区的引导沟槽的间距，所述激活区的引导沟槽通过过渡沟槽与所述生长区的引导沟槽对应连接。
  16. 根据权利要求15所述的阵列基板，其中，位于所述激活区的所述引导沟槽的间距为0.2～2μm；位于所述生长区的所述引导沟槽的间距为50～500nm。
  17. 根据权利要求15所述的阵列基板，其中，所述激活区包括第一激活区和第二激活区；所述生长区包括第一生长区和第二生长区，所述第一生 长区的引导沟槽与所述第一激活区的引导沟槽连通，所述第二生长区的引导沟槽与所述第二激活区的引导沟槽连通。
  18. 根据权利要求17所述的阵列基板，其中，所述第一激活区的引导沟槽的宽度大于第二激活区的引导沟槽的宽度，所述第一生长区的引导沟槽的宽度与所述第一激活区的引导沟槽的宽度相同，所述第二生长区的引导沟槽的宽度与所述第二激活区的引导沟槽的宽度相同。
  19. 根据权利要求17所述的阵列基板，其中，所述纳米线层包括多组纳米线组，每组所述纳米线组包括多条间隔设置的纳米线；所述激活区对应的所述纳米线组中的所述纳米线的间距为0.2～2μm，所述生长区对应的纳米线组中的所述纳米线的间距为50～500nm。
  20. 根据权利要求19所述的阵列基板，其中，所述第一激活区和所述第一生长区对应的纳米线组中的纳米线的线宽为60～80nm，所述第二激活区和所述第二生长区对应的纳米线组中的纳米线的线宽为20～30nm。
  21. 根据权利要求14所述的阵列基板，其中，还包括：第一电极层，所述第一电极层叠置于所述纳米线层背离所述衬底的表面，且设置于所述第一电极层的第一电极与所述纳米线的源极区域电连接，设置于所述第一电极层的第二电极与所述纳米线的漏极区域电连接。
  22. 根据权利要求21所述的阵列基板，其中，还包括：过渡层，所述过渡层设置于所述纳米线层背离所述衬底的表面，且设置于所述过渡层的第一过渡电极叠置于所述第一电极与所述纳米线的源极区域之间，设置于所述过渡层的第二过渡电极叠置于所述第二电极与所述纳米线的漏极区域之间。
  23. 根据权利要求22任意一项所述的阵列基板，其中，还包括：第三电极，所述第三电极设置于所述衬底和所述绝缘层之间。
  24. 根据权利要求23所述的阵列基板，其中，还包括钝化层，所述钝化层覆盖所述沟槽层、所述纳米线层和所述第一电极层的裸露表面。
  25. 根据权利要求14-22任意一项所述的阵列基板，其中，还包括钝化 层和第三电极，所述钝化层覆盖所述绝缘层和所述纳米线的裸露表面；
    所述第三电极设置于所述钝化层背离所述衬底的表面。
  26. 一种电子设备，其包括权利要求14-25任意一项所述的阵列基板。
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