WO2022252469A1 - 一种薄膜晶体管以及薄膜晶体管的制备方法 - Google Patents

一种薄膜晶体管以及薄膜晶体管的制备方法 Download PDF

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WO2022252469A1
WO2022252469A1 PCT/CN2021/124661 CN2021124661W WO2022252469A1 WO 2022252469 A1 WO2022252469 A1 WO 2022252469A1 CN 2021124661 W CN2021124661 W CN 2021124661W WO 2022252469 A1 WO2022252469 A1 WO 2022252469A1
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electrode
insulating layer
substrate
gate
layer
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PCT/CN2021/124661
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English (en)
French (fr)
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徐苗
李民
周雷
徐华
李洪濛
庞佳威
彭俊彪
王磊
邹建华
陶洪
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华南理工大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • Embodiments of the present invention relate to the technical field of semiconductors, and in particular to a thin film transistor and a method for manufacturing the thin film transistor.
  • thin film transistors play a very important role in the performance of display devices.
  • Common thin film transistors mainly include amorphous silicon thin film transistors, polysilicon thin film transistors, organic thin film transistors and metal oxide thin film transistors.
  • metal oxide thin film transistors have excellent piezoelectric, photoelectric, gas-sensitive and pressure-sensitive properties, they have broad development prospects in the semiconductor field.
  • the source and drain of traditional thin film transistors are designed to be coplanar.
  • the shape of the source is changed, the shape of the drain needs to be adjusted accordingly, resulting in too much correlation between the source and drain, which in turn leads to the thin film transistor.
  • the production cost is relatively high.
  • the invention provides a thin film transistor and a preparation method of the thin film transistor, so as to reduce the degree of correlation between the source and the drain and the production cost.
  • an embodiment of the present invention provides a thin film transistor, and the thin film transistor includes:
  • a first electrode located on the surface of the substrate
  • interlayer insulating layer is located on the surface of the first electrode facing away from the substrate, the surface of the interlayer insulating layer facing away from the first electrode is a plane, and the interlayer insulating layer A first via hole is provided, and the first via hole exposes part of the first electrode;
  • the active layer is located on the surface of the interlayer insulating layer facing away from the first electrode, the active layer includes a source region, a drain region, and a drain region located between the source region and the drain region The channel region between; the projected area of the first electrode on the substrate covers the projected area of the channel region on the substrate, wherein the active layer includes metal oxide semiconductor material or carbon nanometer Tube;
  • a gate insulating layer and a gate, the gate insulating layer and the gate stack are disposed on the surface of the active layer on the side away from the interlayer insulating layer, wherein the gate insulating layer is located on the between the active layer and the gate;
  • a first passivation layer is located on the surface of the interlayer insulating layer facing away from the first electrode, and extends to the surface of the active layer, the first passivation layer is set There is a second via;
  • the second electrode is located on the surface of the first passivation layer away from the gate;
  • the first electrode is a source, the source region is connected to the first electrode through the first via hole, the second electrode is a drain, and the second electrode is connected to the first electrode through the second via hole
  • the drain region is connected; or, the first electrode is a drain, the drain region is connected to the first electrode through the first via hole, the second electrode is a source electrode, and the second electrode is connected to the first electrode through the first via hole.
  • Two via holes are connected with the source region.
  • the first electrode is a source
  • the second electrode is a drain
  • the thickness of the first electrode is greater than the thickness of the second electrode
  • the first electrode is a drain
  • the second electrode is a source electrode
  • the thickness of the second electrode is greater than the thickness of the first electrode
  • the first electrode is a source
  • the second electrode is a drain
  • the projected area of the first electrode on the substrate is larger than the projected area of the second electrode on the substrate
  • the The projection of the first electrode on the substrate covers part or all of the projection of the channel region on the substrate
  • the first electrode is a drain
  • the second electrode is a source
  • the second The projected area of the electrode on the substrate is larger than the projected area of the first electrode on the substrate
  • the projected area of the second electrode on the substrate covers part or all of the channel region on the substrate Bottom projection.
  • a projection of the gate on the substrate overlaps with a projection of the gate insulating layer on the substrate.
  • the projection of the gate on the substrate and the projection of the channel region on the substrate overlap, the conductivity of the source region is greater than the conductivity of the channel region, and the The conductivity of the drain region is greater than that of the channel region.
  • MO composite oxide
  • RO rare earth oxide
  • the embodiment of the present invention also provides a method for manufacturing a thin film transistor, and the method for manufacturing a thin film transistor includes:
  • An interlayer insulating layer is formed on the surface of the first electrode away from the substrate, wherein the surface of the interlayer insulating layer away from the first electrode is a plane, and the interlayer insulating layer is provided with a first a via hole, the first via hole exposing part of the first electrode;
  • An active layer is formed on the surface of the interlayer insulating layer facing away from the first electrode, and the active layer includes a source region, a drain region, and a channel region between the source region and the drain region ;
  • the projected area of the first electrode on the substrate covers the projected area of the channel region on the substrate, wherein the active layer includes metal oxide semiconductor materials or carbon nanotubes;
  • a gate insulating layer and a gate on the surface of the active layer facing away from the interlayer insulating layer, wherein the gate insulating layer is located between the active layer and the gate;
  • a first passivation layer is formed on the surface of the interlayer insulating layer facing away from the first electrode, the active layer, the gate insulating layer and the gate are located in the first passivation layer, the first passivation layer
  • a passivation layer includes a second via hole
  • the first electrode is a source, the source region is connected to the first electrode through the first via hole, the second electrode is a drain, and the second electrode is connected to the first electrode through the second via hole
  • the drain region of the active layer is connected; or, the first electrode is a drain electrode, the drain region is connected to the first electrode through the first via hole, the second electrode is a source electrode, and the second electrode connected to the source region of the active layer through the second via hole.
  • forming a gate insulating layer and a gate on the surface of the active layer facing away from the interlayer insulating layer includes:
  • patterning the conductive layer to form the gate includes:
  • patterning the insulating layer through a self-alignment process to form the gate insulating layer further includes:
  • the gate and the gate insulating layer as a mask, perform high-conductivity treatment on the source region and the drain region, wherein the conductivity of the source region is greater than that of the channel region rate, and the conductivity of the drain region is greater than the conductivity of the channel region.
  • the method further includes:
  • the second passivation layer is located on the surface of the second electrode away from the first passivation layer, and extend to the surface of the first passivation layer.
  • the projected area of the first electrode on the substrate covers the projected area of the channel region on the substrate, so that the first electrode can reflect the light shown on the side away from the active side of the substrate, and avoid the channel region inside the substrate away from the active side. Under the action of light on the surface of one side of the layer, photogenerated carriers are generated, which promotes the good output characteristics of the thin film transistor in the saturation region.
  • the surface of the interlayer insulating layer facing away from the first electrode is a plane, which ensures the flatness of the active layer, thereby improving the stability of the electrical performance of the thin film transistor.
  • the invention achieves the effects of reducing the degree of correlation between the source and the drain and the production cost.
  • the active layer includes metal oxide semiconductor materials or carbon nanotubes, and the thin film transistor can exhibit excellent device performance.
  • FIG. 1 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another thin film transistor provided by an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another thin film transistor provided by an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of another thin film transistor provided by an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another thin film transistor provided by an embodiment of the present invention.
  • FIG. 6 is a flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present invention.
  • Fig. 7 is a flowchart of the preparation method included in S450 in Fig. 6;
  • FIG. 8 is a flowchart of another method for manufacturing a thin film transistor provided by an embodiment of the present invention.
  • 9 to 18 are sectional views corresponding to each step of a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of another thin film transistor provided by an embodiment of the present invention.
  • the thin film transistor includes: a substrate 110; The first electrode 120, the first electrode 120 is located on the surface of the substrate 110; the interlayer insulating layer 130, the interlayer insulating layer 130 is located on the surface of the first electrode 120 away from the substrate 110 side, the interlayer insulating layer 130 is away from the first electrode
  • the surface of 120 is a plane, the interlayer insulating layer 130 is provided with a first via hole 131, the first via hole 131 exposes part of the first electrode 120; the active layer 140, the active layer 140 is located in the interlayer insulating layer 130 away from the first electrode 120, the active layer 140 includes a source region 141, a drain region 142, and a channel region 143 between the source region 141 and the drain region 142; the projected area of the first electrode 120 on
  • the first electrode 120 is the source
  • the source region 141 is connected to the first electrode 120 through the first via hole 131
  • the second electrode 180 is the drain
  • the second electrode 180 Connect to the drain region 142 through the second via hole 171; or, referring to FIG. 2, the first electrode 120 is the drain electrode, the drain region 142 is connected to the first electrode 120 through the first via hole 131, and the second electrode 180 is the source electrode, The second electrode 180 is connected to the source region 141 through the second via hole 171 .
  • the substrate 110 has the functions of supporting and fixing.
  • the active layer 140 includes metal oxide semiconductor materials, and the thin film transistor has excellent piezoelectric, photoelectric, gas-sensitive and pressure-sensitive properties.
  • the active layer 140 includes carbon nanotubes.
  • the diameter of the carbon nanotube is greater than or equal to 1.45 nanometers and less than or equal to 1.65 nanometers.
  • the length of the carbon nanotube is greater than or equal to 0.7 nanometers and less than or equal to 1.3 nanometers.
  • the thickness of the carbon nanotube is greater than or equal to 5 nanometers and less than or equal to 15 nanometers.
  • the carbon nanotubes in this embodiment include single-walled carbon nanotubes (SWCNTs). Single-walled carbon nanotubes are widely used in electronic and optoelectronic devices due to their excellent charge transport properties, good solution processability, high flexibility, excellent mechanical properties and high thermal conductivity, excellent mechanical stability and chemical stability.
  • thin-film transistors prepared with single-walled carbon nanotubes as active layer materials have excellent electrical properties, smaller feature size, good stability, faster heat dissipation, and higher operating frequency, showing excellent device performance and great stability.
  • Example 1 It can be seen that the data line is connected to the source, and when the driving current value on the data line is large, The ability of the source to transmit a large driving current can be improved by enlarging the area of the source.
  • Example 2 In order to reduce the voltage drop of the source, thereby reducing power consumption, the thickness of the source can be increased to reduce the cross-sectional area of the mobile charge, thereby reducing the resistance of the source, thereby reducing the voltage drop of the source and thin film transistor power consumption.
  • Example 3 In order to prevent light from the substrate 110 side from irradiating the active layer to form photogenerated carriers, the projected area of the first electrode 120 on the substrate 110 needs to cover the projected area of the channel region 143 on the substrate 110 .
  • Example 2 For the change of the shape of the source in Example 1 and Example 2, the technical solution provided by this embodiment does not need to change the shape of the drain synchronously. If the source and drain are located on the same layer, the amount of metal used in the drain will increase. Technical problems that increase costs.
  • the technical solution provided by this embodiment does not need to change the shape of the second electrode 180 synchronously.
  • the amount of metal used in the second electrode 180 increases the technical problem of cost.
  • the part of the active layer 140 close to the first via hole 131 may be the source region 141 or the drain region 142 .
  • the first electrode 120 is the source
  • the second electrode 180 is the drain
  • the part of the active layer 140 close to the first via hole 131 is the source region 141
  • the active layer 140 is close to the second via hole 171 is the drain region 142
  • FIG. 2 when the first electrode 120 is the drain, the second electrode 180 is the source, and the part of the active layer 140 close to the first via hole 131 is the drain region 142, then there is A portion of the source layer 140 close to the second via hole 171 is the source region 141 .
  • the projected area of the first electrode 120 on the substrate 110 covers the projected area of the channel region 143 on the substrate 110, so that the first electrode 120 can reflect light from the surface of the substrate 110 away from the active layer 140, avoiding the channel region 143.
  • the region 143 photocarriers are generated by the light on the surface of the substrate 110 facing away from the active layer 140 , so that the thin film transistor exhibits good output characteristics in the saturation region.
  • the surface of the interlayer insulating layer 130 facing away from the first electrode 120 is a plane, which ensures the flatness of the active layer 140 and improves the stability of the electrical performance of the thin film transistor.
  • the projected area of the first electrode 120 on the substrate 110 covers the projected area of the channel region 143 on the substrate 110, so that the first electrode 120 can reflect the light on the side of the substrate 110 away from the active layer 140, avoiding the channel region 143.
  • the thin film transistor exhibits good output characteristics in the saturation region.
  • the surface of the interlayer insulating layer 130 facing away from the first electrode 120 is a plane, which ensures the flatness of the active layer 140 and improves the stability of the electrical performance of the thin film transistor.
  • the technical solution of this embodiment solves the problem that the source and drain are designed in the same layer in the prior art, which leads to too much correlation between the source and the drain, which in turn leads to a large production cost of the thin film transistor, and achieves a reduction The degree of correlation between source and drain and the effect of production cost.
  • the active layer 140 includes metal oxide semiconductor materials or carbon nanotubes, and the thin film transistor can exhibit excellent device performance.
  • the first electrode 120 is a source electrode
  • the second electrode 180 is a drain electrode
  • the thickness of the first electrode 120 is greater than the thickness of the second electrode 180; or, referring to FIG. 2.
  • the first electrode 120 is a drain
  • the second electrode 180 is a source
  • the thickness of the second electrode 180 is greater than that of the first electrode 120 .
  • the source electrode is connected to the data line connection electrode of the display panel, setting the thickness of the source electrode greater than the thickness of the drain electrode can make the cross-sectional area through which the current flows larger, thereby reducing the overall resistance, so that the source electrode The voltage drop is reduced to achieve the effect of reducing power consumption.
  • the first electrode 120 is a source
  • the second electrode 180 is a drain
  • the projected area of the first electrode 120 on the substrate 110 is greater than the projected area of the second electrode 180 on the substrate 110
  • the projection of an electrode 120 on the substrate 110 covers part or all of the projection of the channel region 143 on the substrate 110; or, referring to FIG. 2, the first electrode 120 is a drain, the second electrode 180 is a source, and the second electrode 180
  • the projected area of the substrate 110 is greater than the projected area of the first electrode 120 on the substrate 110
  • the projected area of the second electrode 180 on the substrate 110 covers part or all of the projected area of the channel region 143 on the substrate 110 .
  • the projected area of the source on the substrate 110 is larger than the projected area of the drain 110 on the substrate 110, so that while ensuring that the projection of the source on the substrate 110 covers the projection of the channel region 143 on the substrate 110, when When the value of the driving current on the data line is large, the projected area of the source on the substrate 110 is larger than the projected area of the drain 110 on the substrate to improve the ability of the source to transmit a large driving current.
  • the shape of the drain electrode does not need to be changed, thereby reducing the manufacturing cost.
  • the larger the area where the projection of the first electrode 120 covers the channel region 143 on the substrate 110 is, the better the effect is on reducing the light from the substrate 110 side to irradiate the active layer 140 to form photogenerated carriers.
  • the thickness of the source electrode can be made greater than the thickness of the drain electrode in order to reduce the voltage drop and power consumption of the source electrode;
  • the projected area of the source on the substrate 110 is larger than the projected area of the drain on the substrate 110 to improve the ability of the source to transmit a large driving current.
  • the projection of the gate 160 on the substrate 110 overlaps with the projection of the gate insulating layer 150 on the substrate 110 .
  • the projection of the gate 160 on the substrate 110 overlaps with the projection of the gate insulating layer 150 on the substrate 110, so that after the gate 160 is prepared, the self-alignment process of the gate 160 can be used to form the gate 160
  • the film layer where the gate insulating layer 150 is located is patterned to obtain the gate insulating layer 150, which saves the number of masks and the manufacturing cost of the thin film transistor.
  • the projection of the gate 160 on the substrate 110 overlaps with the projection of the channel region 143 on the substrate 110.
  • the gate 160 can be self-aligned.
  • the source region 141 of the active layer 140 is subjected to a high-conductivity treatment, so that the conductivity of the source region 141 is greater than the conductivity of the channel region 143, and the drain region of the active layer 140 is 142 is subjected to a high-conductivity treatment so that the conductivity of the drain region 142 is greater than that of the channel region 143.
  • the source region 141 and the source A good ohmic contact is formed between them, and a good ohmic contact is formed between the drain region 142 and the drain.
  • FIG. 3 is a schematic structural diagram of another thin film transistor provided by an embodiment of the present invention.
  • the thin film transistor further includes: a second passivation layer 190, a second passivation layer The layer 190 is located on the surface of the second electrode 180 away from the first passivation layer 170 and extends to the surface of the first passivation layer 170 .
  • the second passivation layer 190 has the functions of dustproof, waterproof and insulating, thereby achieving the effect of protecting the second electrode 180, and the second passivation layer 190 may include a silicon dioxide (SiO 2 ) layer and an organic substance, wherein The thickness of silicon dioxide is about The thickness of the organic matter is about 1.2um.
  • FIG. 4 is a schematic structural diagram of another thin film transistor provided by an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of another thin film transistor provided by an embodiment of the present invention.
  • the thin film transistor further includes: an anode 210 and a data line connection electrode 220; the second passivation layer 190 further includes a third via hole 191 and a fourth via hole 192, and the first passivation layer 170 further includes The fifth via hole 172, the interlayer insulating layer 130 also includes the sixth via hole 132; when the first electrode 120 is the source and the second electrode 180 is the drain, the anode 210 of the display unit is located in the second passivation layer 190 away from the first On the surface on one side of the passivation layer 170, the anode 210 of the display unit is connected to the second electrode 180 through the third via hole 191; On the surface, the data line connection electrode 220 is connected to the first electrode 120 through the fourth via hole 192 , the fifth via hole
  • the anode 210 of the display unit connects with the fourth via 192 , the fifth via 172 and the sixth via 132 through the fourth via 192 , the fifth via 172 and the sixth via 132 .
  • One electrode 120 is connected; the data line connection electrode 220 is connected to the second electrode 180 through the third via hole 191 .
  • the thin film transistor provided in this embodiment is used to provide a driving current for a display unit in a saturated state.
  • the active layer 140 includes at least one of indium, zinc, gallium, tin, zirconium, and tantalum corresponding to a composite oxide composed of an oxide MO and a rare earth oxide RO.
  • MO x
  • RO rare earth oxide
  • rare earth oxides include at least one of praseodymium oxide, terbium oxide, dysprosium oxide and ytterbium oxide .
  • the rare earth oxide can be used as a light stabilizer, thereby enhancing the light stability of the active layer 140, thereby enhancing the display uniformity and stability of the display screen.
  • FIG. 6 is a flowchart of a method for manufacturing a thin film transistor provided by an embodiment of the present invention.
  • 9 to 18 are sectional views corresponding to each step of a method for manufacturing a thin film transistor according to an embodiment of the present invention. Referring to FIG. 6, the thin film transistor shown in FIG. 1 is taken as an example for illustration.
  • the preparation method of the thin film transistor includes the following steps:
  • a substrate 110 is provided.
  • the substrate 110 may be a wafer.
  • the first electrode 120 may be formed on the surface of the substrate 110 through an electroplating process. Specifically, firstly, an entire seed layer covering the substrate 10 is formed on the surface of the substrate 10 . Then a patterned electroplating film layer is formed on the surface of the seed layer, and an electroplating metal layer with a predetermined thickness is continuously formed on the surface of the patterned electroplating mask layer through an electroplating process. After that, the electroplating layer is removed, and the seed layer and the electroplating metal layer are patterned to obtain the first electrode 120 .
  • the seed layer may be a stack of metal molybdenum and metal copper.
  • the film thickness of the metal molybdenum is more than 30 nanometers, and the film thickness of the metal copper is about 300 nanometers.
  • the electroplated metal layer may be an electroplated copper layer, wherein the thickness of the electroplated copper layer is greater than or equal to 300 nanometers and less than or equal to 1000 nanometers.
  • the electroplating film layer may include any one of SU-8, silicon nitride (SiNx) and silicon oxide (SiO 2 ). Among them, SU-8 is a negative, epoxy type, near ultraviolet photoresist. The thickness of the electroplating layer is greater than or equal to 5 microns and less than or equal to 25 microns.
  • a metal layer may also be formed on the surface of the substrate 110 through a magnetron sputtering process, and then a patterning process is performed on the metal layer through a first mask to form the first electrode 120 .
  • the first electrode 120 may be a source or a drain.
  • the first electrode 120 is a source.
  • the source electrode can be a stack of metal titanium and metal copper.
  • the thickness of the metal titanium is The thickness of copper metal
  • the drain electrode may include metal molybdenum.
  • the thickness of metal molybdenum is Alternatively, the drain electrode may be a laminated layer of metal aluminum and metal molybdenum.
  • the thickness of metal aluminum is The thickness of molybdenum metal is Alternatively, the drain electrode may be a laminated layer of metal molybdenum and metal copper.
  • the thickness of metal molybdenum is The thickness of copper metal is
  • an interlayer insulating layer 130 is formed on the surface of the first electrode 120 facing away from the substrate 110, wherein the surface of the interlayer insulating layer 130 facing away from the first electrode 120 is a plane, which can ensure that the interlayer insulating layer 130 The flatness of the formed functional layer.
  • the interlayer insulating layer 130 is patterned through the second mask to form the first via hole 131 .
  • the interlayer insulating layer 130 may include a stack of silicon nitride (SiNx) and silicon dioxide (SiO 2 ), or, the interlayer insulating layer 130 includes silicon dioxide (SiO 2 ), for example, nitrogen
  • the thickness of SiO is The thickness of silicon dioxide is The thickness of silicon dioxide is
  • the active layer includes a source region, a drain region, and a channel region between the source region and the drain region; the first electrode is formed on the substrate
  • the projected area covers the projected area of the channel region on the substrate, wherein the active layer includes metal oxide semiconductor materials or carbon nanotubes.
  • an active layer 140 is formed on the surface of the interlayer insulating layer 130 facing away from the first electrode 120, and the active layer 140 includes a source region 141, a drain region 142, and a trench between the source region 141 and the drain region 142.
  • Road District 143 The projected area of the first electrode 120 on the substrate 110 covers the projected area of the channel region 143 on the substrate 110, so that the first electrode 120 can reflect the light on the surface of the substrate 110 away from the active layer 140, avoiding the channel region 143 Photocarriers are generated inside under the action of light on the surface of the substrate 110 facing away from the active layer 140 , so that the thin film transistor exhibits good output characteristics in the saturation region.
  • the film layer where the active layer 140 is located is patterned through the third mask to form the active layer 140 .
  • MO composite oxide
  • RO rare earth oxide
  • the rare earth oxide can be used as a light stabilizer, thereby enhancing the light stability of the active layer 140, thereby enhancing the display uniformity and stability of the display screen.
  • a gate insulating layer 150 and a gate 160 are formed on the surface of the active layer 140 facing away from the interlayer insulating layer 130 , wherein the gate insulating layer 150 is located between the active layer 140 and the gate 160 .
  • the gate insulating layer 150 includes silicon dioxide.
  • the thickness of silicon dioxide is The gate 160 may include metal molybdenum.
  • the thickness of metal molybdenum is Alternatively, the grid 160 may be a laminate of metal aluminum and metal molybdenum, and the thickness of the metal aluminum is The thickness of molybdenum metal is Alternatively, the gate 160 may be a laminated layer of metal molybdenum and metal copper.
  • the thickness of metal molybdenum is The thickness of copper metal is
  • the film layer where the gate 160 is located is patterned through the fourth mask to form the gate 160 .
  • a first passivation layer 170 is formed on the surface of the interlayer insulating layer 130 facing away from the first electrode 120 .
  • the first passivation layer 170 is patterned through a fifth mask to form a second via hole 171 .
  • the first passivation layer 170 may include a silicon dioxide (SiO 2 ) layer and organic matter, wherein the silicon dioxide has a thickness of about The thickness of the organic matter is about 1.2um.
  • the first electrode is a source, the source region is connected to the first electrode through a first via hole, the second electrode is a drain, and the second electrode is a source.
  • the second electrode is connected to the drain region of the active layer through the second via hole; or, the first electrode is a drain electrode, the drain region is connected to the first electrode through the first via hole, the second electrode is a source electrode, and the second electrode is connected to the first electrode through the first via hole.
  • the second via hole is connected with the source area of the active layer.
  • the second electrode 180 may be formed on the surface of the first passivation layer 170 facing away from the interlayer insulating layer 130 through an electroplating process.
  • Example 1 It can be seen that the data line is connected to the source, and when the driving current value on the data line is large, The ability of the source to transmit a large driving current can be improved by enlarging the area of the source.
  • Example 2 In order to reduce the voltage drop of the source, thereby reducing power consumption, the thickness of the source can be increased to reduce the cross-sectional area of the mobile charge, thereby reducing the resistance of the source, thereby reducing the voltage drop of the source and thin film transistor power consumption.
  • Example 3 In order to prevent light from the substrate 110 side from irradiating the active layer 140 to form photogenerated carriers, the projected area of the first electrode 120 on the substrate 110 needs to cover the projected area of the channel region 143 on the substrate 110 .
  • Example 2 For the change of the shape of the source in Example 1 and Example 2, the technical solution provided by this embodiment does not need to change the shape of the drain synchronously. If the source and drain are located on the same layer, the amount of metal used in the drain will increase. Technical problems that increase costs.
  • the technical solution provided by this embodiment does not need to change the shape of the second electrode 180 synchronously.
  • the amount of metal used in the second electrode 180 increases the technical problem of cost.
  • the film layer where the second electrode 180 is located is patterned through the sixth mask to form the second electrode 180 .
  • the first electrode 120 is the source, the source region 141 is connected to the first electrode 120 through the first via hole 131, the second electrode 180 is the drain electrode, and the second electrode 120 is connected to the existing electrode 120 through the second via hole 171.
  • the drain region 142 of the source layer 140 is connected; or, referring to FIG. 2 , the first electrode 120 is a drain, the drain region 142 is connected to the first electrode 120 through the first via hole 131, the second electrode 180 is a source, and the second electrode 180 is connected to the source region 141 of the active layer 140 through the second via hole 171 .
  • the manufacturing method of the thin film transistor shown in FIG. 2 is similar to the manufacturing method of the thin film transistor shown in FIG. 1 , and will not be repeated here.
  • the part of the active layer 140 close to the first via hole 131 may be the source region 141 or the drain region 142.
  • the second electrode 180 is the drain electrode.
  • the part of the active layer 140 close to the first via hole 131 is the source region 141
  • the part of the active layer 140 close to the second via hole 171 is the drain region 142;
  • the first electrode 120 is the drain electrode
  • the second electrode 180 is the source
  • the part of the active layer 140 close to the first via hole 131 is the drain region 142
  • the part of the active layer 140 close to the second via hole 171 is the source region 141 .
  • the first electrode 120 is a source electrode
  • the second electrode 180 is a drain electrode
  • the thickness of the first electrode 120 is greater than the thickness of the second electrode 180; or, referring to FIG. 2 , the first electrode 120 is a drain electrode. electrode
  • the second electrode 180 is the source electrode
  • the thickness of the second electrode 180 is greater than that of the first electrode 120 .
  • the source electrode is connected to the data line connection electrode of the display panel, setting the thickness of the source electrode greater than the thickness of the drain electrode can make the cross-sectional area through which the current flows larger, thereby reducing the overall resistance, so that the source electrode The voltage drop is reduced to achieve the effect of reducing power consumption.
  • the film thickness of the first electrode 120 can be controlled by controlling the film forming time of the metal sputtering process.
  • the second electrode 180 is formed on the surface of the first passivation layer 170 away from the interlayer insulating layer 130. Exemplarily, the formation time of the second electrode 180 can be controlled by controlling the film formation time of the metal sputtering process. film thickness.
  • the first electrode 120 is a source
  • the second electrode 180 is a drain
  • the projected area of the first electrode 120 on the substrate 110 is greater than the projected area of the second electrode 180 on the substrate 110
  • the projection of an electrode 120 on the substrate 110 covers part or all of the projection of the channel region 143 on the substrate 110; or, referring to FIG. 2, the first electrode 120 is a drain, the second electrode 180 is a source, and the second electrode 180
  • the projected area of the substrate 110 is greater than the projected area of the first electrode 120 on the substrate 110
  • the projected area of the second electrode 180 on the substrate 110 covers part or all of the projected area of the channel region 143 on the substrate 110 .
  • first electrode 120 and the second electrode 180 having different projected areas can be formed by patterning.
  • the projected area of the source on the substrate 110 is larger than the projected area of the drain 110 on the substrate, so that while ensuring that the projection of the source on the substrate 110 covers the projection of the channel region 143 on the substrate 110, when the data When the value of the driving current on the line is large, the projected area of the source on the substrate 110 is larger than the projected area of the drain 110 on the substrate to improve the ability of the source to transmit a large driving current.
  • the shape of the drain electrode does not need to be changed, thereby reducing the manufacturing cost.
  • the larger the area where the projection of the first electrode 120 covers the channel region 143 on the substrate 110 is, the better the effect is on reducing the light from the substrate 110 side to irradiate the active layer 140 to form photogenerated carriers.
  • the thickness of the source electrode can be made greater than the thickness of the drain electrode in order to reduce the voltage drop and power consumption of the source electrode;
  • the projected area of the source on the substrate 110 is larger than the projected area of the drain 110 on the substrate to improve the ability of the source to transmit a large driving current.
  • the projected area of the first electrode 120 on the substrate 110 covers the projected area of the channel region 143 on the substrate 110, so that the first electrode 120 can reflect light from the surface of the substrate 110 away from the active layer 140, avoiding the channel region 143.
  • photocarriers are generated by the light on the surface of the substrate 110 facing away from the active layer 140 , so that the thin film transistor exhibits good output characteristics in the saturation region.
  • the surface of the interlayer insulating layer 130 facing away from the first electrode 120 is a plane, which ensures the flatness of the active layer 140 and improves the stability of the electrical performance of the thin film transistor.
  • the technical solution of this embodiment solves the problem that the source and drain are designed in the same layer in the prior art, which leads to too much correlation between the source and the drain, which in turn leads to a large production cost of the thin film transistor, and achieves a reduction The degree of correlation between source and drain and the effect of production cost.
  • the active layer 140 includes metal oxide semiconductor materials or carbon nanotubes, and the thin film transistor can exhibit excellent device performance.
  • FIG. 7 is a flow chart of the preparation method included in S450 in FIG. 6 .
  • forming a gate insulating layer and a gate on the surface of the active layer facing away from the interlayer insulating layer includes:
  • an insulating layer 151 is formed on the surface of the channel region 143 facing away from the interlayer insulating layer 130 .
  • a conductive layer 161 is formed on the surface of the insulating layer 151 away from the active layer 140 .
  • the conductive layer 161 is patterned through a fourth mask to form a gate 160 .
  • the insulating layer 151 is patterned by a self-alignment process to form the gate insulating layer 150, wherein the projection of the gate 160 on the substrate 110 and the gate insulating The projections of the layers 150 on the substrate 110 overlap.
  • the projection of the gate 160 on the substrate 110 overlaps with the projection of the gate insulating layer 150 on the substrate 110, so that after the gate 160 is prepared, the self-alignment process of the gate 160 can be used to form the gate 160
  • the film layer where the gate insulating layer 150 is located is patterned to obtain the gate insulating layer 150, which saves the number of masks and the manufacturing cost of the thin film transistor.
  • S453 patterning the conductive layer to form a gate includes:
  • the conductive layer is patterned to form a grid whose projection on the substrate overlaps with the projection of the channel region on the substrate.
  • the conductive layer 161 is patterned through a fourth mask to form a gate 160 whose projection on the substrate 110 overlaps with the projection of the channel region 143 on the substrate 110 .
  • patterning the insulating layer through a self-alignment process to form the gate insulating layer further includes:
  • the source and drain regions are treated with high conductivity, wherein the conductivity of the source region is greater than that of the channel region, and the conductivity of the drain region is greater than that of the channel region conductivity.
  • the source region 141 and the drain region 142 are subjected to high-conductivity treatment, wherein the conductivity of the source region 141 is greater than that of the channel region 143, And the conductivity of the drain region 142 is greater than the conductivity of the channel region 143 .
  • the projection of the gate 160 on the substrate 110 overlaps with the projection of the channel region 143 on the substrate 110.
  • the gate 160 can be self-aligned.
  • the source region 141 of the active layer 140 is subjected to a high-conductivity treatment, so that the conductivity of the source region 141 is greater than the conductivity of the channel region 143, and the drain region of the active layer 140 is 142 is subjected to a high-conductivity treatment so that the conductivity of the drain region 142 is greater than that of the channel region 143.
  • the source region 141 and the source A good ohmic contact is formed between them, and a good ohmic contact is formed between the drain region 142 and the drain.
  • FIG. 8 is a flow chart of another method for manufacturing a thin film transistor provided in the embodiment of the present invention.
  • the thin film transistor shown in FIG. 1 is taken as an example for illustration.
  • the preparation method of the thin film transistor comprises the following steps:
  • a substrate 110 is provided.
  • a first electrode 120 is formed on a surface of a substrate 110 .
  • an interlayer insulating layer 130 is formed on the surface of the first electrode 120 facing away from the substrate 110 , wherein the surface of the interlayer insulating layer 130 facing away from the first electrode 120 is a plane.
  • the active layer includes a source region, a drain region, and a channel region located between the source region and the drain region;
  • the projected area of the bottom covers the projected area of the channel region on the substrate, wherein the active layer includes metal oxide semiconductor materials or carbon nanotubes.
  • an active layer 140 is formed on the surface of the interlayer insulating layer 130 facing away from the first electrode 120, and the active layer 140 includes a source region 141, a drain region 142, and a trench between the source region 141 and the drain region 142.
  • Road District 143 an active layer 140 is formed on the surface of the interlayer insulating layer 130 facing away from the first electrode 120, and the active layer 140 includes a source region 141, a drain region 142, and a trench between the source region 141 and the drain region 142.
  • a gate insulating layer 150 and a gate 160 are formed on the surface of the active layer 140 facing away from the interlayer insulating layer 130 , wherein the gate insulating layer 150 is located between the active layer 140 and the gate 160 .
  • a first passivation layer 170 is formed on the surface of the interlayer insulating layer 130 facing away from the first electrode 120 .
  • the first passivation layer 170 is patterned through a fifth mask to form a second via hole 171 .
  • the first electrode is the source electrode, the source region is connected to the first electrode through the first via hole, the second electrode is the drain electrode, and the second electrode is connected to the drain region of the active layer through the second via hole; or, the first The electrode is a drain, and the drain region is connected to the first electrode through the first via hole; the second electrode is a source electrode, and the second electrode is connected to the source region of the active layer through the second via hole.
  • the second electrode 180 may be formed on the surface of the first passivation layer 170 facing away from the interlayer insulating layer 130 through an electroplating process.
  • a second passivation layer 190 is formed on the surface of the first passivation layer 170 away from the interlayer insulating layer 130 , and the second passivation layer 190 is located on the surface of the second electrode 180 away from the first passivation layer 170 , and extend to the surface of the first passivation layer 170 .
  • the second passivation layer 190 has the functions of dustproof, waterproof and insulating, thereby achieving the effect of protecting the second electrode 180, and the second passivation layer 190 may include a silicon dioxide (SiO 2 ) layer and an organic substance, wherein The thickness of silicon dioxide is about The thickness of the organic matter is about 1.2um.
  • an anode 210 and a data line connection electrode 220 are formed on the surface of the second passivation layer 190 away from the first passivation layer 170, the first electrode 120 is a source, and the second electrode 180 is a drain.
  • the anode 210 of the display unit is connected to the second electrode 180 through the third via hole 191
  • the data line connection electrode 220 is connected to the first electrode 120 through the fourth via hole 192, the fifth via hole 172 and the sixth via hole 132.
  • the formation process of the sixth via hole 132 is as follows: the interlayer insulating layer 130 can be patterned through the second mask, and the sixth via hole 131 is formed at the same time. Vias 132 .
  • the formation process of the fifth via hole 172 is as follows: the first passivation layer 170 may be patterned through a fifth mask to form the second via hole 171 and the fifth via hole 172 at the same time.
  • the forming process of the third via hole 191 and the fourth via hole 192 is as follows: the second passivation layer 190 is patterned through a seventh mask to form the third via hole 191 and the fourth via hole 192 .
  • the film layer where the anode 210 and the data line connection electrode 220 are located is patterned through the eighth mask to form the anode 210 and the data line connection electrode 220 .
  • the anode 210 of the display unit connects with the first electrode 120 through the fourth via hole 192 , the fifth via hole 172 and the sixth via hole 132 . Connection; data line connection
  • the electrode 220 is connected to the second electrode through the third via hole 191 .
  • the thin film transistor provided in this embodiment is used to provide a driving current for a display unit in a saturated state.

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Abstract

本发明公开了一种薄膜晶体管以及薄膜晶体管的制备方法。薄膜晶体管包括：衬底；第一电极位于衬底的表面；层间绝缘层位于第一电极背离衬底一侧的表面，层间绝缘层背离第一电极的表面为平面，层间绝缘层设置有第一过孔；有源层位于层间绝缘层背离第一电极一侧的表面，有源层包括源区、漏区以及位于源区与漏区之间的沟道区；第一电极在衬底的投影面积覆盖沟道区在衬底的投影面积；栅极绝缘层和栅极层叠设置在有源层背离层间绝缘层一侧的表面；第一钝化层位于层间绝缘层背离第一电极一侧的表面，且延伸至有源层的表面；第二电极位于第一钝化层背离栅极一侧的表面。本发明达到了降低源极和漏极之间的关联度和生产成本的效果。

Description

一种薄膜晶体管以及薄膜晶体管的制备方法 技术领域
本发明实施例涉及半导体技术领域，尤其涉及一种薄膜晶体管以及薄膜晶体管的制备方法。
背景技术
薄膜晶体管作为液晶、有机显示器的关键器件，对于显示器件的工作性能具有十分重要的作用。常见的薄膜晶体管主要有非晶硅薄膜晶体管、多晶硅薄膜晶体管、有机薄膜晶体管以及金属氧化物薄膜晶体管。
由于金属氧化物薄膜晶体管具有优良的压电、光电、气敏和压敏等性能，在半导体领域具有广泛的发展前景。
传统的薄膜晶体管的源极和漏极大都共面设计，改变源极的形状时，漏极的形状也需要相应调整，导致源极和漏极之间的关联度太大，进而导致薄膜晶体管的生产成本较大。
发明内容
本发明提供一种薄膜晶体管以及薄膜晶体管的制备方法，以降低源极和漏极之间的关联度和生产成本。
第一方面，本发明实施例提供了一种薄膜晶体管，薄膜晶体管包括：
衬底；
第一电极，所述第一电极位于所述衬底的表面；
层间绝缘层，所述层间绝缘层位于所述第一电极背离所述衬底一侧的表面，所述层间绝缘层背离所述第一电极的表面为平面，所述层间绝缘层设置有第一过孔，所述第一过孔暴露部分所述第一电极；
有源层，所述有源层位于所述层间绝缘层背离所述第一电极一侧的表面，所述有源层包括源区、漏区以及位于所述源区与所述漏区之间的沟道区；所述第一电极在所述衬底的投影面积覆盖所述沟道区在所述衬底的投影面积，其中，所述有源层包括金属氧化物半导体材料或者碳纳米管；
栅极绝缘层和栅极，所述栅极绝缘层和所述栅极层叠设置在所述有源层背离所述层间绝缘层一侧的表面，其中，所述栅极绝缘层位于所述有源层和所述栅极之间；
第一钝化层，所述第一钝化层位于所述层间绝缘层背离所述第一电极一侧的表面，且延伸至所述有源层的表面，所述第一钝化层设置有第二过孔；
第二电极，所述第二电极位于所述第一钝化层背离所述栅极一侧的表面；
所述第一电极为源极，所述源区通过所述第一过孔与所述第一电极连接，第二电极为漏极，所述第二电极通过所述第二过孔与所述漏区连接；或者，所述第一电极为漏极，所述漏区通过所述第一过孔与所述第一电极连接，第二电极为源极，所述第二电极通过所述第二过孔与所述源区连接。
可选地，所述第一电极为源极，第二电极为漏极，所述第一电极的厚度大于所述第二电极的厚度；或者，所述第一电极为漏极，第二电极为源极，所述第二电极的厚度大于所述第一电极的厚度。
可选地，所述第一电极为源极，第二电极为漏极，所述第一电极在所述衬底的投影面积大于所述第二电极在所述衬底的投影面积，且所述第一电极在所述衬底的投影覆盖部分或全部所述沟道区在所述衬底的投影；或者，所述第一电极为漏极，第二电极为源极，所述第二电极在所述衬底的投影面积大于所述第一电极在所述衬底的投影面积， 且所述第二电极在所述衬底的投影覆盖部分或全部所述沟道区在所述衬底的投影。
可选地，所述栅极在所述衬底的投影和所述栅极绝缘层在所述衬底的投影重叠。
可选地，所述栅极在所述衬底的投影和所述沟道区在所述衬底的投影重叠，所述源区的导电率大于所述沟道区的导电率，且所述漏区的导电率大于所述沟道区的导电率。
可选地，所述有源层包括铟、锌、镓、锡、锆以及钽中的至少一种对应的氧化物MO和稀土氧化物RO组成的复合氧化物(MO) x(RO) y薄膜，其中，0<x<1，0.0001≤y≤0.2，x+y＝1，所述稀土氧化物包括氧化镨、氧化铽、氧化镝以及氧化镱中的至少一种。
第二方面，本发明实施例还提供了一种薄膜晶体管的制备方法，薄膜晶体管的制备方法包括：
提供衬底；
在所述衬底的表面形成第一电极；
在所述第一电极背离所述衬底一侧的表面形成层间绝缘层，其中，所述层间绝缘层背离所述第一电极的表面为平面，所述层间绝缘层设置有第一过孔，所述第一过孔暴露部分所述第一电极；
在所述层间绝缘层背离所述第一电极一侧的表面形成有源层，所述有源层包括源区、漏区以及位于所述源区与所述漏区之间的沟道区；所述第一电极在所述衬底的投影面积覆盖所述沟道区在所述衬底的投影面积，其中，所述有源层包括金属氧化物半导体材料或者碳纳米管；
在所述有源层背离所述层间绝缘层一侧的表面形成栅极绝缘层和栅极，其中，所述栅极绝缘层位于所述有源层和所述栅极之间；
在所述层间绝缘层背离所述第一电极一侧的表面形成第一钝化层，所述有源层、栅极绝缘层和栅极位于所述第一钝化层内，所述第一钝化层包括第二过孔；
在所述第一钝化层背离所述层间绝缘层一侧的表面形成第二电极；
所述第一电极为源极，所述源区通过所述第一过孔与所述第一电极连接，第二电极为漏极，所述第二电极通过所述第二过孔与所述有源层的漏区连接；或者，所述第一电极为漏极，所述漏区通过所述第一过孔与所述第一电极连接，第二电极为源极，所述第二电极通过所述第二过孔与所述有源层的源区连接。
可选地，在所述有源层背离所述层间绝缘层一侧的表面形成栅极绝缘层和栅极包括：
在所述沟道区背离所述层间绝缘层一侧的表面形成绝缘层；
在所述绝缘层背离所述有源层的表面形成导电层；
对所述导电层进行图形化处理，以形成所述栅极；
以所述栅极作为掩膜版，通过自对准工艺对所述绝缘层进行图形化处理，以形成所述栅极绝缘层，其中，所述栅极在所述衬底的投影和所述栅极绝缘层在所述衬底的投影重叠。
可选地，对所述导电层进行图形化处理，以形成所述栅极包括：
对所述导电层进行图形化处理，以形成在所述衬底的投影和所述沟道区在所述衬底的投影重叠的栅极；
以所述栅极作为掩膜版，通过自对准工艺对所述绝缘层进行图形化处理，以形成所述栅极绝缘层之后还包括：
以所述栅极和所述栅极绝缘层作为掩膜版，对所述源区和所述漏区进行高导化处理，其中，所述源区的导电率大于所述沟道区的导电率，且所述漏区的导电率大于所述沟道区的导电率。
可选地，在所述第一钝化层背离所述层间绝缘层一侧的表面形成第二电极之后还包括：
在所述第一钝化层背离所述层间绝缘层一侧的表面形成第二钝化层，所述第二钝化层位于所述第二电极背离所 述第一钝化层的表面，且延伸至所述第一钝化层的表面。
本发明通过将第一电极和第二电极位于不同层的设置，当第一电极和第二电极中的一个的形状需要作出改变时，无需同步改变另一个的形状，降低了第一电极和第二电极之间的关联度，进而降低了生产成本。其中，第一电极在衬底的投影面积覆盖沟道区在衬底的投影面积，使得第一电极可以反射衬底背离有源一侧表明的光线，避免沟道区内部在衬底背离有源层一侧表面的光线的作用下产生光生载流子，促使薄膜晶体管在饱和区表现出良好的输出特性。而且，层间绝缘层背离第一电极的表面为平面，保证了有源层的平坦性，进而提高了薄膜晶体管的电学性能的稳定性。本发明达到了降低源极和漏极之间的关联度和生产成本的效果。且有源层包括金属氧化物半导体材料或者碳纳米管，该薄膜晶体管可以表现出优异的器件性能。
附图说明
图1是本发明实施例提供的一种薄膜晶体管的结构示意图；
图2是本发明实施例提供的另一种薄膜晶体管的结构示意图；
图3是本发明实施例提供的另一种薄膜晶体管的结构示意图；
图4是本发明实施例提供的又一种薄膜晶体管的结构示意图；
图5是本发明实施例提供的又一种薄膜晶体管的结构示意图；
图6是本发明实施例提供的一种薄膜晶体管的制备方法的流程图；
图7是图6中S450包括的制备方法的流程图；
图8是本发明实施例提供的另一种薄膜晶体管的制备方法的流程图；
图9-图18是本发明实施例提供的一种薄膜晶体管的制备方法各步骤对应的剖面图。
具体实施方式
下面结合附图和实施例对本发明作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本发明，而非对本发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分而非全部结构。
图1是本发明实施例提供的一种薄膜晶体管的结构示意图，图2是本发明实施例提供的另一种薄膜晶体管的结构示意图，参见图1和图2，薄膜晶体管包括：衬底110；第一电极120，第一电极120位于衬底110的表面；层间绝缘层130，层间绝缘层130位于第一电极120背离衬底110一侧的表面，层间绝缘层130背离第一电极120的表面为平面，层间绝缘层130设置有第一过孔131，第一过孔131暴露部分第一电极120；有源层140，有源层140位于层间绝缘层130背离第一电极120一侧的表面，有源层140包括源区141、漏区142以及位于源区141与漏区142之间的沟道区143；第一电极120在衬底110的投影面积覆盖沟道区143在衬底110的投影面积，其中，有源层140包括金属氧化物半导体材料或者碳纳米管；栅极绝缘层150和栅极160，栅极绝缘层150和栅极160层叠设置在有源层140背离层间绝缘层130一侧的表面，其中，栅极绝缘层150位于有源层140和栅极160之间；第一钝化层170，第一钝化层170位于层间绝缘层130背离第一电极120一侧的表面，且延伸至有源层140的表面，第一钝化层170设置有第二过孔171；第二电极180，第二电极180位于第一钝化层170背离栅极160一侧的表面；参见图1，第一电极120为源极，源区141通过第一过孔131与第一电极120连接，第二电极180为漏极，第二电极 180通过第二过孔171与漏区142连接；或者，参见图2，第一电极120为漏极，漏区142通过第一过孔131与第一电极120连接，第二电极180为源极，第二电极180通过第二过孔171与源区141连接。
具体地，衬底110具有支撑和固定的作用。
有源层140包括金属氧化物半导体材料，该薄膜晶体管具有优良的压电、光电、气敏和压敏等性能。
有源层140包括碳纳米管。示例性的，碳纳米管的直径大于或等于1.45纳米，且小于或等于1.65纳米。碳纳米管的长度大于或等于0.7纳米，且小于或等于1.3纳米。碳纳米管的厚度大于或等于5纳米，且小于或等于15纳米。可选的，本实施例中碳纳米管包括单壁碳纳米管(SWCNTs)。单壁碳纳米管由于其优异的电荷传输性能、良好的溶液加工性，高柔性，优异的力学性能和高的导热性能，优异的机械稳定性和化学稳定性，在电子器件和光电子器件上有广泛的应用，例如，透明导电膜电极、薄膜晶体管、逻辑电路、柔性可穿戴电子器件、化学与生物传感器、超级电容器、太阳能电池等。其中，以单壁碳纳米管作为有源层材料所制备的薄膜晶体管电学性能优异、特征尺寸更小、稳定性好、散热更快、运行频率更高，表现出优异的器件性能及极大的应用发展潜力。
第一电极120和第二电极180不同层，即第一电极120和第二电极180非共面设计，以降低源极和漏极之间的关联度和生产成本。下面三种示例中，需要对第一电极120或者第二电极180的形状进行调整，具体如下：示例一：可知的，数据线与源极连接，当数据线上的驱动电流数值较大时，可以通过扩大源极的面积，来提高源极传输大驱动电流的能力。示例二：为了降低源极的电压降，进而降低功耗，可以提高源极的厚度，来降低移动电荷的横截面积，进而降低源极的电阻值，从而降低源极的压降和薄膜晶体管的功耗。示例三：为了避免衬底110侧的光对有源层照射形成光生载流子，需要将第一电极120在衬底110的投影面积覆盖沟道区143在衬底110的投影面积。
针对示例一和示例二中对于源极的形状的改变，本实施例提供的技术方案无需同步改变漏极的形状，若源极和漏极位于同层，则会出现加大漏极金属用量，增大成本的技术问题。
针对示例三中对于第一电极120形状的改变，本实施例提供的技术方案无需同步改变第二电极180的形状，若第一电极120和第二电极180位于同层，则会出现加大第二电极180金属用量，增大成本的技术问题。
需要说明的是，有源层140中靠近第一过孔131的部分可以是源区141，也可以漏区142。参见图1，当第一电极120为源极时，第二电极180为漏极，有源层140中靠近第一过孔131的部分是源区141，则有源层140靠近第二过孔171的部分是漏区142；参见图2，当第一电极120为漏极时，第二电极180为源极，有源层140中靠近第一过孔131的部分是漏区142，则有源层140靠近第二过孔171的部分是源区141。
其中，第一电极120在衬底110的投影面积覆盖沟道区143在衬底110的投影面积，使得第一电极120可以反射衬底110背离有源层140一侧表面的光线，避免沟道区143内部在衬底110背离有源层140一侧表面的光线的作用下产生光生载流子，促使薄膜晶体管在饱和区表现出良好的输出特性。而且层间绝缘层130背离第一电极120的表面为平面，保证了有源层140的平坦性，进而提高了薄膜晶体管的电学性能的稳定性。
本实施例的技术方案，通过将第一电极120和第二电极180位于不同层的设置，当第一电极120和第二电极180中的一个的形状需要作出改变时，无需同步改变另一个的形状，降低了第一电极120和第二电极180之间的关联度，进而降低了生产成本。其中，第一电极120在衬底110的投影面积覆盖沟道区143在衬底110的投影面积，使得第一电极120可以反射衬底110背离有源层140一侧表明的光线，避免沟道区143内部在衬底110背离有源层140一侧表面的光线的作用下产生光生载流子，促使薄膜晶体管在饱和区表现出良好的输出特性。而且，层间绝缘层130背离第一电极120的表面为平面，保证了有源层140的平坦性，进而提高了薄膜晶体管的电学性能的稳定性。本实 施例的技术方案解决了现有技术中源极和漏极同层设计，导致源极和漏极之间的关联度太大，进而导致薄膜晶体管的生产成本较大的问题，达到了降低源极和漏极之间的关联度和生产成本的效果。且有源层140包括金属氧化物半导体材料或者碳纳米管，该薄膜晶体管可以表现出优异的器件性能。
在上述技术方案的基础上，可选地，参见图1，第一电极120为源极，第二电极180为漏极，第一电极120的厚度大于第二电极180的厚度；或者，参见图2，第一电极120为漏极，第二电极180为源极，第二电极180的厚度大于第一电极120的厚度。
具体地，因为源极是与显示面板的数据线连接电极连接，所以设置源极的厚度大于漏极的厚度，可以使得电流流过的横截面积变大，从而减小整体电阻，使得源极的压降减小，达到降低功耗的效果。
可选地，参见图1，第一电极120为源极，第二电极180为漏极，第一电极120在衬底110的投影面积大于第二电极180在衬底110的投影面积，且第一电极120在衬底110的投影覆盖部分或全部沟道区143在衬底110的投影；或者，参见图2，第一电极120为漏极，第二电极180为源极，第二电极180在衬底110的投影面积大于第一电极120在衬底110的投影面积，且第二电极180在衬底110的投影覆盖部分或全部沟道区143在衬底110的投影。
具体地，源极在衬底110的投影面积大于漏极110在衬底110的投影面积，使得在保证源极在衬底110的投影覆盖沟道区143在衬底110的投影的同时，当数据线上的驱动电流数值较大时，将源极在衬底110的投影面积大于漏极110在衬底的投影面积来提高源极传输大驱动电流的能力。且上述技术方案，在改变源极形状的同时，不用改变漏极的形状，减小了制作成本。其中，第一电极120在衬底110的投影覆盖沟道区143的面积越大，对于降低衬底110侧的光对有源层140照射形成光生载流子的效果越好。
本实施例的技术方案通过将第一电极120和第二电极180位于不同层的设置，既可以为了降低源极的压降和功耗，将源极的厚度大于漏极的厚度；又可以为了当数据线上的驱动电流数值较大时，将源极在衬底110的投影面积大于漏极在衬底110的投影面积来提高源极传输大驱动电流的能力。
在上述技术方案的基础上，可选地，栅极160在衬底110的投影和栅极绝缘层150在衬底110的投影重叠。
具体地，栅极160在衬底110的投影和栅极绝缘层150在衬底110的投影重叠，使得在制备好栅极160之后，可以通过栅极160的自对准工艺，以栅极160作为掩膜版，对栅极绝缘层150所在的膜层进行图形化处理，以得到栅极绝缘层150，节省了掩膜版的数量，节省了薄膜晶体管的制作成本。
可选地，参见图1和图2，栅极160在衬底110的投影和沟道区143在衬底110的投影重叠，源区141的导电率大于沟道区143的导电率，且漏区142的导电率大于沟道区143的导电率。
具体地，栅极160在衬底110的投影和沟道区143在衬底110的投影重叠，在制备好栅极160和栅极绝缘层150之后，可以通过栅极160的自对准工艺，以栅极160作为掩膜版，对有源层140的源区141进行高导化处理，以使源区141的导电率大于沟道区143的导电率，并对有源层140的漏区142进行高导化处理，以使漏区142的导电率大于沟道区143的导电率，在节省了掩膜版的数量和降低薄膜晶体管的制作成本的基础上，使得源区141和源极之间形成良好的欧姆接触，并且使得漏区142和漏极之间形成良好的欧姆接触。
在上述实施方案的基础上，图3是本发明实施例提供的另一种薄膜晶体管的结构示意图，可选地，参见图3，薄膜晶体管还包括：第二钝化层190，第二钝化层190位于第二电极180背离第一钝化层170的表面，且延伸至第 一钝化层170的表面。
具体地，第二钝化层190具有防尘、防水和绝缘的作用，从而达到了保护第二电极180的效果，第二钝化层190可以包括二氧化硅(SiO 2)层和有机物，其中二氧化硅的厚度约为
Figure PCTCN2021124661-appb-000001
有机物的厚度约为1.2um。
进一步地，图4是本发明实施例提供的又一种薄膜晶体管的结构示意图，图5是本发明实施例提供的又一种薄膜晶体管的结构示意图。可选地，参见图4，薄膜晶体管还包括：阳极210和数据线连接电极220；第二钝化层190还包括第三过孔191和第四过孔192，第一钝化层170还包括第五过孔172，层间绝缘层130还包括第六过孔132；第一电极120为源极，第二电极180为漏极时，显示单元的阳极210位于第二钝化层190背离第一钝化层170一侧的表面，显示单元的阳极210通过第三过孔191与第二电极180连接；数据线连接电极220位于第二钝化层190背离第一钝化层170一侧的表面，数据线连接电极220通过第四过孔192、第五过孔172和第六过孔132与第一电极120连接。
可选地，参见图5，第一电极120为漏极，第二电极180为源极时，显示单元的阳极210通过第四过孔192、第五过孔172和第六过孔132与第一电极120连接；数据线连接电极220通过第三过孔191与第二电极180连接。本实施例提供的薄膜晶体管用于在饱和状态下为显示单元提供驱动电流。
可选地，参见图1、图2和图3，有源层140包括铟、锌、镓、锡、锆以及钽中的至少一种对应的氧化物MO和稀土氧化物RO组成的复合氧化物(MO) x(RO) y薄膜，其中，0<x<1，0.0001≤y≤0.2，x+y＝1，稀土氧化物包括氧化镨、氧化铽、氧化镝以及氧化镱中的至少一种。
具体地，有源层140可以为在金属氧化物(Metal Oxide,MO)半导体薄膜中掺杂少量稀土氧化物(Rare-earth Oxides,RO)组成的复合氧化物(MO) x(RO) y薄膜，其中，0<x<1，0.0001≤y≤0.2，且x+y＝1。稀土氧化物可以作为光稳定剂，从而增强有源层140的光稳定性，进而增强显示屏显示的均匀性和稳定性。
本发明实施例还提供了一种薄膜晶体管的制备方法。图6是本发明实施例提供的一种薄膜晶体管的制备方法的流程图。图9-图18是本发明实施例提供的一种薄膜晶体管的制备方法各步骤对应的剖面图。参见图6，以图1示出的薄膜晶体管为例进行说明，该薄膜晶体管的制备方法包括如下步骤：
S410、提供衬底。
参见图9，提供衬底110，示例性的，衬底110可以选择晶圆。
S420、在衬底的表面形成第一电极。
参见图10，可以通过电镀工艺在衬底110的表面形成第一电极120。具体的，首先在衬底10的表面形成覆盖衬底10的整层种子层。然后在种子层的表面形成图案化的电镀膜具层，在图案化的电镀掩膜层的表面继续通过电镀工艺形成预设厚度的电镀金属层。之后去除电镀膜具层，对种子层和电镀金属层进行图形化工艺，得到第一电极120。示例性的，种子层可以是金属钼和金属铜的叠层。其中，金属钼的膜层厚度大于为30纳米，金属铜的膜层厚度大约为300纳米。电镀金属层可以是电镀铜层，其中电镀铜层的厚度大于或等于300纳米，且小于或等于1000纳米。电镀膜具层可以包括SU-8、氮化硅(SiNx)以及氧化硅(SiO 2)中的任意一种。其中，SU-8是一种负性、环氧树脂型、近紫外线光刻胶。电镀膜具层的厚度大于或等于5微米，且小于或等于25微米。
示例性的，还可以通过磁控溅射工艺在在衬底110的表面形成金属层，然后通过第一掩膜版对金属层进行图形化工艺，以形成第一电极120。第一电极120可以是源极，也可以是漏极。示例性的，在图10中，第一电极120为源极。第一电极120为源极时，源极可以为金属钛和金属铜的叠层，示例性的，金属钛的厚度为
Figure PCTCN2021124661-appb-000002
金属铜 的厚度为
Figure PCTCN2021124661-appb-000003
第一电极120为漏极时，漏极可以包括金属钼，示例性的，金属钼的厚度为
Figure PCTCN2021124661-appb-000004
或者，漏极可以是金属铝和金属钼的叠层，示例性的，金属铝的厚度为
Figure PCTCN2021124661-appb-000005
金属钼的厚度为
Figure PCTCN2021124661-appb-000006
或者，漏极可以是金属钼和金属铜的叠层，示例性的，金属钼的厚度为
Figure PCTCN2021124661-appb-000007
金属铜的厚度为
Figure PCTCN2021124661-appb-000008
S430、在第一电极背离衬底一侧的表面形成层间绝缘层，其中，层间绝缘层背离第一电极的表面为平面，层间绝缘层设置有第一过孔，第一过孔暴露部分第一电极。
参见图11，在第一电极120背离衬底110一侧的表面形成层间绝缘层130，其中，层间绝缘层130背离第一电极120的表面为平面，可以保证在层间绝缘层130上形成的功能层的平坦性。通过第二掩膜版对层间绝缘层130进行图形化，形成第一过孔131。可选地，层间绝缘层130可以包括氮化硅(SiNx)和二氧化硅(SiO 2)的叠层，或者，层间绝缘层130包括二氧化硅(SiO 2)，示例性的，氮化硅的厚度为
Figure PCTCN2021124661-appb-000009
二氧化硅的厚度为
Figure PCTCN2021124661-appb-000010
二氧化硅的厚度为
Figure PCTCN2021124661-appb-000011
S440、在层间绝缘层背离第一电极一侧的表面形成有源层，有源层包括源区、漏区以及位于源区与漏区之间的沟道区；第一电极在衬底的投影面积覆盖沟道区在衬底的投影面积，其中，有源层包括金属氧化物半导体材料或者碳纳米管。
参见图12，在层间绝缘层130背离第一电极120一侧的表面形成有源层140，有源层140包括源区141、漏区142及位于源区141和漏区142之间的沟道区143。第一电极120在衬底110的投影面积覆盖沟道区143在衬底110的投影面积，使得第一电极120可以反射衬底110背离有源层140一侧表面的光线，避免沟道区143内部在衬底110背离有源层140一侧表面的光线的作用下产生光生载流子，促使薄膜晶体管在饱和区表现出良好的输出特性。
需要说明的是，通过第三掩膜版对有源层140所在的膜层进行图形化，以形成有源层140。
可选地，有源层140包括铟、锌、镓、锡、锆以及钽中的至少一种对应的氧化物MO和稀土氧化物RO组成的复合氧化物(MO) x(RO) y薄膜，其中，0<x<1，0.0001≤y≤0.2，x+y＝1，稀土氧化物包括氧化镨、氧化铽、氧化镝以及氧化镱中的至少一种。
具体地，有源层140可以为在金属氧化物(Metal Oxide,MO)半导体薄膜中掺杂少量稀土氧化物(Rare-earth Oxides,RO)组成的复合氧化物(MO) x(RO) y薄膜，其中，0<x<1，0.0001≤y≤0.2，且x+y＝1。稀土氧化物可以作为光稳定剂，从而增强有源层140的光稳定性，进而增强显示屏显示的均匀性和稳定性。
S450、在有源层背离层间绝缘层一侧的表面形成栅极绝缘层和栅极，其中，栅极绝缘层位于有源层和栅极之间。
参见图16，在有源层140背离层间绝缘层130一侧的表面形成栅极绝缘层150和栅极160，其中，栅极绝缘层150位于有源层140和栅极160之间。可选地，栅极绝缘层150包括二氧化硅，示例性的，二氧化硅的厚度为
Figure PCTCN2021124661-appb-000012
栅极160可以包括金属钼，示例性的，金属钼的厚度为
Figure PCTCN2021124661-appb-000013
或者，栅极160可以是金属铝和金属钼的叠层，金属铝的厚度为
Figure PCTCN2021124661-appb-000014
金属钼的厚度为
Figure PCTCN2021124661-appb-000015
或者，栅极160可以是金属钼和金属铜的叠层，示例性的，金属钼的厚度为
Figure PCTCN2021124661-appb-000016
金属铜的厚度为
Figure PCTCN2021124661-appb-000017
需要说明的是，通过第四掩膜版对栅极160所在的膜层进行图形化，以形成栅极160。
S460、在层间绝缘层背离第一电极一侧的表面形成第一钝化层，有源层、栅极绝缘层和栅极位于第一钝化层内，第一钝化层包括第二过孔。
参见图17，在层间绝缘层130背离第一电极120一侧的表面形成第一钝化层170。通过第五掩膜版对第一钝化层170进行图形化，形成第二过孔171。第一钝化层170可以包括二氧化硅(SiO 2)层和有机物，其中二氧化硅的厚度约为
Figure PCTCN2021124661-appb-000018
有机物的厚度约为1.2um。
S470、在第一钝化层背离层间绝缘层一侧的表面形成第二电极；第一电极为源极，源区通过第一过孔与第一电极连接，第二电极为漏极，第二电极通过第二过孔与有源层的漏区连接；或者，第一电极为漏极，漏区通过第一过孔与第一电极连接，第二电极为源极，第二电极通过第二过孔与有源层的源区连接。
参见图1，可以通过电镀工艺在第一钝化层170背离层间绝缘层130一侧的表面形成第二电极180。
第一电极120和第二电极180不同层，即第一电极120和第二电极180非共面设计，以降低源极和漏极之间的关联度和生产成本。下面三种示例中，需要对第一电极120或者第二电极180的形状进行调整，具体如下：示例一：可知的，数据线与源极连接，当数据线上的驱动电流数值较大时，可以通过扩大源极的面积，来提高源极传输大驱动电流的能力。示例二：为了降低源极的电压降，进而降低功耗，可以提高源极的厚度，来降低移动电荷的横截面积，进而降低源极的电阻值，从而降低源极的压降和薄膜晶体管的功耗。示例三：为了避免衬底110侧的光对有源层140照射形成光生载流子，需要将第一电极120在衬底110的投影面积覆盖沟道区143在衬底110的投影面积。
针对示例一和示例二中对于源极的形状的改变，本实施例提供的技术方案无需同步改变漏极的形状，若源极和漏极位于同层，则会出现加大漏极金属用量，增大成本的技术问题。
针对示例三中对于第一电极120形状的改变，本实施例提供的技术方案无需同步改变第二电极180的形状，若第一电极120和第二电极180位于同层，则会出现加大第二电极180金属用量，增大成本的技术问题。
需要说明的是，通过第六掩膜版对第二电极180所在膜层进行图形化处理，以形成第二电极180。
其中，参见图1，第一电极120为源极，源区141通过第一过孔131与第一电极120连接，第二电极180为漏极，第二电极120通过第二过孔171与有源层140的漏区142连接；或者，参见图2，第一电极120为漏极，漏区142通过第一过孔131与第一电极120连接，第二电极180为源极，第二电极180通过第二过孔171与有源层140的源区141连接。需要说明的是，图2示出的薄膜晶体管的制备方法和图1示出的薄膜晶体管的制备方法类似，此处不再赘述。
具体地，有源层140中靠近第一过孔131的部分可以是源区141，也可以漏区142，参见图1，当第一电极120为源极时，第二电极180为漏极，有源层140中靠近第一过孔131的部分是源区141，则有源层140靠近第二过孔171的部分是漏区142；参见图2，当第一电极120为漏极时，第二电极180为源极，有源层140中靠近第一过孔131的部分是漏区142，则有源层140靠近第二过孔171的部分是源区141。
可选地，参见图1，第一电极120为源极，第二电极180为漏极，第一电极120的厚度大于第二电极180的厚度；或者，参见图2，第一电极120为漏极，第二电极180为源极，第二电极180的厚度大于第一电极120的厚度。
具体地，因为源极是与显示面板的数据线连接电极连接，所以设置源极的厚度大于漏极的厚度，可以使得电流流过的横截面积变大，从而减小整体电阻，使得源极的压降减小，达到降低功耗的效果。需要说明的是，在S420中，在衬底110的表面形成第一电极120时，示例性的，可以通过控制金属溅射工艺的成膜时间来控制第一电极120的成膜厚度。在S470中，在第一钝化层170背离层间绝缘层130一侧的表面形成第二电极180，示例性的，可以通过控制金属溅射工艺的成膜时间来控制第二电极180的成膜厚度。
可选地，参见图1，第一电极120为源极，第二电极180为漏极，第一电极120在衬底110的投影面积大于第二电极180在衬底110的投影面积，且第一电极120在衬底110的投影覆盖部分或全部沟道区143在衬底110的投影；或者，参见图2，第一电极120为漏极，第二电极180为源极，第二电极180在衬底110的投影面积大于第一电极120在衬底110的投影面积，且第二电极180在衬底110的投影覆盖部分或全部沟道区143在衬底110的投影。
需要说明的是，可以通过图形化处理，形成投影面积不同的第一电极120和第二电极180。
具体地，源极在衬底110的投影面积大于漏极110在衬底的投影面积，使得在保证源极在衬底110的投影覆盖沟道区143在衬底110的投影的同时，当数据线上的驱动电流数值较大时，将源极在衬底110的投影面积大于漏极110在衬底的投影面积来提高源极传输大驱动电流的能力。且上述技术方案，在改变源极形状的同时，不用改变漏极的形状，减小了制作成本。其中，第一电极120在衬底110的投影覆盖沟道区143的面积越大，对于降低衬底110侧的光对有源层140照射形成光生载流子的效果越好。
本实施例的技术方案通过将第一电极120和第二电极180位于不同层的设置，既可以为了降低源极的压降和功耗，将源极的厚度大于漏极的厚度；又可以为了当数据线上的驱动电流数值较大时，将源极在衬底110的投影面积大于漏极110在衬底的投影面积来提高源极传输大驱动电流的能力。
本实施例的技术方案，通过将第一电极120和第二电极180位于不同层的设置，当第一电极120和第二电极180中的一个的形状需要作出改变时，无需同步改变另一个的形状，降低了第一电极120和第二电极180之间的关联度，进而降低了生产成本。其中，第一电极120在衬底110的投影面积覆盖沟道区143在衬底110的投影面积，使得第一电极120可以反射衬底110背离有源层140一侧表面的光线，避免沟道区143内部在衬底110背离有源层140一侧表面的光线的作用下产生光生载流子，促使薄膜晶体管在饱和区表现出良好的输出特性。而且，层间绝缘层130背离第一电极120的表面为平面，保证了有源层140的平坦性，进而提高了薄膜晶体管的电学性能的稳定性。本实施例的技术方案解决了现有技术中源极和漏极同层设计，导致源极和漏极之间的关联度太大，进而导致薄膜晶体管的生产成本较大的问题，达到了降低源极和漏极之间的关联度和生产成本的效果。且有源层140包括金属氧化物半导体材料或者碳纳米管，该薄膜晶体管可以表现出优异的器件性能。
需要说明的是，通过电镀工艺形成厚度较厚或者面积较大的电极层，其形成效率高，制备成本低。
下面具体介绍栅极绝缘层159和栅极160的制备方法，图7是图6中S450包括的制备方法的流程图。
在上述实施方案的基础上，可选地，参见图7，S450、在有源层背离层间绝缘层一侧的表面形成栅极绝缘层和栅极包括：
S451、在沟道区背离层间绝缘层一侧的表面形成绝缘层。
参见图13，在沟道区143背离层间绝缘层130一侧的表面形成绝缘层151。
S452、在绝缘层背离有源层的表面形成导电层。
参见图14，在绝缘层151背离有源层140的表面形成导电层161。
S453、对导电层进行图形化处理，以形成栅极。
参见图15，通过第四掩膜版对导电层161进行图形化处理，以形成栅极160。
S454、以栅极作为掩膜版，通过自对准工艺对绝缘层进行图形化处理，以形成栅极绝缘层，其中，栅极在衬底的投影和栅极绝缘层在衬底的投影重叠。
参见图16，以栅极160作为掩膜版，通过自对准工艺对绝缘层151进行图形化处理，以形成栅极绝缘层150，其中，栅极160在衬底110的投影和栅极绝缘层150在衬底110的投影重叠。
具体地，栅极160在衬底110的投影和栅极绝缘层150在衬底110的投影重叠，使得在制备好栅极160之后，可以通过栅极160的自对准工艺，以栅极160作为掩膜版，对栅极绝缘层150所在的膜层进行图形化处理，以得到栅极绝缘层150，节省了掩膜版的数量，节省了薄膜晶体管的制作成本。
可选地，在上述实施方案的技术上，S453对导电层进行图形化处理，以形成栅极包括：
对导电层进行图形化处理，以形成在衬底的投影和沟道区在衬底的投影重叠的栅极。
参见图15，通过第四掩膜版对导电层161进行图形化处理，以形成在衬底110的投影和沟道区143在衬底110的投影重叠的栅极160。
S454、以栅极作为掩膜版，通过自对准工艺对绝缘层进行图形化处理，以形成栅极绝缘层之后还包括：
以栅极和栅极绝缘层作为掩膜版，对源区和漏区进行高导化处理，其中，源区的导电率大于沟道区的导电率，且漏区的导电率大于沟道区的导电率。
参见图19，以栅极160和栅极绝缘层150作为掩膜版，对源区141和漏区142进行高导化处理，其中，源区141的导电率大于沟道区143的导电率，且漏区142的导电率大于沟道区143的导电率。
具体地，栅极160在衬底110的投影和沟道区143在衬底110的投影重叠，在制备好栅极160和栅极绝缘层150之后，可以通过栅极160的自对准工艺，以栅极160作为掩膜版，对有源层140的源区141进行高导化处理，以使源区141的导电率大于沟道区143的导电率，并对有源层140的漏区142进行高导化处理，以使漏区142的导电率大于沟道区143的导电率，在节省了掩膜版的数量和降低薄膜晶体管的制作成本的基础上，使得源区141和源极之间形成良好的欧姆接触，并且使得漏区142和漏极之间形成良好的欧姆接触。
在上述实施方案的基础上，图8是本发明实施例提供的另一种薄膜晶体管的制备方法的流程图，可选地，参见图8，以图1示出的薄膜晶体管为例进行说明，该薄膜晶体管的制备方法包括如下步骤：
S610、提供衬底。
参见图9，提供衬底110。
S620、在衬底的表面形成第一电极。
参见图10，在衬底110的表面形成第一电极120。
S630、在第一电极背离衬底一侧的表面形成层间绝缘层，其中，层间绝缘层背离第一电极的表面为平面，层间绝缘层设置有第一过孔，第一过孔暴露部分第一电极。
参见图11，在第一电极120背离衬底110一侧的表面形成层间绝缘层130，其中，层间绝缘层130背离第一电极120的表面为平面。
S640、在层间绝缘层背离第一电极一侧的表面形成有源层，有源层包括源区、漏区以及位于源区与所述漏区之间的沟道区；第一电极在衬底的投影面积覆盖沟道区在衬底的投影面积，其中，有源层包括金属氧化物半导体材料或者碳纳米管。
参见图12，在层间绝缘层130背离第一电极120一侧的表面形成有源层140，有源层140包括源区141、漏区142及位于源区141和漏区142之间的沟道区143。
S650、在有源层背离层间绝缘层一侧的表面形成栅极绝缘层和栅极，其中，栅极绝缘层位于有源层和栅极之间。
参见图16，在有源层140背离层间绝缘层130一侧的表面形成栅极绝缘层150和栅极160，其中，栅极绝缘层150位于有源层140和栅极160之间。
S660、在层间绝缘层背离第一电极一侧的表面形成第一钝化层，有源层、栅极绝缘层和栅极位于第一钝化层内，第一钝化层包括第二过孔。
参见图17，在层间绝缘层130背离第一电极120一侧的表面形成第一钝化层170。通过第五掩膜版对第一钝化层170进行图形化，形成第二过孔171。
S670、在第一钝化层背离层间绝缘层一侧的表面形成第二电极。
其中，第一电极为源极，源区通过第一过孔与第一电极连接，第二电极为漏极，第二电极通过第二过孔与有源层的漏区连接；或者，第一电极为漏极，漏区通过第一过孔与第一电极连接，第二电极为源极，第二电极通过第二过孔与有源层的源区连接。
参见图1，可以通过电镀工艺在第一钝化层170背离层间绝缘层130一侧的表面形成第二电极180。
S680、在第一钝化层背离层间绝缘层一侧的表面形成第二钝化层，第二钝化层位于第二电极背离第一钝化层的表面，且延伸至第一钝化层的表面。
继续参考图3，在第一钝化层170背离层间绝缘层130一侧的表面形成第二钝化层190，第二钝化层190位于第二电极180背离第一钝化层170的表面，且延伸至第一钝化层170的表面。
具体地，第二钝化层190具有防尘、防水和绝缘的作用，从而达到了保护第二电极180的效果，第二钝化层190可以包括二氧化硅(SiO 2)层和有机物，其中二氧化硅的厚度约为
Figure PCTCN2021124661-appb-000019
有机物的厚度约为1.2um。
进一步的，继续参考图4，在第二钝化层190背离第一钝化层170一侧的表面形成阳极210和数据线连接电极220，第一电极120为源极，第二电极180为漏极时，显示单元的阳极210通过第三过孔191与第二电极180连接，数据线连接电极220通过第四过孔192、第五过孔172和第六过孔132与第一电极120连接。
可选地，以图4为例进行说明，第六过孔132的形成过程如下：可以通过第二掩膜版对层间绝缘层130进行图形化，形成第一过孔131的同时形成第六过孔132。可选地，第五过孔172的形成过程如下：可以是通过第五掩膜版对第一钝化层170进行图形化，形成第二过孔171的同时形成第五过孔172。第三过孔191和第四过孔192的形成过程如下：通过第七掩膜版对第二钝化层190进行图形化处理，以形成第三过孔191和第四过孔192。具体地，通过第八掩膜版对阳极210和数据线连接电极220所在膜层进行图案化处理，以形成阳极210和数据线连接电极220。
继续参考图5，第一电极120为漏极，第二电极180为源极时，显示单元的阳极210通过第四过孔192、第五过孔172和第六过孔132与第一电极120连接；数据线连接电极220通过第三过孔191与第二电极连接。本实施例提供的薄膜晶体管用于在饱和状态下为显示单元提供驱动电流。
需要说明的是，图5示出的第六过孔132、第一过孔131和第五过孔172的形成过程和图4示出的第六过孔132、第一过孔131和第五过孔172的形成过程类似，此处不再赘述。
注意，上述仅为本发明的较佳实施例及所运用技术原理。本领域技术人员会理解，本发明不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本发明的保护范围。因此，虽然通过以上实施例对本发明进行了较为详细的说明，但是本发明不仅仅限于以上实施例，在不脱离本发明构思的情况下，还可以包括更多其他等效实施例，而本发明的范围由所附的权利要求范围决定。

Claims (10)

  1. 一种薄膜晶体管，其特征在于，包括：
    衬底；
    第一电极，所述第一电极位于所述衬底的表面；
    层间绝缘层，所述层间绝缘层位于所述第一电极背离所述衬底一侧的表面，所述层间绝缘层背离所述第一电极的表面为平面，所述层间绝缘层设置有第一过孔，所述第一过孔暴露部分所述第一电极；
    有源层，所述有源层位于所述层间绝缘层背离所述第一电极一侧的表面，所述有源层包括源区、漏区以及位于所述源区与所述漏区之间的沟道区；所述第一电极在所述衬底的投影面积覆盖所述沟道区在所述衬底的投影面积，其中，所述有源层包括金属氧化物半导体材料或者碳纳米管；
    栅极绝缘层和栅极，所述栅极绝缘层和所述栅极层叠设置在所述有源层背离所述层间绝缘层一侧的表面，其中，所述栅极绝缘层位于所述有源层和所述栅极之间；
    第一钝化层，所述第一钝化层位于所述层间绝缘层背离所述第一电极一侧的表面，且延伸至所述有源层的表面，所述第一钝化层设置有第二过孔；
    第二电极，所述第二电极位于所述第一钝化层背离所述栅极一侧的表面；
    所述第一电极为源极，所述源区通过所述第一过孔与所述第一电极连接，第二电极为漏极，所述第二电极通过所述第二过孔与所述漏区连接；或者，所述第一电极为漏极，所述漏区通过所述第一过孔与所述第一电极连接，第二电极为源极，所述第二电极通过所述第二过孔与所述源区连接。
  2. 权利要求1所述的薄膜晶体管，其特征在于，所述第一电极为源极，第二电极为漏极，所述第一电极的厚度大于所述第二电极的厚度；或者，所述第一电极为漏极，第二电极为源极，所述第二电极的厚度大于所述第一电极的厚度。
  3. 根据权利要求1或2所述的薄膜晶体管，其特征在于，所述第一电极为源极，第二电极为漏极，所述第一电极在所述衬底的投影面积大于所述第二电极在所述衬底的投影面积，且所述第一电极在所述衬底的投影覆盖部分或全部所述沟道区在所述衬底的投影；或者，所述第一电极为漏极，第二电极为源极，所述第二电极在所述衬底的投影面积大于所述第一电极在所述衬底的投影面积，且所述第二电极在所述衬底的投影覆盖部分或全部所述沟道区在所述衬底的投影。
  4. 根据权利要求1所述的薄膜晶体管，其特征在于，所述栅极在所述衬底的投影和所述栅极绝缘层在所述衬底的投影重叠。
  5. 根据权利要求4所述的薄膜晶体管，其特征在于，所述栅极在所述衬底的投影和所述沟道区在所述衬底的投影重叠，所述源区的导电率大于所述沟道区的导电率，且所述漏区的导电率大于所述沟道区的导电率。
  6. 根据权利要求1所述的薄膜晶体管，其特征在于，所述有源层包括铟、锌、镓、锡、锆以及钽中的至少一种对应的氧化物MO和稀土氧化物RO组成的复合氧化物(MO)x(RO)y薄膜，其中，0<x<1，0.0001≤y≤0.2，x+y＝1，所述稀土氧化物包括氧化镨、氧化铽、氧化镝以及氧化镱中的至少一种。
  7. 一种薄膜晶体管的制备方法，其特征在于，包括：
    提供衬底；
    在所述衬底的表面形成第一电极；
    在所述第一电极背离所述衬底一侧的表面形成层间绝缘层，其中，所述层间绝缘层背离所述第一电极的表面为 平面，所述层间绝缘层设置有第一过孔，所述第一过孔暴露部分所述第一电极；
    在所述层间绝缘层背离所述第一电极一侧的表面形成有源层，所述有源层包括源区、漏区以及位于所述源区与所述漏区之间的沟道区；所述第一电极在所述衬底的投影面积覆盖所述沟道区在所述衬底的投影面积，其中，所述有源层包括金属氧化物半导体材料或者碳纳米管；
    在所述有源层背离所述层间绝缘层一侧的表面形成栅极绝缘层和栅极，其中，所述栅极绝缘层位于所述有源层和所述栅极之间；
    在所述层间绝缘层背离所述第一电极一侧的表面形成第一钝化层，所述有源层、栅极绝缘层和栅极位于所述第一钝化层内，所述第一钝化层包括第二过孔；
    在所述第一钝化层背离所述层间绝缘层一侧的表面形成第二电极；
    所述第一电极为源极，所述源区通过所述第一过孔与所述第一电极连接，第二电极为漏极，所述第二电极通过所述第二过孔与所述有源层的漏区连接；或者，所述第一电极为漏极，所述漏区通过所述第一过孔与所述第一电极连接，第二电极为源极，所述第二电极通过所述第二过孔与所述有源层的源区连接。
  8. 根据权利要求7所述的薄膜晶体管的制备方法，其特征在于，在所述有源层背离所述层间绝缘层一侧的表面形成栅极绝缘层和栅极包括：
    在所述沟道区背离所述层间绝缘层一侧的表面形成绝缘层；
    在所述绝缘层背离所述有源层的表面形成导电层；
    对所述导电层进行图形化处理，以形成所述栅极；
    以所述栅极作为掩膜版，通过自对准工艺对所述绝缘层进行图形化处理，以形成所述栅极绝缘层，其中，所述栅极在所述衬底的投影和所述栅极绝缘层在所述衬底的投影重叠。
  9. 根据权利要求8所述的薄膜晶体管的制备方法，其特征在于，对所述导电层进行图形化处理，以形成所述栅极包括：
    对所述导电层进行图形化处理，以形成在所述衬底的投影和所述沟道区在所述衬底的投影重叠的栅极；
    以所述栅极作为掩膜版，通过自对准工艺对所述绝缘层进行图形化处理，以形成所述栅极绝缘层之后还包括：
    以所述栅极和所述栅极绝缘层作为掩膜版，对所述源区和所述漏区进行高导化处理，其中，所述源区的导电率大于所述沟道区的导电率，且所述漏区的导电率大于所述沟道区的导电率。
  10. 根据权利要求7所述的薄膜晶体管的制备方法，其特征在于，在所述第一钝化层背离所述层间绝缘层一侧的表面形成第二电极之后还包括：
    在所述第一钝化层背离所述层间绝缘层一侧的表面形成第二钝化层，所述第二钝化层位于所述第二电极背离所述第一钝化层的表面，且延伸至所述第一钝化层的表面。
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