WO2013075551A1 - 电子纸有源基板及其制造方法和电子纸显示屏 - Google Patents

电子纸有源基板及其制造方法和电子纸显示屏 Download PDF

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Publication number
WO2013075551A1
WO2013075551A1 PCT/CN2012/082361 CN2012082361W WO2013075551A1 WO 2013075551 A1 WO2013075551 A1 WO 2013075551A1 CN 2012082361 W CN2012082361 W CN 2012082361W WO 2013075551 A1 WO2013075551 A1 WO 2013075551A1
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Prior art keywords
common electrode
layer
passivation layer
electronic paper
forming step
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PCT/CN2012/082361
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English (en)
French (fr)
Inventor
张卓
盖翠丽
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2014542686A priority Critical patent/JP6280042B2/ja
Priority to KR1020127031145A priority patent/KR101431655B1/ko
Priority to US13/703,469 priority patent/US8861065B2/en
Priority to EP12788101.9A priority patent/EP2784575B1/en
Publication of WO2013075551A1 publication Critical patent/WO2013075551A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G02F1/1676—Electrodes
    • G02F1/16766—Electrodes for active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/166—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect
    • G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G02F1/1676—Electrodes
    • G02F1/16761—Side-by-side arrangement of working electrodes and counter-electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G02F1/1676—Electrodes
    • G02F1/16762—Electrodes having three or more electrodes per pixel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G02F1/16756—Insulating layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • Embodiments of the present invention relate to an electronic paper active substrate, a method of fabricating the same, and an electronic paper display. Background technique
  • Electrophoresis type electronic paper is one of which realizes image display by using charged particles containing black particles and white particles to move up and down in an applied electric field.
  • active matrix drive technology is required for electronic paper to display text information.
  • TFT Thin Film Transistor
  • Electrophoresis type electronic paper is generally formed by pairing an active substrate and an electrophoretic substrate.
  • the electrophoretic substrate is provided with a common electrode and is coated with an electrophoretic particle layer;
  • the active substrate is responsible for inputting a data signal to perform real-time control on the displayed image, and is composed of a plurality of pixel units arranged in a matrix form.
  • electrophoresis type electronic paper The advantages of electrophoresis type electronic paper are better performance in contrast, brightness and other aspects, low power consumption, light weight and easy to be thinned, and many shapes can be prepared.
  • the disadvantage is that the electrophoresis type electronic paper display screen needs to be higher. The voltage, high voltage, and large leakage current. Therefore, in order to maintain charge stability, it is generally necessary to design a large storage capacitor.
  • FIG. 1 A cross-sectional structural view of an active substrate in a conventional electronic paper pixel (sub-pixel) structure is shown in FIG.
  • the larger the ⁇ the larger the capacitance; the larger the area, the larger the capacitance; the closer the distance, the larger the capacitance.
  • the source/drain 5 and the common electrode 3 correspond to the two plates of the capacitor, and the gate insulating layer 4 is an insulating layer.
  • ⁇ is related to the insulating material filled between the two plates of the capacitor, when the insulating material is selected, ⁇ is basically a constant value.
  • one method is to increase the area where the source drain and the common electrode face each other, but the pixel area itself is limited, so the effect of the method is limited; another method is to reduce the gate The thickness of the insulating layer, but the gate insulating layer is too thin, may cause short-circuit or breakdown of the gate edge and the source and drain, and may affect the performance of the TFT (Thin Film Field Effect Transistor).
  • TFT Thin Film Field Effect Transistor
  • One of the technical problems to be solved by the embodiments of the present invention is to provide the above-mentioned defects in the prior art, and to provide an electronic paper active substrate capable of effectively improving the storage capacitance without affecting the performance of the TFT device and using the electronic device.
  • An embodiment of the present invention provides an electronic paper active substrate, including: a base substrate, a gate, a first common electrode, a second common electrode, a gate insulating layer, an active layer, a source and a drain, and a passivation a layer, a resin passivation layer, and a pixel electrode layer; the gate electrode and the first common electrode are disposed on the base substrate, and the gate insulating layer and the active layer are sequentially disposed on the gate a source drain, a passivation layer, a resin passivation layer, and a pixel electrode layer; the gate electrode layer, the source and drain electrodes, the passivation layer, the second common electrode, and the resin passivation layer are sequentially disposed on the first common electrode And a pixel electrode layer, and the first common electrode and the second common electrode are electrically connected.
  • the first common electrode and the second common electrode are arranged in parallel by passing through the gate insulating layer and the second via of the passivation layer Electrically connected to each other.
  • the material of the second common electrode is metal or indium tin oxide, or a combination of metal or indium tin oxide.
  • the second common electrode contains a metal.
  • the area of the first common electrode is The ratio of the area of the pixel electrode in the corresponding pixel unit of the pixel electrode layer is not less than 30%.
  • the ratio of the area of the second common electrode to the area of the pixel electrode in the corresponding pixel unit of the pixel electrode layer is not less than 30%.
  • a first via hole is formed in the resin passivation layer and the passivation layer above the source drains of the first common electrode and the second common electrode, So that the pixel electrode layer is connected to the source and drain through the first via.
  • a second common electrode is added between the passivation layer and the resin passivation layer, and the second common electrode is passed through the second via A common electrode is connected, so that the capacitance originally formed by the source drain and the single common electrode becomes a capacitance formed by the source and drain electrodes and the first and second common electrodes, so that the storage capacitance is greatly increased (nearly increases) Doubled, the storage capacitor limit of electronic paper is greatly expanded.
  • Another embodiment of the present invention provides an electronic paper active substrate manufacturing method, including: a gate and a first common electrode forming step for forming a gate and a first common electrode on a base substrate; a layer forming step of forming a gate insulating layer on the gate, the first common electrode, and the surface of the base substrate; an active layer forming step of forming an active layer on the gate insulating layer; and a source/drain forming step for Forming a source drain on the active layer, wherein the source and drain electrodes are at least partially disposed on the gate insulating layer on the first common electrode, and the source and drain electrodes do not completely cover the first common electrode; and the passivation layer forming step is performed Forming a passivation layer on the structure obtained in the source-drain formation step; a second via forming step of forming a second via hole penetrating the passivation layer and the gate insulating layer, thereby Exposing a portion of the first common electrode through the second via hole; a second common electrode
  • the electronic paper active substrate manufacturing method further includes: a resin passivation layer forming step of forming a resin passivation layer on the surface of the structure obtained by the second common electrode forming step; the first via formation a step of forming a first via hole over the source drain of the first common electrode and the second common electrode to pass through the resin passivation layer and the passivation layer to expose a portion of the source and drain; and And an electrode layer forming step of forming a pixel electrode layer on the surface of the structure obtained after the first via forming step, wherein the pixel electrode layer is connected to the exposed portion of the source and drain through the first via hole.
  • the electronic paper active substrate manufacturing method further includes: a first via first shape And a step of forming a first via lower portion in the passivation layer after the passivation layer forming step.
  • the resin passivation layer forming step causes the resin passivation layer to fill the first via lower portion; and the first via formation step further a first via second forming step for forming the first via in the resin passivation layer, the first via including the first via lower portion, thereby the first via And exposing a portion of the source and drain electrodes; and the pixel electrode layer forming step is configured to form a pixel electrode layer on the surface of the structure obtained by the first via first forming step, wherein the pixel electrode layer passes the first pass A hole is connected to the exposed portion of the source drain.
  • a second common electrode is added between the passivation layer and the resin passivation layer, and the second common electrode can be connected to the first common electrode through the second via hole.
  • the capacitance originally formed by the source drain and the single common electrode becomes a capacitance formed by the source and drain electrodes and the first and second common electrodes, so that the storage capacitance is greatly increased (approximately doubled).
  • the storage capacitor limit of electronic paper is greatly expanded.
  • Another embodiment of the present invention provides an electronic paper display screen comprising the above described electronic paper active substrate.
  • the electronic paper display can also achieve the beneficial technical effects that the electronic paper active substrate can achieve. That is, by adding a second common electrode between the passivation layer and the resin passivation layer, and electrically connecting the second common electrode to the first common electrode through the second via, so that the source and drain are originally
  • the capacitance formed by a single common electrode becomes a capacitance formed by the source and drain electrodes and the first and second common electrodes, which nearly doubles the area of the capacitor plate, so that the storage capacitance is greatly increased (nearly doubled) ), the storage capacitor limit of electronic paper is greatly expanded without affecting the performance of the TFT device.
  • FIG. 1 is a cross-sectional structural view of a prior art electronic paper active substrate.
  • FIG. 2 is a schematic cross-sectional view showing a gate electrode and a first common electrode in an electronic paper active substrate according to a first embodiment of the present invention.
  • 3 is a schematic cross-sectional view showing the formation of a gate insulating layer in an electronic paper active substrate according to a first embodiment of the present invention.
  • Fig. 4 is a cross-sectional view showing the formation of source and drain electrodes in the electronic paper active substrate of the first embodiment of the present invention.
  • Fig. 5 is a cross-sectional view showing the formation of a passivation layer in the electronic paper active substrate of the first embodiment of the present invention.
  • Fig. 6 is a schematic cross-sectional view showing the second via hole in the electronic paper active substrate of the first embodiment of the present invention.
  • Fig. 7 is a schematic cross-sectional view showing the second common electrode in the electronic paper active substrate of the first embodiment of the present invention.
  • Fig. 8 is a schematic cross-sectional view showing the formation of a resin passivation layer in the electronic paper active substrate of the first embodiment of the present invention.
  • Fig. 9 is a schematic cross-sectional view showing the first via hole in the electronic paper active substrate of the first embodiment of the present invention.
  • Figure 10 is a schematic cross-sectional view showing the formation of a pixel electrode layer in an electronic paper active substrate according to a first embodiment of the present invention.
  • Figure 11 is a plan view of one possible electronic paper active substrate of Figure 10.
  • Figure 12 is a flow chart showing a method of manufacturing an electronic paper active substrate according to a first embodiment of the present invention.
  • Figure 13 is a cross-sectional view showing the second via hole and the first via lower portion simultaneously formed in the electronic paper active substrate according to the second embodiment of the present invention.
  • the electronic paper active substrate of the embodiment of the invention includes: a base substrate, a gate, a first common electrode, a gate insulating layer, an active layer, a source and a drain, a passivation layer, a second common electrode, and a resin passivation layer And a pixel electrode layer.
  • the active substrate includes a plurality of gate lines 12 and a plurality of data lines 13 which cross each other to define a plurality of pixel units arranged in an array.
  • each pixel unit includes a thin film transistor as a switching element, and a gate of the thin film transistor is connected or integrally formed with a corresponding gate line, and one of the source and the drain is connected or integrated with a corresponding data line, and the other source and drain are The pixel electrode is connected.
  • the following description is for a single pixel unit, but other pixel units are equally applicable.
  • the gate electrode and the first common electrode are directly disposed on the base substrate.
  • a gate insulating layer covers the gate and the first common electrode, and covers a portion of the surface of the base substrate that is not covered by the gate and the first common electrode.
  • a portion of the source drain is disposed on a portion of the gate insulating layer on the first common electrode (ie, the gate insulating layer over the first common electrode is not completely covered by the source and drain), and the source and drain are further A portion may also be disposed on a portion of the gate insulating layer on the base substrate.
  • An active layer (not shown) is disposed between the gate insulating layer and the source and drain electrodes.
  • a portion of the passivation layer is disposed on a portion of the gate insulating layer on the first common electrode, and a portion of the passivation layer covers the source drain, the gate insulating layer over the gate, and a nearby region.
  • a second common electrode is disposed on the passivation layer.
  • first common electrode and the second common electrode are connected to each other through a second via hole that passes through the gate insulating layer and the passivation layer.
  • the resin passivation layer covers the second common electrode, and the resin passivation layer also covers a portion of the gate insulating layer.
  • the pixel electrode layer covers the resin passivation layer.
  • a gate insulating layer, an active layer, a source and a drain, a passivation layer, a resin passivation layer, and a pixel electrode layer are sequentially disposed on the gate; and a gate insulating layer is sequentially disposed on the first common electrode.
  • a source drain, a passivation layer, a second common electrode, a resin passivation layer, and a pixel electrode layer are sequentially disposed on the first common electrode.
  • the surface of the electronic paper active substrate is formed with a first via hole.
  • the gate electrode, the gate insulating layer, the active layer, and the source and drain electrodes constitute a thin film field effect transistor (TFT).
  • the pixel electrode layer includes a pixel electrode of each pixel unit for display of the corresponding pixel.
  • a resin passivation layer can be used to reduce parasitic capacitance to increase the aperture ratio.
  • the thin film field effect transistor is used as a switching element for controlling whether or not the pixel electrode is powered.
  • the first common electrode and the second common electrode are common electrodes for forming a storage capacitor in the corresponding pixel unit on the active substrate. It can be seen that a conductive layer (second common electrode) is added between the passivation layer and the resin passivation layer, and the conductive layer is conducted through the first common electrode through a via (second via). Therefore, the area of one capacitor plate of the capacitor is expanded from a single common electrode to two common electrodes, so that the area of the capacitor plate is nearly doubled, so that the first common electrode and the second common electrode together with the source and drain electrodes A larger capacitance is formed, which greatly increases the storage capacitance of the pixel.
  • first common electrode and the second common electrode are arranged in parallel so that the effect of increasing the storage capacitance is better.
  • the materials of the first common electrode and the second common electrode may be selected from the same materials or different materials.
  • the second common electrode may be a metal such as Mo, MO/Al/Mo, Mo/Al/Nd/Mo, or the like, or indium tin oxide (ITO), or a combination of metal or indium tin oxide.
  • the second common electrode is, for example, a metal.
  • the ratio of the area of the first common electrode to the area of the pixel electrode in the corresponding pixel unit is not less than 30%.
  • the ratio of the area of the second common electrode to the area of the pixel electrode in the corresponding pixel unit is not less than 30%.
  • Figure 12 is a flow chart showing a method of manufacturing an electronic paper active substrate according to a first embodiment of the present invention. As shown in FIG. 12, the electronic paper active substrate manufacturing method of this embodiment includes the following steps.
  • the gate electrode and the first common electrode are formed in step S1 for forming the gate electrode 2 and the first common electrode 3 on the substrate by, for example, a photolithography process.
  • 2 is a schematic cross-sectional view showing the formation of the gate electrode 2 and the first common electrode 3 in the active substrate. It can be seen from the figure that the first common three electrode occupies almost the pixel list. Most areas of the yuan. For example, the ratio of the area of the first common electrode 3 to the area of the pixel electrode in the corresponding pixel unit is, for example, not less than 30%.
  • the gate electrode 2 and the first common electrode 3 may be formed of the same conductive material such as a metal material or a conductive oxide material, or may be formed of different conductive materials.
  • gate lines can also be formed at the same time, and the gate electrodes 2 are electrically connected to the corresponding gate lines.
  • the gate insulating layer forming step S2 is for forming a gate insulating layer 4 on the gate 2, the first common electrode 3, and the surface of the substrate (for example, a material for the gate insulating layer is made of silicon dioxide).
  • Fig. 3 is a schematic cross-sectional view showing the formation of the gate insulating layer 4 in the active substrate, and it can be seen from the figure that the gate insulating layer covers almost the entire area above the pixel unit.
  • the active layer processing step S3 is for performing processing such as deposition, activation, etch patterning on the active layer (not shown).
  • processing such as deposition, activation, etch patterning on the active layer (not shown).
  • the structure and processing of the active layer (or active area) can be performed using the prior art and will not be described herein.
  • the source and drain forming step S4 is for forming the source and drain electrodes 5 on the gate insulating layer.
  • the source drain 5 is at least partially disposed on the gate insulating layer 4 on the first common electrode 3, and the source drain 5 does not completely cover the gate insulating layer 4 on the first common electrode 3, but leaves a
  • the small block area is prepared for forming a via hole (for example, the second via hole 11 shown in Fig. 6) in the subsequent step, and the area left in Fig. 5 is the right side portion in the drawing.
  • the source drain 5 is also used as a self-aligned mask and a channel (not shown) of the active layer is formed by, for example, an etching process.
  • Fig. 4 shows a schematic cross-sectional view after the source and drain electrodes 5 are formed in the active substrate.
  • a plurality of data lines can be simultaneously formed, one of the source and drain 5 of the same thin film transistor is electrically connected to the corresponding data line, and the other source drain 5 is connected to the corresponding pixel electrode formed later.
  • the passivation layer is formed in step S5 for depositing the passivation layer 6 on the resulting structure with, for example, plasma enhanced chemical vapor deposition (PECVD) with SiO 2 or SiNx or other suitable material.
  • PECVD plasma enhanced chemical vapor deposition
  • a passivation layer 6 is formed on the source and drain electrodes 5 and the gate insulating layer 4 on the first common electrode 3, and on the gate insulating layer 4 over the gate electrode 2 and its vicinity, and FIG. 5 shows A schematic cross-sectional view of the passivation layer 6 in the active substrate after formation.
  • the second via forming step S6 is for forming a second via 11 by, for example, a photolithography process, while simultaneously penetrating the passivation layer 6 and the gate insulating layer 4. Thus, a portion of the first common electrode 3 can be exposed through the second via 11, and FIG. 6 shows a schematic cross-sectional view after the formation of the second via 11 in the active substrate.
  • the second common electrode forming step S7 is for forming a second common electrode 9, which is connected to the first common electrode 3 through the second via hole 11 formed in the previous step.
  • Fig. 7 is a schematic cross-sectional view showing the formation of the second common electrode 9 in the active substrate. In the horizontal direction as shown in FIG.
  • the second common electrode 9 and the source and drain electrodes 5 have a large overlapping coverage, and the ratio of the area of the second common electrode 9 to the area of the pixel electrode in the corresponding pixel unit formed later is proportional to If not less than 30%, to form a large storage capacitor. Also, the second common electrode 9 does not cover the first via hole connected between the resin passivation layer 7 and the source and drain electrodes 5 formed in the subsequent step (as shown in FIGS. 9 and 10).
  • the second common electrode 9 is, for example, a metal such as Mo, Al, Cu, Al, Nd, or the like, and an alloy thereof, and may be a material such as indium tin oxide.
  • the resin passivation layer forming step S8 is for forming a resin passivation layer 7 on the surface of the structure obtained in the step S7.
  • the basic requirements for material selection of the resin passivation layer 7 are: low dielectric constant, that is, £ ⁇ 5, Such as JSR's PC403, PC405G, PC411B, PC415G, PC542, DA-2009 of Dongjin Company.
  • Fig. 8 is a schematic cross-sectional view showing the formation of the resin passivation layer 7 in the active substrate.
  • the first via forming step S9 is for forming a first via 10 to pass through the resin passivation layer 7 and the passivation layer 6 so that a portion of the source drain 5 is exposed so that the source drain 5 is exposed. A portion is in contact connection with a pixel electrode in the subsequently formed pixel electrode layer 8.
  • FIG. 9 is a schematic cross-sectional view showing the formation of the first via hole 10 in the active substrate.
  • an etching process (such as wet etching or dry etching) may be selected according to the specific resin passivation layer 7, which can be performed by using a known technique, and is no longer used here. Narration.
  • Fig. 10 is a schematic cross-sectional view showing the formation of a pixel electrode layer in an active substrate.
  • FIGS. 10 and 11 are schematic plan views showing an example of an active substrate of the electronic paper active substrate shown in FIG. 10, and FIG. 11 is a schematic diagram of an active substrate including six pixel unit structures, but the present embodiment The pixel unit in the example is not limited thereto.
  • FIG. 10 is a schematic cross-sectional view of an electronic paper active substrate taken along line AA shown in FIG. 10 and 11 clearly show the position of the second via hole 11 in the electronic paper active substrate.
  • the difference between this embodiment and the first embodiment is that the electronic paper active substrate manufacturing method of the first embodiment needs to etch both the resin passivation layer 7 and the passivation layer 6 in the first via forming step S9.
  • a first forming step of forming the first via hole 10 in the passivation layer 6 (for example, by etching) is convenient to obtain a structure in which the second via hole 11 and the lower portion of the first via hole 10 are formed.
  • the second via forming step and the first via first forming step can be performed in the same etching step, that is, the formation of both is completed in one time using a mask, as shown in Fig. 13, thereby saving the formation process.
  • the resin passivation layer forming step S8 fills the lower portion of the first via hole. Subsequently, in the first via forming step S9, only the material of the resin passivation layer is etched once to form the structure shown in Fig. 9.
  • the electronic paper active substrate of the embodiment of the present invention has a second common electrode structure, and therefore, the single common electrode is expanded into two common electrodes, thereby increasing the area of the capacitor plate by nearly double, and the storage capacitance of the pixel It is nearly doubled without affecting the performance of the formed thin film transistor (TFT) device.
  • TFT thin film transistor
  • an embodiment of the present invention provides an electronic paper display screen comprising the electronic paper active substrate and the electrophoretic substrate according to the first embodiment or the second embodiment.
  • a common electrode is provided on the electrophoretic substrate, and an electrophoretic particle layer is also coated.
  • the active substrate is responsible for inputting the data signal to control the image in real time, including a plurality of pixel units arranged in a matrix form.
  • Electronic paper active due to an embodiment of the present invention
  • the substrate has a large storage capacitor, so the ability of the electronic paper display to withstand high voltage and large leakage current can be effectively improved.

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Abstract

一种电子纸有源基板及其制造方法和电子纸显示屏。该电子纸有源基板包括：基板（1）、栅极（2）、第一公共电极（3）、第二公共电极（9）、栅极绝缘层（4）、有源层、源漏极（5）、钝化层（6）、树脂钝化层（7）、以及像素电极层（8）。栅极（2）和第一公共电极（3）布置在基板（1）上，并且栅极（2）上依次布置有栅极绝缘层（4）、有源层、源漏极（5）、钝化层（6）、树脂钝化层（7）以及像素电极层（8）。第一公共电极（3）上依次布置有栅极绝缘层（4）、源漏极（5）、钝化层（6）、第二公共电极（9）、树脂钝化层（7）、以及像素电极层（8），并且第一公共电极（3）和第二公共电极（9）电连接。

Description

电子纸有源基板及其制造方法和电子纸显示屏 技术领域
本发明的实施例涉及一种电子纸有源基板及其制造方法和电子纸显屏。 背景技术
电子纸是一种新型的可重复利用的电子显示设备，外形呈薄而柔软的纸 状物。 电泳型电子纸就是其中的一种， 其利用内含黑色颗粒和白色颗粒的带 电粒子在施加的电场中上下移动来实现图像显示的。 电子纸要实现文本信息 的显示， 就需要使用有源矩阵驱动技术。 例如， 薄膜晶体管 （Thin Film Transistor, TFT )技术就是实现有源矩阵驱动的一种。
电泳型电子纸一般由有源基板和电泳基板对盒而成。 电泳基板上设有公 共电极， 还涂覆有电泳粒子层； 有源基板负责输入数据信号对显示的图像进 行实时控制， 由矩阵形式排列的多个像素单元组成。
电泳型电子纸的优点在于对比度、明亮度视觉等方面性能较好，耗电低， 重量轻而容易使其薄型化， 可以制备多多种形状等； 其缺点在于电泳型电子 纸显示屏需要较高的电压， 电压高， 漏电流较大。 因此， 为了保持电荷稳定 性， 一般都需要设计一个较大的存储电容。
可商业获取的有源电子纸显示屏为了实现大存储电容，需要使得存储电 容几乎占据了整个像素单元。 这是由于电子纸膜较厚， 使得像素电极层与电 泳基板的公共电极层形成的电容较小， 从而必须依靠源漏极与有源基板上的 公共电极层形成电容。 即， 源漏极与有源基板上的公共电极层形成的电容为 每个像素的主要电容， 而像素电极层与电泳基板的公共电极层形成的电容则 可以忽略。
现有的电子纸通常在钝化层外有一层树脂钝化层， 以减少寄生电容， 使 得像素电极层可以平铺更大的面积。 现有的电子纸像素（亚像素）结构中有 源基板的截面结构图如图 1所示。 从图 1可以看出， 为了实现较大的存储电 容,用于开关元件的薄膜晶体管的源漏极 5在像素区内进行了大面积的铺展， 根据电容公式 C=sS/d (其中， ε为电容器的极板间介质的介电常数， S为平 行极板正对的面积， d为平行极板间的距离）可知， ε越大， 电容越大； 面积 越大， 电容越大； 距离越近， 电容越大。 在有源基板中， 源漏极 5与公共电 极 3相当于电容器的两极板， 栅极绝缘层 4为绝缘层。 在电容公式中， 由于 ε与电容两极板间所填充的绝缘材料有关， 当绝缘材料选定后， ε基本是一个 定值。 因此， 为了实现有源基板每个像素的大电容， 一个方法是增大源漏极 与公共电极正对的面积， 但像素面积本身有限， 因此该方法的效果有限； 另 一个办法就是减小栅极绝缘层的厚度， 但栅极绝缘层太薄， 可能带来栅极边 缘与源漏极的短路或击穿， 并会影响 TFT (薄膜场效应晶体管） 的性能。
因此，在不影响 TFT器件性能的同时又有效提高存储电容是目前亟待解 决的问题。 发明内容
本发明的实施例所要解决的技术问题之一是针对现有技术中存在上述 缺陷，提供一种在不影响 TFT器件性能的同时又能有效提高存储电容的电子 纸有源基板和釆用该电子纸有源基板的电子纸显示屏， 以及该电子纸有源基 板的制造方法。
本发明的一个实施例提供了一种电子纸有源基板， 其包括： 基底基板、 栅极、 第一公共电极、 第二公共电极、 栅极绝缘层、 有源层、 源漏极、 钝化 层、 树脂钝化层、 以及像素电极层； 所述栅极和所述第一公共电极布置在所 述基底基板上， 并且所述栅极上依次布置有所述栅极绝缘层、 有源层、 源漏 极、 钝化层、 树脂钝化层以及像素电极层； 所述第一公共电极上依次布置有 栅极绝缘层、 源漏极、 钝化层、 第二公共电极、 树脂钝化层、 以及像素电极 层， 并且所述第一公共电极和所述第二公共电极电连接。
在一个示例中， 在上述电子纸有源基板中， 所述第一公共电极和所述第 二公共电极平行布置,通过穿过所述栅极绝缘层以及所述钝化层的第二过孔 相互电连接。
在一个示例中， 在上述电子纸有源基板中， 所述第二公共电极的材料为 金属或氧化铟锡， 或者为金属或氧化铟锡的组合。
在一个示例中， 所述第二公共电极含有金属。
在一个示例中， 在上述电子纸有源基板中， 所述第一公共电极的面积与 像素电极层的相应像素单元中的像素电极的面积之比不小于 30%。
在一个示例中，所述第二公共电极的面积与像素电极层的相应像素单元 中的像素电极的面积之比不小于 30%。
在一个示例中， 在上述电子纸有源基板中， 在没有第一公共电极和第二 公共电极的源漏极之上的所述树脂钝化层和钝化层中形成有第一过孔， 以使 得像素电极层通过所述第一过孔与所述源漏极相连。
在根据本发明实施例所述的电子纸有源基板中，通过在钝化层与树脂钝 化层之间增加一层第二公共电极， 并且使第二公共电极可通过第二过孔与第 一公共电极相连， 这样便使得原本由源漏极与单个公共电极形成的电容， 变 成了由源漏极与第一和第二公共电极形成的电容,使得存储电容大大增加（近 乎可增大一倍）， 使得电子纸的存储电容极限得到极大扩充。
本发明的另一个实施例提供了一种电子纸有源基板制造方法， 其包括： 栅极及第一公共电极形成步骤 ,用于在基底基板上形成栅极和第一公共电极； 栅极绝缘层形成步骤， 用于在栅极、 第一公共电极以及基底基板表面形成栅 极绝缘层； 有源层形成步骤， 在栅极绝缘层上形成有源层； 源漏极形成步骤， 用于在有源层上形成源漏极， 其中， 源漏极至少部分地布置在第一公共电极 上的栅极绝缘层上，并且源漏极未完全覆盖第一公共电极；钝化层形成步骤， 用于在源漏极形成步骤所得到的结构上形成钝化层； 第二过孔形成步骤， 用 于形成第二过孔， 使之穿透所述钝化层和所述栅极绝缘层， 从而通过第二过 孔暴露第一公共电极的一部分； 第二公共电极形成步骤， 用于形成第二公共 电极， 所述第二公共电极在钝化层上形成并通过所述第二过孔与所述第一公 共电极相连。
在一个示例中， 所述电子纸有源基板制造方法还包括： 树脂钝化层形成 步骤， 用于在第二公共电极形成步骤所得到的结构表面上形成树脂钝化层； 第一过孔形成步骤， 在没有第一公共电极和第二公共电极的源漏极之上形成 一个第一过孔以使之穿过树脂钝化层和钝化层，以使得源漏极的一部分暴露； 以及像素电极层形成步骤， 用于在第一过孔形成步骤后所得到的结构表面形 成像素电极层， 所述像素电极层通过所述第一过孔与所述源漏极的暴露部分 连接。
在一个示例中， 所述电子纸有源基板制造方法还包括： 第一过孔第一形 成步骤，用于在钝化层形成步骤之后，在所述钝化层中形成第一过孔下部分。 在一个示例中， 在所述电子纸有源基板制造方法中， 树脂钝化层形成步 骤使得所述树脂钝化层填充所述第一过孔下部分； 并且所述第一过孔形成步 骤还包括第一过孔第二形成步骤， 用于在树脂钝化层中形成所述第一过孔， 所述第一过孔包含了所述第一过孔下部分， 从而所述第一过孔使得源漏极的 一部分暴露； 并且， 所述像素电极层形成步骤， 用于在第一过孔第一形成步 骤所得到的结构表面形成像素电极层， 所述像素电极层通过所述第一过孔与 所述源漏极的暴露部分连接。
利用本发明的电子纸有源基板制造方法，通过在钝化层与树脂钝化层之 间增加一层第二公共电极， 并且使第二公共电极可通过第二过孔与第一公共 电极相连， 这样便使得原本由源漏极与单个公共电极形成的电容， 变成了由 源漏极与第一和第二公共电极形成的电容， 使得存储电容大大增加（近乎可 增大一倍 ), 使得电子纸的存储电容极限得到极大扩充。
本发明的另一个实施例提供了一种电子纸显示屏，其包括上述的电子纸 有源基板。
由于釆用了本发明的实施例的电子纸有源基板， 因此， 电子纸显示屏同 样能够实现电子纸有源基板所能实现的有益技术效果。 即， 通过在钝化层与 树脂钝化层之间增加一层第二公共电极， 并且使第二公共电极通过第二过孔 与第一公共电极电连接， 这样便使得原本由源漏极与单个公共电极形成的电 容， 变成了由源漏极与第一和第二公共电极形成的电容， 使电容板的面积增 大了将近一倍， 使得存储电容大大增加（近乎可增大一倍）， 使得电子纸的存 储电容极限得到极大扩充， 同时又不影响 TFT器件性能。 附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术的电子纸有源基板的截面结构图。
图 2为本发明第一实施例的电子纸有源基板中栅极及第一公共电极形成 之后的截面示意图。 图 3为本发明第一实施例的电子纸有源基板中栅极绝缘层形成之后的截 面示意图。
图 4为本发明第一实施例的电子纸有源基板中源漏极形成之后的截面示 意图。
图 5为本发明第一实施例的电子纸有源基板中钝化层形成之后的截面示 意图。
图 6为本发明第一实施例的电子纸有源基板中第二过孔形成之后的截面 示意图。
图 7为本发明第一实施例的电子纸有源基板中第二公共电极形成之后的 截面示意图。
图 8为本发明第一实施例的电子纸有源基板中树脂钝化层形成之后的截 面示意图。
图 9为本发明第一实施例的电子纸有源基板中第一过孔形成之后的截面 示意图。
图 10为本发明第一实施例的电子纸有源基板中像素电极层形成之后的 截面示意图。
图 11为图 10中一种可能的电子纸有源基板的平面图。
图 12为本发明第一实施例的电子纸有源基板制造方法的流程图。
图 13为本发明第二实施例的电子纸有源基板中第二过孔以及第一过孔 下部分同时形成之后截面示意图。
1-基底基板； 2-栅极； 3-第一公共电极； 4-栅极绝缘层； 5-源漏极； 6- 钝化层； 7-树脂钝化层； 8-像素电极层； 9-第二公共电极； 10-第一过孔； 11- 第二过孔。 具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。 请注意， 在附图中表示的结构并非按比例绘制。 并且， 附图中， 相同或 者类似的元件标有相同或者类似的标号。
本发明的实施例的电子纸有源基板包括： 基底基板、 栅极、 第一公共电 极、 栅极绝缘层、 有源层、 源漏极、 钝化层、 第二公共电极、 树脂钝化层、 以及像素电极层。
如图 11所示，该有源基板包括多条栅线 12和多条数据线 13 ,这些栅线 12和数据线 13彼此交叉以定义呈阵列排列的多个像素单元。 例如， 每个像 素单元包括作为开关元件的薄膜晶体管， 薄膜晶体管的栅极与对应的栅线连 接或一体形成， 源漏极之一与对应的数据线连接或一体形成， 另一源漏极与 像素电极连接。 下面的描述针对单个像素单元进行， 但其他像素单元同样适 用。
例如， 栅极和第一公共电极直接布置在基底基板上。 栅极绝缘层覆盖栅 极和第一公共电极， 并且覆盖未被栅极和第一公共电极所覆盖的部分基底基 板表面。
例如， 源漏极的一部分布置在第一公共电极上的一部分栅极绝缘层上 (即在第一公共电极上面的栅极绝缘层并没有被源漏极全部覆盖），并且源漏 极的另一部分还可以布置在基底基板上的一部分栅极绝缘层上。 栅极绝缘层 与源漏极中间设置有有源层（图中未示出）。
例如， 钝化层的一部分布置在第一公共电极上的一部分栅极绝缘层上， 并且钝化层的一部分覆盖源漏极、 栅极之上的栅极绝缘层上及附近区域。
例如， 在钝化层上布置有第二公共电极。
例如， 第一公共电极和第二公共电极通过第二过孔相互连接， 该第二过 孔穿过栅极绝缘层以及钝化层。
例如， 树脂钝化层覆盖了第二公共电极， 并且树脂钝化层还覆盖了部分 栅极绝缘层。
例如， 在最上层， 像素电极层覆盖了树脂钝化层。
可以看出， 栅极上依次布置有栅极绝缘层、 有源层、 源漏极、 钝化层、 树脂钝化层以及像素电极层； 而第一公共电极上依次布置有栅极绝缘层、 源 漏极、 钝化层、 第二公共电极、 树脂钝化层、 以及像素电极层。
例如， 该电子纸有源基板的表面形成有第一过孔。 栅极、 栅极绝缘层、 有源层、 源漏极构成一个薄膜场效应晶体管（Thin Film Transistor, TFT )。 像素电极层包括每个像素单元的像素电极， 用于相应 像素的显示。 树脂钝化层可用来减少寄生电容以扩大开口率。 薄膜场效应晶 体管作为开关元件， 用于控制是否对像素电极是否加电。
第一公共电极和第二公共电极是公共电极，用于在有源基板上形成相应 像素单元中的存储电容。 可以看出， 由于在钝化层和树脂钝化层中间加设了 一层导电层（第二公共电极）， 并且使得该导电层通过一个过孔（第二过孔） 与第一公共电极电导通， 由此电容器的一个电容板的面积由单个公共电极扩 展为两个公共电极， 从而该电容板的面积增大了将近一倍， 使得第一公共电 极和第二公共电极一起与源漏极形成了一个更大的电容， 由此可大大增加像 素的存储电容。
例如， 第一公共电极和第二公共电极平行布置， 以使得存储电容增大的 效果更好。
例如， 第一公共电极和第二公共电极的材料可以选用同样的材料， 也可 以选用不同的材料。
例如， 第二公共电极可以为金属， 如 Mo, MO/Al/Mo, Mo/Al/Nd/Mo 等， 也可以为氧化铟锡（ITO ), 也可以为金属或氧化铟锡的组合。 进一步， 为了减少电阻， 第二公共电极例如为金属。
例如，第一公共电极的面积与相应像素单元中的像素电极的面积之比不 小于 30%。 例如， 第二公共电极的面积与相应像素单元中的像素电极的面积 之比不小于 30%。 由此， 可以确保较好的存储电容增大的技术效果。
第一实施例
接下来将参考图 2至图 10描述第一实施例的电子纸有源基板制造方法 的具体实施方式。 在图中仅示出了一个像素单元， 其他像素单元可在相同的 步骤中形成。
图 12为本发明第一实施例的电子纸有源基板制造方法的流程图。 如图 12所示， 本实施例的电子纸有源基板制造方法包括如下步骤。
栅极及第一公共电极形成步骤 S1 , 用于通过例如光刻工艺在基板上形 成栅极 2和第一公共电极 3。图 2示出了有源基板中栅极 2及第一公共电极 3 形成之后的截面示意图， 从图中可以看到第一公共 3电极几乎占据了像素单 元的大部分区域。 例如， 第一公共电极 3的面积与相应像素单元中的像素电 极的面积之比例如不小于 30%。 栅极 2及第一公共电极 3可以通过同一导电 材料例如金属材料或导电氧化物材料形成， 或者可以通过不同的导电材料形 成。 在该步骤之中还可以同时形成栅线， 栅极 2与相应的栅线电连接。
栅极绝缘层形成步骤 S2, 用于在栅极 2、 第一公共电极 3以及基板表面 形成栅极绝缘层 4 (例如， 栅极绝缘层的材料釆用二氧化硅）。 图 3示出了有 源基板中栅极绝缘层 4形成之后的截面示意图， 从图中可以看到栅极绝缘层 几乎覆盖了像素单元上方的整个区域。
有源层处理步骤 S3 , 用于对有源层（图中未示出）进行诸如沉积、 活 化、 刻蚀图案化之类的处理。 有源层（或称为有源区） 的结构和处理可以釆 用现有技术来进行， 在此不再赘述。
源漏极形成步骤 S4, 用于在栅极绝缘层上形成源漏极 5。 源漏极 5至少 部分地布置在第一公共电极 3上的栅极绝缘层 4上， 并且源漏极 5并未完全 覆盖第一公共电极 3上的栅极绝缘层 4, 而是留出一小块区域为后续步骤中 形成过孔（例如， 图 6所示的第二过孔 11 )做准备， 在图 5中所留出的区域 为图中的右侧部分。 在该步骤 S4中， 还以源漏极 5作为自对准掩膜并利用 例如刻蚀工艺来形成有源层的沟道（图中未示出）。这些工艺步骤可以釆用现 有技术的工艺来进行， 图 4示出了有源基板中源漏极 5形成之后的截面示意 图。 在该步骤之中， 可以同时形成多条数据线， 同一薄膜晶体管的源漏极 5 之一与相应的数据线电连接， 而另一源漏极 5将与之后形成的相应的像素电 极连接。
钝化层形成步骤 S5 , 用于利用例如等离子体增强化学气相沉积 ( PECVD )以 Si02或 SiNx或其它合适的材料在所得到的结构上沉积钝化层 6。 例如， 在源漏极 5以及第一公共电极 3上的栅极绝缘层 4上、 以及栅极 2 之上的栅极绝缘层 4上及其附近区域形成了钝化层 6, 图 5示出了有源基板 中钝化层 6形成之后的截面示意图。
第二过孔形成步骤 S6, 用于通过例如光刻工艺形成一个第二过孔 11 , 使之同时穿透钝化层 6和栅极绝缘层 4。 这样， 通过第二过孔 11可暴露第一 公共电极 3的一部分，图 6示出了有源基板中第二过孔 11形成之后的截面示 意图。 第二公共电极形成步骤 S7, 用于形成第二公共电极 9, 该第二公共电极 9通过上一步骤中形成的第二过孔 11与第一公共电极 3相连。 图 7示出了有 源基板中第二公共电极 9形成之后的截面示意图。 在如图 7所示的水平方向 上， 第二公共电极 9与源漏极 5有很大的重叠覆盖， 第二公共电极 9的面积 与之后形成的相应像素单元中的像素电极的面积之比例如不小于 30%, 以形 成一个大的存储电容。 并且， 该第二公共电极 9不覆盖后续步骤中形成的树 脂钝化层 7与源漏极 5之间相连的第一过孔（如图 9和图 10所示）。 第二公 共电极 9例如为金属， 如 Mo、 Al、 Cu、 Al、 Nd等， 以及其合金， 也可以是 氧化铟锡等材料。
树脂钝化层形成步骤 S8, 用于在步骤 S7所得到的结构表面上形成树脂 钝化层 7, 该树脂钝化层 7的材料选择的基本要求为： 低介电常数， 即£<5, 如 JSR公司的 PC403、 PC405G、 PC411B、 PC415G、 PC542, 东进公司的 DA-2009等。 图 8示出了有源基板中树脂钝化层 7形成之后的截面示意图。
第一过孔形成步骤 S9, 用于形成一个第一过孔 10以使之穿过树脂钝化 层 7和钝化层 6, 以使得源漏极 5的一部分暴露， 以便源漏极 5的暴露部分 与后续形成的像素电极层 8中的像素电极接触连接。 在该步骤 S9中， 由于 不仅需要刻蚀树脂钝化层 7, 而且需要刻蚀钝化层 6 (例如 Si02或 SiNx ), 所以可以釆用干刻工艺一次性刻蚀上述两种材料， 或者在另一个示例中， 也 可分为两步， 先通过湿法刻蚀在树脂钝化层 7中形成第一过孔 10的上部分， 再通过干法刻蚀在 Si02或 SiNx 的钝化层中形成相应的第一过孔 10的下部 分。 图 9示出了有源基板中第一过孔 10形成之后的截面示意图。 由于不同的 树脂钝化层 7的图案化方法不一样， 可以根据具体的树脂钝化层 7选择刻蚀 工艺 （如湿刻或干刻）， 这可以釆用公知技术来执行， 在此不再赘述。
像素电极层形成步骤 S10, 用于在电子纸有源基板的表面形成像素电极 层 8, 该像素电极层 8包括每个像素单元的像素电极， 该像素电极通过第一 过孔 10与源漏极 5的暴露部分连接。 图 10示出了有源基板中像素电极层形 成之后的截面示意图。
通过本实施例上述电子纸有源基板制造方法，得到如图 10和图 11所示 的电子纸有源基板结构。 图 11为图 10所示电子纸有源基板的一种可能的平 面图示例， 图 11中包含有 6个像素单元结构的有源基板示意图，但是本实施 例中的像素单元不限于此.图 10是沿着图 11所示的线 A-A截取的一个电子纸 有源基板的截面示意图。 图 10和图 11均清楚地示出了电子纸有源基板中第 二过孔 11的位置。
这里应该理解的是， 上面结合图 2-12对本实施例的电子纸有源基板及 其制造方法按各个步骤进行了说明， 但是本发明并不排除除了上述步骤之外 其它步骤的存在。 因此， 在不脱离本发明的范围的情况下， 可以在所描述的 步骤中加入其它步骤以形成其它结构或者实现其它目的。
第二实施例
本实施例与第一实施例的区别在于，第一实施例所述电子纸有源基板制 造方法在第一过孔形成步骤 S9需要对树脂钝化层 7和钝化层 6都进行刻蚀 以形成第一过孔 10; 而在本实施例中， 简化了第一过孔 10形成步骤 S9的工 艺， 即通过在钝化层 6形成步骤 S5或第二过孔 11形成步骤 S6之后增加一 个在钝化层 6中形成第一过孔 10的第一形成步骤（例如通过刻蚀）， 以方便 得到形成有第二过孔 11以及第一过孔 10的下部分的结构。
第二过孔形成步骤以及第一过孔第一形成步骤可在同一个刻蚀步骤中 完成， 即利用一个掩膜一次性完成两者的形成， 如图 13所示， 因此节省了形 成工艺。
然后， 树脂钝化层形成步骤 S8将填充该第一过孔下部分。 随后， 在第 一过孔形成步骤 S9中只需对树脂钝化层的材料进行一次性刻蚀即可形成图 9 所示的结构。
本实施例中电子纸有源基板制造方法中的其它步骤与第一实施例中相 同， 在此不再赘述。
本发明的实施例所述电子纸有源基板中具有第二公共电极结构,因此，由 单个公共电极扩展为两个公共电极， 从而使电容板的面积增大了将近一倍， 像素的存储电容增大了近一倍， 同时又不影响所形成的薄膜晶体管 （TFT ) 器件性能。
此外， 本发明的实施例还提供了一种电子纸显示屏， 其包括第一实施例 或第二实施例所述的电子纸有源基板和电泳基板。 例如， 电泳基板上设有公 共电极， 还涂覆有电泳粒子层。 有源基板负责输入数据信号对图像实时进行 控制， 包括矩阵形式排列的多个像素单元。 由于本发明实施例的电子纸有源 基板具有较大的存储电容， 因此能有效地提高电子纸显示屏耐受电压高、 漏 电流大的能力。
凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施 例所做的任何简单修改、 等同变化及修饰， 均仍属于本发明技术方案保护的 范围内。

Claims

权利要求书
1. 一种电子纸有源基板， 包括基底基板、 栅极、 第一公共电极、 第二公 共电极、 栅极绝缘层、 有源层、 源漏极、 钝化层、 树脂钝化层、 以及像素电 极层； 其中，
所述栅极和所述第一公共电极布置在所述基底基板上，
所述栅极上依次布置有所述栅极绝缘层、 有源层、 源漏极、 钝化层、 树 脂钝化层以及像素电极层；
所述第一公共电极上依次布置有栅极绝缘层、 源漏极、 钝化层、 第二公 共电极、 树脂钝化层、 以及像素电极层， 并且
所述第一公共电极和所述第二公共电极电连接。
2. 根据权利要求 1所述的电子纸有源基板，其中，所述第一公共电极和 所述第二公共电极平行布置,通过穿过所述栅极绝缘层以及所述钝化层的第 二过孔相互电连接。
3. 根据权利要求 1或 2所述的电子纸有源基板，其中，所述第二公共电 极的材料为金属或氧化铟锡，或者为金属或氧化铟锡的组合。
4. 根据权利要求 1-3任一所述的电子纸有源基板， 其中， 所述第一公共 电极的面积与像素电极层的相应像素单元中的像素电极的面积之比不小于 30%。
5. 根据权利要求 1-4任一所述的电子纸有源基板， 其中， 所述第二公共 电极的面积与像素电极层的相应像素单元中的像素电极的面积之比不小于 30%。
6. 根据权利要求 1-5任一所述的电子纸有源基板， 其中， 在没有第一公 共电极和第二公共电极的源漏极之上所述树脂钝化层和钝化层中形成有第一 过孔， 以使得像素电极层通过所述第一过孔与所述源漏极电连接。
7. 一种电子纸有源基板制造方法， 包括：
栅极及第一公共电极形成步骤，用于在基底基板上形成栅极和第一公共 电极；
栅极绝缘层形成步骤， 用于在栅极、 第一公共电极以及基底基板表面形 成栅极绝缘层； 有源层形成步骤， 在栅极绝缘层上形成有源层；
源漏极形成步骤， 用于在有源层上形成源漏极， 其中， 源漏极至少部分 地布置在第一公共电极上的栅极绝缘层上， 并且源漏极未完全覆盖第一公共 电极上的栅极绝缘层；
钝化层形成步骤， 用于在源漏极形成步骤所得到的结构上形成钝化层； 第二过孔形成步骤， 用于形成第二过孔， 使之穿透所述钝化层和所述栅 极绝缘层， 从而通过第二过孔暴露第一公共电极的一部分；
第二公共电极形成步骤， 用于形成第二公共电极， 所述第二公共电极在 钝化层上形成并通过所述第二过孔与所述第一公共电极相连。
8. 根据权利要求 7所述的电子纸有源基板制造方法， 还包括： 树脂钝化层形成步骤，用于在第二公共电极形成步骤所得到的结构表面 上形成树脂钝化层；
第一过孔形成步骤，在没有第一公共电极和第二公共电极的源漏极之上 形成第一过孔以使之穿过树脂钝化层和钝化层，以使得源漏极的一部分暴露； 以及
像素电极层形成步骤，用于在第一过孔形成步骤后所得到的结构表面形 成像素电极层， 所述像素电极层通过所述第一过孔与所述源漏极的暴露部分 连接。
9. 根据权利要求 8所述的电子纸有源基板制造方法，其中所述第一过孔 形成步骤包括：
第一过孔第一形成步骤， 用于在钝化层形成步骤之后， 在所述钝化层中 形成第一过孔下部分。
10. 根据权利要求 9所述的电子纸有源基板制造方法， 其中， 树脂钝化 层形成步骤使得所述树脂钝化层填充所述第一过孔下部分；
所述第一过孔形成步骤还包括第一过孔第二形成步骤，用于在树脂钝化 层中形成所述第一过孔， 所述第一过孔包含了所述第一过孔下部分， 从而所 述第一过孔使得源漏极的一部分暴露；
所述像素电极层形成步骤，用于在第一过孔第二形成步骤所得到的结构 表面形成像素电极层 , 所述像素电极层通过所述第一过孔与所述源漏极的暴 露部分连接。
11. 一种电子纸显示屏， 包括根据权利要求 1至 6之一所述的电子纸有 源基板。
PCT/CN2012/082361 2011-11-23 2012-09-28 电子纸有源基板及其制造方法和电子纸显示屏 WO2013075551A1 (zh)

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