WO2021056730A1 - 显示面板及其制备方法以及显示装置 - Google Patents

显示面板及其制备方法以及显示装置 Download PDF

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Publication number
WO2021056730A1
WO2021056730A1 PCT/CN2019/117499 CN2019117499W WO2021056730A1 WO 2021056730 A1 WO2021056730 A1 WO 2021056730A1 CN 2019117499 W CN2019117499 W CN 2019117499W WO 2021056730 A1 WO2021056730 A1 WO 2021056730A1
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WIPO (PCT)
Prior art keywords
layer
hole
source
electrode
drain
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PCT/CN2019/117499
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English (en)
French (fr)
Inventor
李治福
肖军城
艾飞
宋继越
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武汉华星光电技术有限公司
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Publication of WO2021056730A1 publication Critical patent/WO2021056730A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present invention relates to the field of display technology, in particular to the manufacture of display devices, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • LCD Liquid Crystal Display
  • the display thin film transistor device, the sensor thin film transistor device, and the optical sensor in the LCD display screen are arranged on the same layer, so that The optical sensor receives less light, which reduces the accuracy of the optical fingerprint recognition inside the LCD display.
  • the object of the present invention is to provide a display panel, a display device, and a method of manufacturing a display panel, by stacking the second thin film transistor layer and the first thin film transistor layer, and passing through the first through hole, the second through hole, and the third through hole.
  • the through hole, the fourth through hole, the fifth through hole, and the sixth through hole electrically connect the related film layers and solve the problem of LCD caused by the optical sensor receiving less light in the prior art.
  • An embodiment of the present invention provides a display panel, which includes: a substrate, a first thin film transistor layer, a first insulating layer, a second thin film transistor layer, a second insulating layer, a device layer, and a plurality of through holes;
  • the first thin film transistor layer is disposed on the substrate, and the first thin film transistor layer includes a first source and drain layer;
  • the first insulating layer is disposed on the first thin film transistor layer
  • the second thin film transistor layer is disposed on the first insulating layer, and the second thin film transistor layer includes a second gate layer and a second source and drain layer;
  • the second insulating layer is disposed on the second thin film transistor layer
  • the device layer is disposed on the second insulating layer, the device layer includes a pixel electrode, a sensor layer, and a metal part, and the sensor layer includes a first electrode and a second electrode;
  • the plurality of through holes includes a first through hole, a second through hole, a third through hole, a fourth through hole, a fifth through hole, and a sixth through hole.
  • the hole, the third through hole, the fourth through hole, the fifth through hole, and the sixth through hole are all provided with conductive materials;
  • the first through hole is provided on the first insulating layer and the second thin film transistor layer
  • the fifth through hole is provided on the second insulating layer and the device layer
  • the pixel The electrode is electrically connected to the second source/drain layer through the fifth through hole
  • the second source/drain layer is electrically connected to the first source/drain layer through the first through hole, so that The pixel electrode is electrically connected to the first source and drain layer;
  • the second through hole is provided on the second insulating layer, and the first electrode is electrically connected to the second source and drain layer through the second through hole;
  • the third through hole is provided on the second thin film transistor layer, the fourth through hole is provided on the second insulating layer, the sixth through hole is provided on the device layer, and the first The two electrodes are electrically connected to the metal part through the sixth through hole, the metal part is electrically connected to the second source-drain layer through the fourth through hole, and the second source-drain layer
  • the third through hole is electrically connected to the second gate layer, so that the second electrode and the second gate layer are electrically connected.
  • the second gate electrode layer includes a second gate electrode
  • the second source-drain electrode layer includes a second source electrode, a second drain electrode
  • the second source electrode and the second drain electrode The poles are respectively arranged on the left/right and right/left sides of the second grid
  • the source-drain layer further includes a first metal part and a second metal part.
  • the first metal part is provided on a side of the second source electrode away from the second gate electrode, and the second metal part is provided On the side of the second drain away from the second gate;
  • the pixel electrode is electrically connected to the first metal part through the fifth through hole, and the first metal part is electrically connected to the first source and drain layer through the first through hole, so that the The pixel electrode is electrically connected to the first source and drain layer.
  • the first electrode is electrically connected to the second drain through the second through hole.
  • the second gate layer further includes a metal layer, and the metal layer is disposed opposite to the second metal part;
  • the second electrode is electrically connected to the second metal part through the sixth through hole and the fourth through hole in turn, and the second metal part is electrically connected to the metal layer through the third through hole. Electrical connection, so that the second electrode and the metal layer are electrically connected.
  • the second thin film transistor layer further includes a second active layer, the second active layer is disposed above the second gate layer, and the composition material of the second active layer includes One of amorphous silicon or indium gallium zinc oxide.
  • the first thin film transistor layer further includes a first active layer, the first active layer is disposed below the first source and drain layer, and the first active layer is composed of Including polysilicon.
  • An embodiment of the present invention also provides a display device, the display device includes a display panel, the display panel includes: a substrate, a first thin film transistor layer, a first insulating layer, a second thin film transistor layer, a second insulating layer, Device layer and multiple through holes;
  • the first thin film transistor layer is disposed on the substrate, and the first thin film transistor layer includes a first source and drain layer;
  • the first insulating layer is disposed on the first thin film transistor layer
  • the second thin film transistor layer is disposed on the first insulating layer, and the second thin film transistor layer includes a second gate layer and a second source and drain layer;
  • the second insulating layer is disposed on the second thin film transistor layer
  • the device layer is disposed on the second insulating layer, the device layer includes a pixel electrode, a sensor layer, and a metal part, and the sensor layer includes a first electrode and a second electrode;
  • the plurality of through holes includes a first through hole, a second through hole, a third through hole, a fourth through hole, a fifth through hole, and a sixth through hole.
  • the hole, the third through hole, the fourth through hole, the fifth through hole, and the sixth through hole are all provided with conductive materials;
  • the first through hole is provided on the first insulating layer and the second thin film transistor layer
  • the fifth through hole is provided on the second insulating layer and the device layer
  • the pixel The electrode is electrically connected to the second source/drain layer through the fifth through hole
  • the second source/drain layer is electrically connected to the first source/drain layer through the first through hole, so that The pixel electrode is electrically connected to the first source and drain layer;
  • the second through hole is provided on the second insulating layer, and the first electrode is electrically connected to the second source and drain layer through the second through hole;
  • the third through hole is provided on the second thin film transistor layer, the fourth through hole is provided on the second insulating layer, the sixth through hole is provided on the device layer, and the first The two electrodes are electrically connected to the metal part through the sixth through hole, the metal part is electrically connected to the second source-drain layer through the fourth through hole, and the second source-drain layer
  • the third through hole is electrically connected to the second gate layer, so that the second electrode and the second gate layer are electrically connected.
  • the second gate electrode layer includes a second gate electrode
  • the second source-drain electrode layer includes a second source electrode, a second drain electrode
  • the second source electrode and the second drain electrode The poles are respectively arranged on the left/right and right/left sides of the second grid
  • the source-drain layer further includes a first metal part and a second metal part.
  • the first metal part is provided on a side of the second source electrode away from the second gate electrode, and the second metal part is provided On the side of the second drain away from the second gate;
  • the pixel electrode is electrically connected to the first metal part through the fifth through hole, and the first metal part is electrically connected to the first source and drain layer through the first through hole, so that the The pixel electrode is electrically connected to the first source and drain layer.
  • the first electrode is electrically connected to the second drain through the second through hole.
  • the second gate layer further includes a metal layer, and the metal layer is disposed opposite to the second metal part;
  • the second electrode is electrically connected to the second metal part through the sixth through hole and the fourth through hole in turn, and the second metal part is electrically connected to the metal layer through the third through hole. Electrical connection, so that the second electrode and the metal layer are electrically connected.
  • the second thin film transistor layer further includes a second active layer, the second active layer is disposed above the second gate layer, and the composition material of the second active layer includes One of amorphous silicon or indium gallium zinc oxide.
  • the first thin film transistor layer further includes a first active layer, the first active layer is disposed below the first source and drain layer, and the first active layer is composed of Including polysilicon.
  • An embodiment of the present invention also provides a manufacturing method of a display panel, the method including:
  • first thin film transistor layer Forming a first thin film transistor layer on the substrate, the first thin film transistor layer including a first source and drain layer;
  • the second thin film transistor layer including a second gate layer and a second source and drain layer;
  • a first through hole is formed on the first insulating layer and the second thin film transistor layer, and a third through hole is formed on the second thin film transistor layer, and in the first through hole and the second thin film transistor layer, Conductive materials are provided in the three through holes.
  • the first through hole is used to electrically connect the second source and drain layer to the first source and drain layer
  • the third through hole is used to connect the The second source and drain layer is electrically connected to the second gate layer
  • a fifth through hole, a second through hole, and a fourth through hole are formed on the second insulating layer, and the fifth through hole, the second through hole, and the fourth through hole are all formed in the fifth through hole, the second through hole, and the fourth through hole.
  • a device layer is formed on the second insulating layer.
  • the device layer includes a pixel electrode, a sensor layer, and a metal part.
  • the sensor layer includes a first electrode and a second electrode.
  • the pixel electrode is electrically connected to the second source/drain layer, the second through hole is used to electrically connect the first electrode to the second source/drain layer, and the fourth through hole is used To electrically connect the metal part with the second source and drain layer;
  • a sixth through hole is formed on the device layer, and a conductive material is disposed in the sixth through hole, and the sixth through hole electrically connects the second electrode and the metal part.
  • the step of forming a second thin film transistor layer on the first insulating layer, the second thin film transistor layer including a second gate layer and a second source and drain layer includes:
  • the second gate layer including a second gate and a metal layer
  • a second source and drain layer is formed on the second active layer and the second gate insulating layer, and the second source and drain layer includes a second source, a second drain, a first metal part, And a second metal part, the second source and the second drain are respectively arranged on the left/right, right/left sides of the second gate, the first metal part is arranged on the first The two source electrodes are away from the second gate, the second metal part is provided on the second drain away from the second gate, the metal layer and the second metal part Relative settings.
  • the step of forming a device layer on the second insulating layer, the device layer including a pixel electrode and a sensor layer, and the sensor layer including a first electrode and a second electrode includes:
  • the pixel electrode and the second electrode are formed on the insulating layer.
  • the present invention provides a display panel, a display device, and a method for manufacturing a display panel.
  • the display panel includes a substrate, a first thin film transistor layer, a first insulating layer, a second thin film transistor layer, a second insulating layer, a device layer, And a plurality of through holes, the second thin film transistor layer is disposed on the first thin film transistor layer, and the plurality of through holes electrically connect the related film layers.
  • the present invention increases the optical sensor receiving The received light improves the accuracy of the optical fingerprint recognition inside the display panel.
  • FIG. 1 is a schematic cross-sectional view of a display panel provided by an embodiment of the invention.
  • FIG. 2 is a schematic top view of a pixel electrode provided by an embodiment of the present invention.
  • FIG. 3 is a flowchart of a manufacturing method of a display panel provided by an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a first scene of a manufacturing method of a display panel provided by an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a second scenario of a method for manufacturing a display panel provided by an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a third scene of the manufacturing method of the display panel provided by the embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a fourth scenario of a method for manufacturing a display panel provided by an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a fifth scenario of a method for manufacturing a display panel provided by an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a sixth scenario of a method for manufacturing a display panel provided by an embodiment of the present invention.
  • length is a neutral word, which does not indicate a preference for long or short, but only expressed as a preset value. The value is uncertain and will be determined according to the actual situation.
  • the present invention provides a display device, which includes a display panel as shown in FIG. 1.
  • the display panel 00 includes: a substrate 10, a first thin film transistor layer 20, a first insulating layer 30, a second thin film transistor layer 40, a second insulating layer 50, and a device Layer 80 and multiple through holes.
  • the first thin film transistor layer 20 is provided on the substrate 10
  • the first insulating layer 30 is provided on the first thin film transistor layer 20
  • the second thin film transistor layer 40 is provided on the On the first insulating layer 30,
  • the second insulating layer 50 is disposed on the second thin film transistor layer 40, and the sensor layer 60 and the pixel electrode 70 are disposed on the second insulating layer 50.
  • the substrate 10 includes a substrate 101, a light shielding layer 102 provided on the substrate 101, and a buffer layer 103 provided on the substrate 101 and the light shielding layer 102.
  • the substrate 101 may be a glass substrate, and the composition material of the glass substrate may include quartz powder, strontium carbonate, barium carbonate, boric acid, boric anhydride, aluminum oxide, calcium carbonate, barium nitrate, magnesium oxide, tin oxide, oxide At least one of zinc.
  • the light-shielding layer 102 may be a non-light-transmitting film layer, and the constituent material of the non-light-transmitting film layer may include materials with low reflectivity such as black resin or light-shielding metal.
  • the light-shielding metal may be Cu. , Mo. It can be understood that when the display panel 00 includes a backlight source, the light shielding layer 102 can avoid the leakage current problem caused by the light from the backlight source irradiating the first thin film transistor layer 20.
  • the buffer layer 103 includes a first buffer layer 1031 and a second buffer layer 1032 that are sequentially disposed on the substrate 101 and the light shielding layer 102.
  • the constituent material of the first buffer layer 1031 may include silicon nitride, and the constituent material of the second buffer layer 1032 may include silicon oxide.
  • the first thin film transistor layer 20 includes a first active layer 201 provided on the substrate 10, a first active layer 201 provided on the first active layer 201 and the first active layer 201 on the substrate 10.
  • the constituent material of the first active layer 201 includes polysilicon.
  • the first active layer 201 may be made of low-temperature polysilicon technology. It is understandable that the first active layer 201 prepared by low-temperature polysilicon technology can have higher electron mobility, so that when the first thin film transistor layer 20 charges the corresponding pixel electrode 70, it can produce Larger drive current to increase charging speed.
  • both ends of the first active layer 201 may be doped with some dopants to form a first source contact area 2011 and a first drain contact area 2022 respectively.
  • the first source contact area 2011 and the first drain contact area 2022 can also be used as ohmic contact layers to reduce the first active layer 201 and the first source 206/the first drain The contact resistance between 207.
  • the dopant may include phosphorous ions, and the concentration of the phosphorous ions may be controlled to form N+-type doping or N-type doping; for example, it may be in the first source contact region 2011/ N-type doping is formed on the side of the first drain contact region 2022 close to the first active layer 201, and the first source contact region 2011/first drain contact region 2022 is close to the first active layer 201.
  • N+ type doping is formed on one side of the source layer 201.
  • the N- type doping can reduce the impact of hot carriers and improve the stability of the first thin film transistor layer 20.
  • the N+ type doping can form Ohmic contact layer.
  • the constituent material of the first gate insulating layer 202 may include at least one of an inorganic dielectric material and an organic dielectric material.
  • the inorganic dielectric material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride
  • the organic dielectric material may be polyimide resin, epoxy resin or acrylic. Polymer materials such as resins.
  • the constituent material of the first gate layer 203 may include at least one of conductive materials such as metal, metal oxide, metal nitride, and metal oxynitride.
  • the metal may be a metal material such as Cu, Al, Mo, Ti, etc., without limitation.
  • constituent material of the first inner insulating layer 204 reference may be made to the related description of the constituent material of the first gate insulating layer 202.
  • the two source and drain through holes 205 are respectively provided on both sides of the first gate layer 203, and the two source and drain through holes 205 are provided with conductive materials.
  • the relative position between the first source 206 and the first drain 207 is not limited.
  • the first source 206 and the first drain 207 are respectively arranged at The source-drain vias 205 on the left and right sides of the first gate layer 203 are taken as an example.
  • the constituent materials of the first source 206 and the first drain 207 may refer to the first gate Related description of the constituent materials of the electrode layer 203; it is understandable that the conductive material in the two source-drain vias 205 may be the same as the constituent materials of the first source 206 and the first drain 207, Therefore, the conductive material in the two source and drain vias 205 can be made integrally with the first source 206 and the first drain 207, for example, as shown in FIG.
  • the first source The electrode 206 and the first drain electrode 207 may be respectively arranged above the two source and drain via holes 205. Further, the conductive material in the two source and drain via holes 205, the first source electrode 206 and the first drain electrode 207 can be prepared in the same layer at the same time.
  • the first insulating layer 30 is provided on the first source 206, the first drain 207, and the first inner insulating layer 204, wherein the first insulating layer 30
  • the constituent materials of refer to the related description of the constituent materials of the first inner insulating layer 204.
  • the second thin film transistor layer 40 includes a second gate layer disposed on the first insulating layer 30, and a second gate insulating layer 402 disposed on the second gate layer.
  • the second source-drain layer includes a second source 404 and a second drain 405.
  • the second gate layer includes a second gate 4011, the second gate 4011 is disposed opposite to the second active layer 403, and the second source 404, the second Two drains 405 are respectively provided on the left and right sides of the second gate 4011, and the second gate 4011 is used to control the conduction between the second source 404 and the second drain 405.
  • the second gate 4011, the second source 404, and the second drain 405 can constitute a complete thin film transistor, and the material of the second gate 4011 can refer to the first A related description of the constituent materials of the gate layer 203.
  • the constituent material of the second active layer 403 may include one of amorphous silicon or indium gallium zinc oxide. It is understandable that the use of amorphous silicon or indium gallium zinc oxide to prepare the second active layer 403 may have a low leakage current to prevent the leakage of the second thin film transistor layer 40 to the The signal of the sensor layer 60 causes interference.
  • the region of the second active layer 403 close to the second source 404 and the second drain 405 It may not be necessary to dope with other substances; when the constituent material of the second active layer 403 includes the amorphous silicon, the second active layer 403 is close to the second source 404 and the second drain.
  • the region 405 may be doped with some dopants.
  • the second source electrode 404 and the second drain electrode 405 in the second source and drain layer are respectively disposed at both ends of the second active layer 403, wherein the second The relative position between the source electrode 404 and the second drain electrode 405 is not limited.
  • the second source electrode 404 and the second drain electrode 405 are respectively arranged on the left side of the second active layer 403.
  • the composition materials of the second source 404 and the second drain 405 can refer to the relevant description of the first source 206 and the first drain 207; specifically, the second source 404 is provided on the second gate insulating layer 402 and extends from the left side of the second active layer 403 to a predetermined position above the second active layer 403, and the second drain electrode 405 is provided It is on the second gate insulating layer 402 and extends from the right side of the second active layer 403 to a predetermined position above the second active layer 403.
  • the through hole includes a first through hole 406, and the first through hole 406 is disposed opposite to the first source electrode 206, or the first through hole 406 is opposite to the first drain electrode 206. 207 are arranged oppositely.
  • the first through hole 406 and the first source electrode 206 are arranged oppositely as an example; specifically, the first through hole 406 is arranged on the first insulating layer 30 and the On the second thin film transistor layer 40, further, as shown in FIG. 1, the first through hole 406 is arranged in contact with the first source 206, and the first through hole 406 penetrates part of the first The insulating layer 30 and all of the second gate insulating layer 402; the first through hole 406 is provided with a conductive material.
  • the second source-drain layer further includes a first metal portion 408, and the first metal portion 408 is disposed on a side of the second source 404 away from the second gate 4011, Or the first metal part 408 is provided on the side of the second drain electrode 405 away from the second gate 4011.
  • the first metal part 408 is provided on the second source electrode 404 away from One side of the second gate 4011 is taken as an example; specifically, the first metal portion 408 and the second source 404 are arranged in the same row and separated by a predetermined distance; it is understandable that the first The conductive material in the through hole 406 may be the same as the constituent material of the first metal portion 408.
  • the conductive material in the first through hole 406 may be made integrally with the first metal portion 408, for example, as shown in FIG. As shown in 1, the first metal portion 408 may be provided above the first through hole 406. Further, the conductive material in the first through hole 406 and the first metal portion 408 may be in the same layer, Prepared at the same time.
  • the second source-drain layer may be electrically connected to the first source-drain layer through the first through hole 406; specifically, the second source-drain layer in the second source-drain layer A metal portion 408 can be electrically connected to the first source electrode 206 or the first drain electrode 207 in the first source drain layer through the first through hole 406.
  • the second gate electrode layer further includes a metal layer 4012, the metal layer 4012 and the second gate electrode 4011 are provided on the same layer and separated by a predetermined distance, and the metal layer 4012 is provided on the same layer as the second gate electrode 4011.
  • the metal layer 4012 is provided on the side of the second gate 4011 away from the first metal portion 408 as an example, wherein the metal layer 4012
  • the constituent material of can be a metal conductive material.
  • the through hole further includes a third through hole 407, which is disposed opposite to the metal layer 4012; specifically, the third through hole 407 is disposed in the second On the thin film transistor layer 40, further, as shown in FIG. 1, the third through hole 407 is arranged in contact with the metal layer 4012, and the third through hole 407 penetrates part of the second gate insulating layer 402 ;
  • the third through hole 407 is provided with a conductive material.
  • the second source-drain layer further includes a second metal portion 409, and the second metal portion 409 is provided on a side of the second source 404 away from the second gate 4011, Or the second metal part 409 is provided on the side of the second drain 405 away from the second gate 4011.
  • the first metal part 408 is provided at the second drain 405 away from One side of the second gate 4011 is taken as an example; specifically, the first metal portion 408 and the second drain 405 are arranged in the same row and separated by a predetermined distance; it is understandable that the third The conductive material in the through hole 407 may be the same as the constituent material of the second metal portion 409.
  • the conductive material in the third through hole 407 may be made integrally with the second metal portion 409, for example, as shown in FIG. As shown in 1, the second metal portion 409 may be provided above the third through hole 407. Further, the conductive material in the third through hole 407 and the second metal portion 409 may be in the same layer, Prepared at the same time.
  • the second source-drain layer may be electrically connected to the second gate layer through the third through hole 407; specifically, the second source-drain layer in the second source-drain layer
  • the metal portion 409 may be electrically connected to the metal layer 4012 in the second gate layer through the third through hole 407.
  • the second source electrode 404, the second drain electrode 405, the first metal portion 408, and the second metal portion 409 in the second source drain layer may be in the same layer, Prepared at the same time.
  • the second insulating layer 50 includes a first passivation layer 501 provided on the second thin film transistor layer 40, a flat layer 502 provided on the first passivation layer 501, and a An intermediate layer 503 on the flat layer 502.
  • the constituent material of the first passivation layer 501 may include at least one of an organic insulating material and an inorganic insulating material.
  • the organic insulating material may include at least one of polyimide, polyamic acid, polyamide, polyvinyl alcohol, polyvinyl alcohol cinnamate, or other suitable photoresist materials.
  • the inorganic insulating material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.
  • the first passivation layer 501 may be made of silicon nitride.
  • the constituent material of the flat layer 502 For the constituent material of the flat layer 502, reference may be made to the related description of the constituent material of the first passivation layer 501. Further, the flat layer 502 can be made of photoresist material.
  • the intermediate layer 503 For the constituent material of the intermediate layer 503, reference may be made to the related description of the constituent material of the first passivation layer 501. Further, the intermediate layer 503 may be made of silicon nitride.
  • the device layer 80 includes a sensor layer 60, a metal portion 508, a touch electrode 801, and a pixel electrode 70.
  • the sensor layer 60 has photosensitive characteristics and unidirectional conductivity. When there is no light, the sensor layer 60 has a small saturated reverse leakage current, that is, dark current. At this time, the sensor layer 60 is equivalent to cut-off; when exposed to light, the sensor layer 60 has a saturated reverse leakage current It greatly increases to form a photocurrent, and the photocurrent changes with the intensity of the incident light.
  • the through hole further includes a second through hole 505, which is disposed opposite to the second source 404, or the second through hole 505 and the second drain
  • the electrodes 405 are arranged oppositely.
  • the second through hole 505 and the second drain electrode 405 are arranged oppositely as an example; specifically, the second through hole 505 is arranged on the first passivation layer 501, On the flat layer 502 and the intermediate layer 503, further, as shown in FIG. 1, the second through hole 505 is arranged in contact with the second drain electrode 405, and the second through hole 505 penetrates a portion The first passivation layer 501, all the flat layers 502, and all the intermediate layers 503; the second through holes 505 are provided with conductive materials.
  • the sensor layer 60 includes a first electrode 601, the first electrode 601 is disposed on the intermediate layer 503, the first electrode 601 has a predetermined length, wherein the first electrode 601
  • the constituent material of the electrode 601 may include a conductive material.
  • the conductive material may include at least one of a metal, a metal oxide, and a conductive polymer material; in particular, the constituent material of the first electrode 601 may also include
  • the transparent conductive material specifically, the transparent conductive material may include at least one of metal oxides such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or indium germanium zinc oxide; It is understood that the conductive material in the second through hole 505 can be made of the same material as the first electrode 601.
  • the conductive material in the second through hole 505 can be made integrally with the first electrode 601
  • the first electrode 601 may be disposed above the second through hole 505, and further, the conductive material in the second through hole 505 and the first electrode 601 may be Prepared at the same layer at the same time.
  • the first electrode 601 may be electrically connected to the second source and drain layer through the second through hole 505; specifically, the first electrode 601 may be electrically connected to the second through hole 505. It is electrically connected to the second drain 405 in the second source-drain layer.
  • the through hole further includes a fourth through hole 506, and the fourth through hole 506 is disposed opposite to the second metal part 409; specifically, the fourth through hole 506 is disposed in the On the first passivation layer 501, the flat layer 502, and the intermediate layer 503, further, as shown in FIG. 1, the fourth through hole 506 is arranged in contact with the second metal portion 409, and the The fourth through hole 506 penetrates part of the first passivation layer 501, all of the flat layer 502, and all of the intermediate layer 503; the fourth through hole 506 is provided with a conductive material.
  • the metal portion 508 is disposed on the intermediate layer 503, and the metal portion 508 is arranged in the same row as the first electrode 601 and separated by a predetermined distance; it is understandable that,
  • the constituent material of the metal portion 508 may be a metal conductive material; it is understandable that the conductive material in the fourth through hole 506 may be the same as the constituent material of the metal portion 508, therefore, the fourth through hole 506
  • the conductive material can be made integrally with the metal part 508.
  • the metal part 508 can be provided above the fourth through hole 506. Further, the metal part 508 in the fourth through hole 506
  • the conductive material and the metal part 508 can be prepared in the same layer at the same time.
  • the metal portion 508 may be electrically connected to the second source and drain layer through the fourth through hole 506; specifically, the metal portion 508 may be electrically connected to the second source and drain layer through the fourth through hole 506.
  • the second metal portion 409 in the second source and drain layer is electrically connected.
  • the touch electrode 801 is disposed on the intermediate layer 503, and the touch electrode 801 may be disposed on a side of the first metal part 408 away from the second active layer 403,
  • the constituent material of the touch electrode 801 may be a metal or non-metal conductive material.
  • touch electrode 801, the first electrode 601, and the metal part 508 can be prepared in the same layer and at the same time.
  • the device layer 80 further includes an insulating layer 802 disposed on the intermediate layer 503, the second metal layer 508, the first electrode 601, and the touch On the electrode 801, the insulating layer 802 is used to insulate a conductive material, and the constituent material of the insulating layer 802 can refer to the related description of the constituent material of the first passivation layer 501.
  • the insulating layer 802 is provided with a common electrode through hole 8031, the common electrode through hole 8031 is in contact with the touch electrode 801 and penetrates the insulating layer 802, and the common electrode through hole 8031 is provided There are conductive materials.
  • the device layer 80 further includes at least one common electrode 803, and the at least one common electrode 803 may be electrically connected to each other, the common electrode 803 is provided on the insulating layer 802, and the
  • the constituent material of the common electrode 803 may be a metal conductive material; it is understandable that the conductive material in the common electrode through hole 8031 may be the same as the constituent material of the common electrode 803, therefore, the common electrode through hole 8031
  • the conductive material can be made integrally with the common electrode 803.
  • the common electrode 803 can be disposed above the common electrode through hole 8031. Further, the common electrode through hole 8031
  • the conductive material in and the common electrode 803 can be prepared in the same layer at the same time.
  • the device layer 80 further includes a second passivation layer 804, the second passivation layer 804 is disposed on the insulating layer 802 and the common electrode 803, and the second passivation layer
  • the constituent material of 804 refer to the related description of the constituent material of the first passivation layer 502.
  • the through hole further includes a fifth through hole 504, and the fifth through hole 504 is disposed opposite to the first metal part 408; specifically, the fifth through hole 504 is disposed in the On the second insulating layer 50 and the device layer 80, further, as shown in FIG. 1, the fifth through hole 504 is arranged in contact with the first metal portion 408, and the fifth through hole 504 penetrates Part of the first passivation layer 501, all of the flat layer 502, all of the intermediate layer 503, all of the insulating layer 802, and all of the second passivation layer 804; in the fifth through hole 504 A conductive material is provided.
  • the pixel electrode 70 is disposed on the second passivation layer 804, and the pixel electrode 70 may correspond to the first thin film transistor layer 20 one-to-one.
  • a pixel electrode 70 may include a plurality of pixel electrode portions 701, and the plurality of pixel electrode portions 701 may be arranged parallel to each other along a predetermined direction and separated by a predetermined distance. It is understandable that, The pixel electrode 70 in FIG. 1 can be seen as a cross-sectional view along the AB direction in FIG. 2, wherein the plurality of pixel electrode portions 701 are connected to each other, that is, the pixel electrode portion 701 is connected to each other. The electrical conditions are the same.
  • the conductive material in the fifth through hole 504 may be the same as the constituent material of the pixel electrode 70. Therefore, the conductive material in the fifth through hole 504 may be integrated with a pixel electrode portion 701. For example, as shown in FIG. 1, the one pixel electrode portion 701 may be arranged above the fifth through hole 504 or arranged in contact with both ends of the fifth through hole 504, and further, the fifth through hole 504 The conductive material in the hole 504 and the pixel electrode portion 701 can be prepared in the same layer at the same time.
  • the pixel electrode 70 may be electrically connected to the second source and drain layer through the fifth through hole 504; specifically, the pixel electrode 70 may be electrically connected to the second source and drain layer through the fifth through hole 504
  • the first metal portion 408 in the second source/drain layer is electrically connected; in combination with the above, the first metal portion 408 in the second source/drain layer may be connected to the first through hole 406
  • the first source electrode 206 or the first drain electrode 207 in the first source-drain layer is electrically connected; in general, the pixel electrode 70 can be connected to the first source-drain layer through the above-mentioned connection method. Electrical connection, wherein the first source and drain layer can control the voltage of the corresponding pixel electrode 70.
  • the device layer 80 further includes a third passivation layer 90, the third passivation layer 90 is provided on the pixel electrode 70 and the second passivation layer 804, the second passivation layer
  • the constituent materials of the three passivation layer 90 can refer to the related description of the constituent materials of the first passivation layer 502.
  • the sensor layer 60 further includes a photosensitive device through hole 604, and the photosensitive device through hole 604 is disposed opposite to the first electrode 601; specifically, the photosensitive device through hole 604 is disposed in the On the device layer 80, further, as shown in FIG. 1, the photosensitive device through hole 604 is arranged in contact with the first electrode 601, and the photosensitive device through hole 604 penetrates part of the insulating layer 802 and all of the The second passivation layer 804, and all the third passivation layers 90.
  • the sensor layer 60 further includes a photosensitive device layer 602, the photosensitive device layer 602 is disposed in the photosensitive device through hole 604, specifically, as shown in FIG. 1, the photosensitive device layer 602 Filling the photosensitive device through hole 604, the photosensitive device layer 602 may include an electron transport layer 6021, a photosensitive layer 6022, and a hole transport layer 6023 sequentially disposed on the first electrode 601.
  • the composition material of the photosensitive layer 6022 may include at least one of silicon oxide and amorphous silicon, but the present invention is not limited to this. Any material that can generate photocurrent after illumination can be used as the material.
  • the through hole further includes a sixth through hole 901, and the sixth through hole 901 is disposed opposite to the second metal layer 508; specifically, the sixth through hole 901 is disposed in the On the device layer 80, further, as shown in FIG. 1, the sixth through hole 901 is arranged in contact with the second metal layer 508, and the sixth through hole 901 penetrates part of the insulating layer 802 and all of the insulating layer 802.
  • the second passivation layer 804 and all the third passivation layers 90; the sixth through hole 901 is provided with a conductive material.
  • the sensor layer 60 further includes a second electrode 603, the second electrode 603 is disposed on the photosensitive device layer 602 and the third passivation layer 90, the second electrode 603 It may correspond to the first electrode 601 one-to-one; wherein, the constituent material of the second electrode 603 may include a transparent conductive material.
  • the transparent conductive material may include indium tin oxide, indium zinc oxide, and aluminum. At least one of metal oxides such as tin oxide, aluminum zinc oxide, or indium germanium zinc oxide.
  • the conductive material in the sixth through hole 901 may be the same as the constituent material of the second electrode 603, therefore, the conductive material in the sixth through hole 901 may be integrated with the second electrode 603
  • the second electrode 603 may be arranged above the sixth through hole 901 or arranged in contact with both ends of the sixth through hole 901. Further, the sixth through hole
  • the conductive material in 901 and the second electrode 603 can be prepared in the same layer at the same time.
  • the second electrode 603 is electrically connected to the metal part 508 through the sixth through hole 901; in combination with the above, the metal part 508 can be connected to the second through hole 506 through the fourth through hole 506.
  • the second metal portion 409 in the source-drain layer is electrically connected; in general, the second electrode 603 can be electrically connected to the second metal portion 409 through the above-mentioned connection method.
  • the second electrode 603 is electrically connected to the second metal portion 409, and the first electrode 601 is electrically connected to the second drain 405, that is, the second drain 405 ,
  • the metal layer 4012 can constitute a storage capacitor.
  • the photocurrent generated by the photosensitive device layer 602 is charged to the upper and lower sides of the storage capacitor through the first electrode 601 and the second electrode 603.
  • the storage capacitor is transferred out of the storage capacitor.
  • the switching signal in the second gate 4011 can control the exposure time, exposure stage, the switching signal in the second gate 4011 causes the second thin film transistor layer 40 to close, the exposure ends, so
  • the storage capacitor transfers its own charge to form a current, and the switching signal in the second gate 4011 makes the second thin film transistor layer 40 of the switching transistor open, and the second source 403 is used to read the
  • the electrical signal corresponding to the photocurrent generated by the photosensitive device layer 602 undergoes subsequent signal conversion to perform fingerprint identification.
  • FIG. 1 illustrates an example of an LCD display panel.
  • the display panel in the present invention may also be an OLED or other display panels, as long as the second thin film transistor layer 40 and the first
  • the thin film transistor layer 20 adopts the above-mentioned stacked arrangement, which all belong to the protection scope of the present invention.
  • the present invention also provides a manufacturing method of the display panel, the method includes the steps shown in FIG. 3, and the steps S10-S90 correspond to the schematic scene diagrams shown in FIGS. 4-5.
  • the substrate 10 includes a substrate 101, a light shielding layer 102 provided on the substrate 101, and a buffer layer 103 provided on the substrate 101 and the light shielding layer 102.
  • the buffer layer 103 includes a first buffer layer 1031 and a second buffer layer 1032 that are sequentially disposed on the substrate 101 and the light shielding layer 102.
  • the substrate 101 For the substrate 101, the light-shielding layer 102, the first buffer layer 1031, and the second buffer layer 1032, reference may be made to the related description in the above-mentioned display panel.
  • the first thin film transistor layer 20 including a first source and drain layer.
  • the first thin film transistor layer 20 includes a first active layer 201 provided on the substrate 10, a first active layer 201 provided on the first active layer 201 and the first active layer 201 on the substrate 10.
  • the first source 206 and the first drain 207 reference may be made to the related description in the above-mentioned display panel.
  • the first insulating layer 30 is provided on the first source 206, the first drain 207, and the first inner insulating layer 204, wherein the first insulating layer 30
  • the constituent materials of may refer to the related description of the constituent materials of the first inner insulating layer 204 in the above-mentioned display panel.
  • the second thin film transistor layer 40 includes a second gate layer disposed on the first insulating layer 30, and a second gate insulating layer 402 disposed on the second gate layer.
  • the first through hole 406 in the subsequent step S50 is provided on the second gate insulating layer 402 in the first insulating layer 30 and the second thin film transistor layer 40, and the third The through hole 407 is provided on the second gate insulating layer 402 in the second thin film transistor layer 40, so the step S40 should be understood as: forming a second gate layer on the first insulating layer 30, and A second active layer 403 is formed on the second gate layer.
  • the step S40 may include the following steps, corresponding to the schematic diagram of the scene as shown in FIG. 6.
  • the metal layer 4012 and the second gate 4011 are provided in the same layer and separated by a predetermined distance.
  • the metal layer 4012 can refer to the relevant description in the above display panel.
  • the second gate insulating layer 402 can refer to the related description in the above-mentioned display panel.
  • the second active layer 403 is disposed opposite to the second gate 4011, and the second active layer 403 can refer to the related description in the above-mentioned display panel.
  • a through hole 406 and the third through hole 407 are both provided with conductive materials, and the first through hole 406 is used to electrically connect the second source and drain layer and the first source and drain layer, so The third through hole 407 is used to electrically connect the second source and drain layer and the second gate layer.
  • the first through hole 406 is disposed opposite to the first source electrode 206, or the first through hole 406 is disposed opposite to the first drain electrode 207.
  • a through hole 406 is disposed opposite to the first source electrode 206, and the first through hole 406 can refer to the related description in the above-mentioned display panel.
  • the third through hole 407 is disposed opposite to the metal layer 4012, and the third through hole 407 may refer to the related description in the above-mentioned display panel.
  • the second thin film transistor layer 40 further includes a second source-drain layer disposed on both ends of the second gate insulating layer 402 and the second active layer 403, and the second source-drain layer It includes a second source 404 and a second drain 405. That is, after the step S50, the step S40 may further include the following steps:
  • the second source-drain layer including a second source 404 and a second drain 405
  • the first metal portion 408, and the second metal portion 409, the second source 404 and the second drain 405 are respectively provided on the left/right, right/left sides of the second gate 4011
  • the first metal portion 408 is provided on the side of the second source 404 away from the second gate 4011
  • the second metal portion 409 is provided on the second drain 405 away from the second gate.
  • the metal layer 4012 is disposed opposite to the second metal portion 409.
  • the second source 404 the second drain 405, the first metal portion 408, and the second metal portion 409, reference may be made to the related description in the above-mentioned display panel.
  • the second insulating layer 50 includes a first passivation layer 501 provided on the second thin film transistor layer 40, a flat layer 502 provided on the first passivation layer 501, and a An intermediate layer 503 on the flat layer 502.
  • a fifth through hole 504, a second through hole 505, and a fourth through hole 506 are formed on the second insulating layer 50, and the fifth through hole 504, the second through hole 505, and the Conductive materials are provided in the fourth through holes 506.
  • the fifth through hole 504 is disposed opposite to the first metal portion 408, the second through hole 505 is disposed opposite to the second source 404, and the fourth through hole 506 is opposite to The second metal parts 409 are arranged opposite to each other.
  • a device layer 80 is formed on the second insulating layer 50, the device layer 80 includes a pixel electrode 70, a sensor layer 60, and a metal part 508, and the sensor layer 60 includes a first electrode 601 and a second electrode 603
  • the fifth through hole 504 is used to electrically connect the pixel electrode 70 and the second source and drain layer
  • the second through hole 505 is used to connect the first electrode 601 to the second
  • the source-drain layer is electrically connected
  • the fourth through hole 506 is used to electrically connect the metal portion 508 with the second source-drain layer.
  • step S80 may include the following steps, corresponding to the schematic diagram of the scene as shown in FIG. 7.
  • the first electrode 601 is disposed on the intermediate layer 503, and the first electrode 601 can refer to the related description in the above-mentioned display panel.
  • the metal part 508 is disposed on the intermediate layer 503, and the metal part 508 is arranged in the same row as the first electrode 601 and separated by a predetermined distance.
  • the metal part 508 can refer to The relevant description in the above display panel.
  • the device layer 80 further includes a touch electrode 801, the touch electrode 801 is disposed on the intermediate layer 503, and the touch electrode 801 may be disposed on the first metal part 408 away from On one side of the second active layer 403, the touch electrode 801 can refer to the related description in the above-mentioned display panel.
  • first electrode 601, the metal portion 508, and the touch electrode 801 can be prepared at the same time and in the same layer.
  • the insulating layer 802 is provided on the intermediate layer 503, the second metal layer 508, the first electrode 601, and the touch electrode 801, and the insulating layer 802 can refer to The relevant description in the above display panel.
  • the insulating layer 802 is provided with a common electrode through hole 8031, and the common electrode 803 can refer to the related description in the above-mentioned display panel.
  • the insulating layer 802 is provided with a first sub-via 9011 at a position opposite to the metal portion 508, and the first sub-via 9011 is provided in contact with the metal portion 508 and penetrates The insulating layer 802.
  • a first photosensitive device through hole 6041 is provided on the insulating layer 802 opposite to the first electrode 601, and the first photosensitive device through hole 6041 is in contact with the first electrode 601
  • the insulating layer 802 is disposed and penetrates through the insulating layer 802.
  • the step S803 may include the following steps, corresponding to the schematic scenario diagrams shown in FIGS. 8-9.
  • the common electrode 803 may be electrically connected to the touch electrode 801 through the common electrode through hole 8031, and the common electrode 803 may refer to the related description in the above display panel.
  • the second passivation layer 804 is provided on the insulating layer 802 and the common electrode 803, and the second passivation layer 804 can refer to the related description in the above display panel.
  • a second photosensitive device through hole 6042 is provided on the second passivation layer 804 opposite to the first photosensitive device through hole 6041, and the second photosensitive device through hole 6042 is connected to the first photosensitive device through hole 6042.
  • a photosensitive device through hole 6041 is provided in contact and penetrates the second passivation layer 804.
  • the second passivation layer 804 is provided with a second sub-via 9012 at a position opposite to the first sub-via 9011, and the second sub-via 9012 communicates with the first sub-via 9012.
  • the hole 9011 is provided in contact and penetrates the second passivation layer 804.
  • the fifth through hole 504 is provided on the insulating layer 802 and the second passivation layer 804 in the device layer 80 in addition to the fifth through hole 504. Refer to the related description in the above display panel.
  • the pixel electrode 70 may correspond to the first thin film transistor layer 20 one to one, and the pixel electrode 70 may include a plurality of pixel electrode portions 701, the pixel electrode 70, and the pixel For the electrode part 701, reference may be made to the related description in the above-mentioned display panel.
  • step of forming the sixth through hole 901 in the subsequent step S90 is performed before the second electrode 603 is prepared, so the step S90 can be performed after the step S8033.
  • a sixth through hole 901 is formed on the device layer 80, and a conductive material is disposed in the sixth through hole 901.
  • the sixth through hole 901 connects the second electrode 603 with the metal portion 508. Electrical connection.
  • a third passivation layer 90 is formed on the second passivation layer 804 and the pixel electrode 70, and the third passivation layer 90 is patterned to form the sixth through hole 901 , And a conductive material is arranged in the sixth through hole 901.
  • the third passivation layer 90 is provided on the pixel electrode 70 and the second passivation layer 804, and the third passivation layer 90 can refer to the related description in the above display panel .
  • a third photosensitive device through hole 6043 is provided on the third passivation layer 90 opposite to the second photosensitive device through hole 6042, and the third photosensitive device through hole 6043 is connected to the second photosensitive device.
  • the through hole 6042 is arranged in contact and penetrates the third passivation layer 90.
  • the first photosensitive device through hole 6041, the second photosensitive device through hole 6042, and the third photosensitive device through hole 6043 together constitute a photosensitive device Through hole 604.
  • the photosensitive device through hole 604 is disposed opposite to the first electrode 601, and the photosensitive device through hole 604 can refer to the related description in the above-mentioned display panel.
  • the third passivation layer 90 is provided with a third sub-via 9013 at a position opposite to the second sub-via 9012, and the third sub-via 9013 is in contact with the second sub-via 9012
  • the third passivation layer 90 is disposed and penetrated, and the first through hole 9011, the second through hole 9012, and the third through hole 9013 together form the sixth through hole 901.
  • the sixth through hole 901 is disposed opposite to the second metal layer 508, and the sixth through hole 901 can refer to the related description in the above-mentioned display panel.
  • the sensor layer 60 further includes a photosensitive device layer 602 disposed on the first electrode 601 and the second electrode 603 disposed on the photosensitive device layer 602. That is, after the step S50, the step S803 may further include the following steps:
  • the photosensitive device layer 602 may include an electron transport layer 6021, a photosensitive layer 6022, and a hole transport layer 6023 sequentially disposed on the first electrode 601.
  • the photosensitive device layer 602 may refer to the above display The relevant description in the panel.
  • the second electrode 603 may correspond to the first electrode 601 one-to-one, and the second electrode 603 may refer to the related description in the above-mentioned display panel.
  • the present invention provides a display panel, a display device, and a method for manufacturing a display panel.
  • the display panel includes a substrate, a first thin film transistor layer, a first insulating layer, a second thin film transistor layer, a second insulating layer, a device layer, And a plurality of through holes, the second thin film transistor layer is disposed on the first thin film transistor layer, and the plurality of through holes electrically connect the related film layers.
  • the present invention increases the optical sensor receiving The received light improves the accuracy of the optical fingerprint recognition inside the display panel.
  • the present invention provides a display panel, a display device, and a manufacturing method of a display panel.
  • the display panel includes a substrate, a first thin film transistor layer, a first insulating layer, a second thin film transistor layer, and a second thin film transistor layer. Two insulating layers, a device layer, and a plurality of through holes, the second thin film transistor layer is disposed on the first thin film transistor layer, and the plurality of through holes electrically connect related film layers,
  • the invention increases the light received by the optical sensor and improves the accuracy of the optical fingerprint recognition inside the display panel.

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Abstract

本发明提供了显示面板，包括层叠设置的第一薄膜晶体管层、第二薄膜晶体管层、器件层；第一薄膜晶体管层包括第一源漏极层，第二薄膜晶体管层包括第二栅极层、第二源漏极层，器件层包括像素电极、第一电极、第二电极；像素电极与第一源漏极层电性连接，第一电极与第一源漏极层电性连接，第二电极与第二栅极层电性连接。

Description

显示面板及其制备方法以及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及显示器件的制造，具体涉及显示面板及其制备方法以及显示装置。
 背景技术
目前，对于LCD（Liquid Crystal Display，液晶显示器）显示屏，由于背光源的光损失以及开口率的大小限制等因素，具体的，所述LCD显示屏中的显示薄膜晶体管器件、传感器薄膜晶体管器件以及光学传感器同层设置，使得光学传感器接收到的光线较少，从而降低了LCD显示屏内部的光学指纹识别的精度。
因此，有必要提供一种可以提高显示面板的光学指纹识别的精度的显示面板及其制备方法以及显示装置。
 技术问题
本发明的目的在于提供显示面板、显示装置、以及显示面板的制作方法，通过将第二薄膜晶体管层与第一薄膜晶体管层进行层叠设置，且通过第一通孔、第二通孔、第三通孔、第四通孔、第五通孔、以及第六通孔，将相关的膜层之间电性连接，解决了现有技术中由于光学传感器接收到的光线较少，而造成的LCD显示屏内部的光学指纹识别的精度较低的问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种显示面板，所述显示面板包括：衬底、第一薄膜晶体管层、第一绝缘层、第二薄膜晶体管层、第二绝缘层、器件层、以及多个通孔；
所述第一薄膜晶体管层，设置在所述衬底上，所述第一薄膜晶体管层包括第一源漏极层；
所述第一绝缘层，设置在所述第一薄膜晶体管层上；
所述第二薄膜晶体管层，设置在所述第一绝缘层上，所述第二薄膜晶体管层包括第二栅极层、第二源漏极层；
所述第二绝缘层，设置在所述第二薄膜晶体管层上；
所述器件层，设置在所述第二绝缘层上，所述器件层包括像素电极、传感器层、以及金属部，所述传感器层包括第一电极、第二电极；
所述多个通孔包括第一通孔、第二通孔、第三通孔、第四通孔、第五通孔、以及第六通孔，所述第一通孔、所述第二通孔、所述第三通孔、所述第四通孔、所述第五通孔、以及所述第六通孔内均设置有导电材料；
所述第一通孔设置在所述第一绝缘层、以及所述第二薄膜晶体管层上，所述第五通孔设置在所述第二绝缘层、以及所述器件层上，所述像素电极通过所述第五通孔与所述第二源漏极层电性连接，所述第二源漏极层通过所述第一通孔与所述第一源漏极层电性连接，使得所述像素电极和所述第一源漏极层电性连接；
所述第二通孔设置在所述第二绝缘层上，所述第一电极通过所述第二通孔与所述第二源漏极层电性连接；
所述第三通孔设置在所述第二薄膜晶体管层上，所述第四通孔设置在所述第二绝缘层上，所述第六通孔设置在所述器件层上，所述第二电极通过所述第六通孔与所述金属部电性连接，所述金属部通过所述第四通孔与所述第二源漏极层电性连接，所述第二源漏极层通过所述第三通孔与所述第二栅极层电性连接，使得所述第二电极和所述第二栅极层电性连接。
在一实施例中，所述第二栅极层包括第二栅极，所述第二源漏极层包括第二源极、第二漏极，所述第二源极、所述第二漏极分别设于所述第二栅极的左/右、右/左两侧；
所述源漏极层还包括第一金属部、第二金属部，所述第一金属部设于所述第二源极远离所述第二栅极的一侧，所述第二金属部设于所述第二漏极远离所述第二栅极的一侧；
所述像素电极通过所述第五通孔与所述第一金属部电性连接，所述第一金属部通过所述第一通孔与所述第一源漏极层电性连接，使得所述像素电极和所述第一源漏极层电性连接。
在一实施例中，所述第一电极通过所述第二通孔与所述第二漏极电性连接。
在一实施例中，所述第二栅极层还包括金属层，所述金属层与所述第二金属部相对设置；
所述第二电极依次通过所述第六通孔、所述第四通孔与所述第二金属部电性连接，所述第二金属部通过所述第三通孔与所述金属层电性连接，使得所述第二电极和所述金属层电性连接。
在一实施例中，所述第二薄膜晶体管层还包括第二有源层，所述第二有源层设于所述第二栅极层上方，所述第二有源层的组成材料包括非晶硅或者铟镓锌氧化物中的一种。
在一实施例中，所述第一薄膜晶体管层还包括第一有源层，所述第一有源层设于所述第一源漏极层下方，所述第一有源层的组成材料包括多晶硅。
本发明实施例还提供一种显示装置，所述显示装置包括显示面板，所述显示面板包括：衬底、第一薄膜晶体管层、第一绝缘层、第二薄膜晶体管层、第二绝缘层、器件层、以及多个通孔；
所述第一薄膜晶体管层，设置在所述衬底上，所述第一薄膜晶体管层包括第一源漏极层；
所述第一绝缘层，设置在所述第一薄膜晶体管层上；
所述第二薄膜晶体管层，设置在所述第一绝缘层上，所述第二薄膜晶体管层包括第二栅极层、第二源漏极层；
所述第二绝缘层，设置在所述第二薄膜晶体管层上；
所述器件层，设置在所述第二绝缘层上，所述器件层包括像素电极、传感器层、以及金属部，所述传感器层包括第一电极、第二电极；
所述多个通孔包括第一通孔、第二通孔、第三通孔、第四通孔、第五通孔、以及第六通孔，所述第一通孔、所述第二通孔、所述第三通孔、所述第四通孔、所述第五通孔、以及所述第六通孔内均设置有导电材料；
所述第一通孔设置在所述第一绝缘层、以及所述第二薄膜晶体管层上，所述第五通孔设置在所述第二绝缘层、以及所述器件层上，所述像素电极通过所述第五通孔与所述第二源漏极层电性连接，所述第二源漏极层通过所述第一通孔与所述第一源漏极层电性连接，使得所述像素电极和所述第一源漏极层电性连接；
所述第二通孔设置在所述第二绝缘层上，所述第一电极通过所述第二通孔与所述第二源漏极层电性连接；
所述第三通孔设置在所述第二薄膜晶体管层上，所述第四通孔设置在所述第二绝缘层上，所述第六通孔设置在所述器件层上，所述第二电极通过所述第六通孔与所述金属部电性连接，所述金属部通过所述第四通孔与所述第二源漏极层电性连接，所述第二源漏极层通过所述第三通孔与所述第二栅极层电性连接，使得所述第二电极和所述第二栅极层电性连接。
在一实施例中，所述第二栅极层包括第二栅极，所述第二源漏极层包括第二源极、第二漏极，所述第二源极、所述第二漏极分别设于所述第二栅极的左/右、右/左两侧；
所述源漏极层还包括第一金属部、第二金属部，所述第一金属部设于所述第二源极远离所述第二栅极的一侧，所述第二金属部设于所述第二漏极远离所述第二栅极的一侧；
所述像素电极通过所述第五通孔与所述第一金属部电性连接，所述第一金属部通过所述第一通孔与所述第一源漏极层电性连接，使得所述像素电极和所述第一源漏极层电性连接。
在一实施例中，所述第一电极通过所述第二通孔与所述第二漏极电性连接。
在一实施例中，其中，所述第二栅极层还包括金属层，所述金属层与所述第二金属部相对设置；
所述第二电极依次通过所述第六通孔、所述第四通孔与所述第二金属部电性连接，所述第二金属部通过所述第三通孔与所述金属层电性连接，使得所述第二电极和所述金属层电性连接。
在一实施例中，所述第二薄膜晶体管层还包括第二有源层，所述第二有源层设于所述第二栅极层上方，所述第二有源层的组成材料包括非晶硅或者铟镓锌氧化物中的一种。
在一实施例中，所述第一薄膜晶体管层还包括第一有源层，所述第一有源层设于所述第一源漏极层下方，所述第一有源层的组成材料包括多晶硅。
本发明实施例还提供一种显示面板的制作方法，所述方法包括：
提供一衬底；
在所述衬底上形成第一薄膜晶体管层，所述第一薄膜晶体管层包括第一源漏极层；
在所述第一薄膜晶体管层上形成第一绝缘层；
在所述第一绝缘层上形成第二薄膜晶体管层，所述第二薄膜晶体管层包括第二栅极层、第二源漏极层；
在所述第一绝缘层和所述第二薄膜晶体管层上形成第一通孔，以及在所述第二薄膜晶体管层上形成第三通孔，并且在所述第一通孔、所述第三通孔内均设置导电材料，所述第一通孔用于将所述第二源漏极层与所述第一源漏极层电性连接，所述第三通孔用于将所述第二源漏极层与所述第二栅极层电性连接；
在所述第二薄膜晶体管层上形成第二绝缘层；
在所述第二绝缘层上形成第五通孔、第二通孔、以及第四通孔，并且在所述第五通孔、所述第二通孔、以及所述第四通孔内均设置导电材料；
在所述第二绝缘层上形成器件层，所述器件层包括像素电极、传感器层、以及金属部，所述传感器层包括第一电极、第二电极，所述第五通孔用于将所述像素电极与所述第二源漏极层电性连接，所述第二通孔用于将所述第一电极与所述第二源漏极层电性连接，所述第四通孔用于将所述金属部与所述第二源漏极层电性连接；
在所述器件层上形成第六通孔，并且在所述第六通孔内设置导电材料，所述第六通孔将所述第二电极与所述金属部电性连接。
在一实施例中，所述在所述第一绝缘层上形成第二薄膜晶体管层，所述第二薄膜晶体管层包括第二栅极层、第二源漏极层的步骤包括：
在所述第一绝缘层上形成第二栅极层，所述第二栅极层包括第二栅极、金属层；
在所述第一绝缘层以及所述第二栅极层上形成第二栅极绝缘层；
在所述第二栅极绝缘层上形成第二有源层；
在所述第二有源层、所述第二栅极绝缘层上形成第二源漏极层，所述第二源漏极层包括第二源极、第二漏极、第一金属部、以及第二金属部，所述第二源极、所述第二漏极分别设于所述第二栅极的左/右、右/左两侧，所述第一金属部设于所述第二源极远离所述第二栅极的一侧，所述第二金属部设于所述第二漏极远离所述第二栅极的一侧，所述金属层与所述第二金属部相对设置。
在一实施例中，所述在所述第二绝缘层上形成器件层，所述器件层包括像素电极和传感器层，所述传感器层包括第一电极、第二电极的步骤包括：
在所述第二绝缘层上形成所述第一电极；
在所述第二绝缘层、所述第一电极上形成绝缘层；
在所述绝缘层上形成所述像素电极、所述第二电极。
 有益效果
本发明提供了显示面板、显示装置、以及显示面板的制作方法，所述显示面板包括衬底、第一薄膜晶体管层、第一绝缘层、第二薄膜晶体管层、第二绝缘层、器件层、以及多个通孔，所述第二薄膜晶体管层设置在所述第一薄膜晶体管层上，且所述多个通孔将相关的膜层之间进行电性连接，本发明增加了光学传感器接收到的光线，提高了显示面板内部的光学指纹识别的精度。
 附图说明
下面通过附图来对本发明进行进一步说明。需要说明的是，下面描述中的附图仅仅是用于解释说明本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的显示面板的剖面示意图。
图2为本发明实施例提供的像素电极的俯视示意图。
图3为本发明实施例提供的显示面板的制作方法的流程图。
图4为本发明实施例提供的显示面板的制作方法的第一种场景示意图。
图5为本发明实施例提供的显示面板的制作方法的第二种场景示意图。
图6为本发明实施例提供的显示面板的制作方法的第三种场景示意图。
图7为本发明实施例提供的显示面板的制作方法的第四种场景示意图。
图8为本发明实施例提供的显示面板的制作方法的第五种场景示意图。
图9为本发明实施例提供的显示面板的制作方法的第六种场景示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“上”、“下”、“两侧”等指示的方位或位置关系为基于附图所示的方位或位置关系，例如，“上”只是表面在物体上方，具体指代正上方、斜上方、上表面都可以，只要居于物体水平之上即可；“两侧”是指代图中可以体现出的物体的相对的两个位置，所述两个位置可以和物体直接/间接接触，以上方位或位置关系仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。另外，还需要说明的是，附图提供的仅仅是和本发明关系比较密切的结构和步骤，省略了一些与发明关系不大的细节，目的在于简化附图，使发明点一目了然，而不是表明实际中装置和方法就是和附图一模一样，不作为实际中装置和方法的限制。
需要注意的是，术语“长度”是中性词，不表示偏向长或短，只是表示为一个预设值，数值不确定，会根据实际情况而定。
另外，还需要说明的是，附图提供的仅仅是和本发明关系比较密切的结构和步骤，省略了一些与发明关系不大的细节，目的在于简化附图，使发明点一目了然，而不是表明实际中装置和方法就是和附图一模一样，不作为实际中装置和方法的限制。
本发明提供显示装置，所述显示装置包括如图1所示的显示面板。
在一实施例中，如图1所示，所述显示面板00包括：衬底10、第一薄膜晶体管层20、第一绝缘层30、第二薄膜晶体管层40、第二绝缘层50、器件层80以及多个通孔。
其中，所述第一薄膜晶体管层20设置在所述衬底10上，所述第一绝缘层30设置在所述第一薄膜晶体管层20上，所述第二薄膜晶体管层40设置在所述第一绝缘层30上，所述第二绝缘层50设置在所述第二薄膜晶体管层40上，所述传感器层60、所述像素电极70设置在所述第二绝缘层50上。
在一实施例中，所述衬底10包括基板101、设于所述基板101上的遮光层102、以及设于所述基板101和所述遮光层102上的缓冲层103。
其中，所述基板101可以为玻璃基板，所述玻璃基板的组成材料可以包括石英粉、碳酸锶、碳酸钡、硼酸、硼酐、氧化铝、碳酸钙、硝酸钡、氧化镁、氧化锡、氧化锌中的至少一种。
其中，所述遮光层102可以为非透光膜层，所述非透光膜层的组成材料可以包括黑色树脂或者遮光金属等反射率较低的材料，具体的，所述遮光金属可以为Cu、Mo。可以理解的，当所述显示面板00包括背光源时，所述遮光层102可以避免所述背光源的光线照射到第一薄膜晶体管层20上而造成的漏电流问题。
在一实施例中，所述缓冲层103包括依次设于所述基板101和所述遮光层102上的第一缓冲层1031、第二缓冲层1032。
其中，所述第一缓冲层1031的组成材料可以包括氮化硅，所述第二缓冲层1032的组成材料可以包括氧化硅。
在一实施例中，所述第一薄膜晶体管层20包括设于所述衬底10上的第一有源层201、设于所述第一有源层201以及所述衬底10上的第一栅极绝缘层202、设于所述第一栅极绝缘层202上的第一栅极层203、设于所述第一栅极层203以及所述第一栅极绝缘层202上的第一内部绝缘层204、设置在所述第一栅极绝缘层202、第一内部绝缘层204上的两个源漏极通孔205、以及设置在所述第一内部绝缘层204、所述两个源漏极通孔205上的第一源漏极层，所述第一源漏极层包括第一源极206、第一漏极207。
其中，所述第一有源层201的组成材料包括多晶硅。具体的，所述第一有源层201可以采用低温多晶硅技术制成。可以理解的，采用低温多晶硅技术制备所述第一有源层201，可以具备较高的电子迁移率，这样当所述第一薄膜晶体管层20给对应的所述像素电极70充电时，可以产生较大的驱动电流，以提高充电速度。
进一步的，所述第一有源层201的两端可以掺杂一些掺杂物，以分别形成第一源极接触区2011、第一漏极接触区2022，所述第一源极接触区2011用于连接所述第一源极206与所述第一有源层201，所述第一漏极接触区2011用于连接所述第一漏极207与所述第一有源层201，另外的，第一源极接触区2011、所述第一漏极接触区2022还可以用作欧姆接触层，以减少第一有源层201与所述第一源极206/所述第一漏极207之间的接触电阻。
具体的，所述掺杂物可以包括磷离子，可以通过控制所述磷离子的浓度，以形成N+型掺杂或者N-型掺杂；例如，可以在所述第一源极接触区2011/第一漏极接触区2022靠近所述第一有源层201的一侧形成N-型掺杂，在所述第一源极接触区2011/第一漏极接触区2022靠近所述第一有源层201的一侧形成N+型掺杂，所述N-型掺杂可以减小热载流子的冲击，提高所述第一薄膜晶体管层20的稳定性，所述N+型掺杂可以形成欧姆接触层。
其中，所述第一栅极绝缘层202的组成材料可以包括无机介电材料、有机介电材料中的至少一种。具体的，所述无机介电材料可以包括氧化硅、氮化硅、氮氧化硅中的至少一种，所述有机介电材料可以为聚酰亚胺系树脂、环氧系树脂或压克力系树脂等高分子材料。
其中，所述第一栅极层203的组成材料可以包括金属、金属氧化物、金属氮化物、金属氮氧化物等导电材料中的至少一种。具体的，所述金属可以为不限于Cu、Al、Mo、Ti等金属材料。
其中，所述第一内部绝缘层204的组成材料可以参考所述第一栅极绝缘层202的组成材料的相关描述。
其中，所述两个源漏极通孔205分别设于所述第一栅极层203两侧，所述两个源漏极通孔205中设置有导电材料。
其中，所述第一源极206、所述第一漏极207两者之间的相对位置不做限定，图1中以所述第一源极206、所述第一漏极207分别设置在所述第一栅极层203左侧、右侧的所述源漏极通孔205为例，所述第一源极206、所述第一漏极207的组成材料可以参考所述第一栅极层203的组成材料的相关描述；可以理解的，所述两个源漏极通孔205中的导电材料可以与所述第一源极206、所述第一漏极207的组成材料相同，因此，所述两个源漏极通孔205中的导电材料可以分别与所述第一源极206、所述第一漏极207一体制作，例如，如图1所示，所述第一源极206、所述第一漏极207可以分别设于所述两个源漏极通孔205上方，进一步的，所述两个源漏极通孔205中的导电材料、所述第一源极206、以及所述第一漏极207可以同层、同时制备。
在一实施例中，所述第一绝缘层30设于所述第一源极206、所述第一漏极207以及所述第一内部绝缘层204上，其中，所述第一绝缘层30的组成材料可以参考所述第一内部绝缘层204的组成材料的相关描述。
在一实施例中，所述第二薄膜晶体管层40包括设于所述第一绝缘层30上的第二栅极层、设于所述第二栅极层上的第二栅极绝缘层402、设于所述第二栅极绝缘层402上的第二有源层403、以及设于第二栅极绝缘层402、以及所述第二有源层403两端的第二源漏极层，所述第二源漏极层包括第二源极404、第二漏极405。
在一实施例中，所述第二栅极层包括第二栅极4011，所述第二栅极4011与所述第二有源层403相对设置，所述第二源极404、所述第二漏极405分别设于所述第二栅极4011的左、右两侧，所述第二栅极4011用于控制所述第二源极404与所述第二漏极405之间的导通情况，即所述第二栅极4011、第二源极404、以及所述第二漏极405可以构成一完整的薄膜晶体管，其中所述第二栅极4011的组成材料可以参考所述第一栅极层203的组成材料的相关描述。
其中，所述第二栅极绝缘层402的组成材料可以参考所述第一栅极绝缘层202的组成材料的相关描述。
其中，所述第二有源层403的组成材料可以包括非晶硅或者铟镓锌氧化物中的一种。可以理解的，所述采用非晶硅或者铟镓锌氧化物制备所述第二有源层403，可以具备低漏电流，以防止曝光情况下，所述第二薄膜晶体管层40漏电对所述传感器层60的信号造成干扰。
具体的，当所述第二有源层403的组成材料包括所述铟镓锌氧化物时，所述第二有源层403中靠近所述第二源极404、第二漏极405的区域可以不需要掺杂其他物质；当所述第二有源层403的组成材料包括所述非晶硅时，所述第二有源层403中靠近所述第二源极404、第二漏极405的区域可以掺杂一些掺杂物，关于所述掺杂物的组成材料可以参考所述第一有源层201的两端的掺杂物的组成材料的相关描述。
在一实施例中，所述第二源漏极层中的所述第二源极404、第二漏极405分别设于所述第二有源层403的两端，其中，所述第二源极404、第二漏极405两者之间的相对位置不做限定，图1中以所述第二源极404、第二漏极405分别设置在所述第二有源层403左侧、右侧为例，所述第二源极404、第二漏极405的组成材料可以参考所述第一源极206、第一漏极207的相关描述；具体的，所述第二源极404设于所述第二栅极绝缘层402上并从所述第二有源层403的左侧延伸至所述第二有源层403上方一预设位置，所述第二漏极405设于所述第二栅极绝缘层402上并从所述第二有源层403的右侧延伸至所述第二有源层403上方一预设位置。
在一实施例中，所述通孔包括第一通孔406，所述第一通孔406与所述第一源极206相对设置，或者所述第一通孔406与所述第一漏极207相对设置，图1中以所述第一通孔406与所述第一源极206相对设置为例；具体的，所述第一通孔406设置在所述第一绝缘层30、以及所述第二薄膜晶体管层40上，进一步的，如图1所示，所述第一通孔406与所述第一源极206接触设置，且所述第一通孔406贯穿部分所述第一绝缘层30、以及全部所述第二栅极绝缘层402；所述第一通孔406中设置有导电材料。
在一实施例中，所述第二源漏极层还包括第一金属部408，所述第一金属部408设于所述第二源极404远离所述第二栅极4011的一侧，或者所述第一金属部408设于所述第二漏极405远离所述第二栅极4011的一侧，图1中以所述第一金属部408设于所述第二源极404远离所述第二栅极4011的一侧为例；具体的，所述第一金属部408与所述第二源极404同排、且相隔一预设距离设置；可以理解的，所述第一通孔406中的导电材料可以与所述第一金属部408的组成材料相同，因此，所述第一通孔406中的导电材料可以与所述第一金属部408一体制作，例如，如图1所示，所述第一金属部408可以设于所述第一通孔406上方，进一步的，所述第一通孔406中的导电材料、以及所述第一金属部408可以同层、同时制备。
可以理解的，所述第二源漏极层可以通过所述第一通孔406与所述第一源漏极层电性连接；具体的，所述第二源漏极层中的所述第一金属部408可以通过所述第一通孔406与所述第一源漏极层中的所述第一源极206、或者所述第一漏极207电性连接。
在一实施例中，所述第二栅极层还包括金属层4012，所述金属层4012与所述第二栅极4011同层、且相隔一预设距离设置，所述金属层4012设于所述第二栅极4011的任意一侧，图1中以所述金属层4012设于所述第二栅极4011远离所述第一金属部408的一侧为例，其中所述金属层4012的组成材料可以为金属导电材料。
在一实施例中，所述通孔还包括第三通孔407，所述第三通孔407与所述金属层4012相对设置；具体的，所述第三通孔407设置在所述第二薄膜晶体管层40上，进一步的，如图1所示，所述第三通孔407与所述金属层4012接触设置，且所述第三通孔407贯穿部分所述第二栅极绝缘层402；所述第三通孔407中设置有导电材料。
在一实施例中，所述第二源漏极层还包括第二金属部409，所述第二金属部409设于所述第二源极404远离所述第二栅极4011的一侧，或者所述第二金属部409设于所述第二漏极405远离所述第二栅极4011的一侧，图1中以所述第一金属部408设于所述第二漏极405远离所述第二栅极4011的一侧为例；具体的，所述第一金属部408与所述第二漏极405同排、且相隔一预设距离设置；可以理解的，所述第三通孔407中的导电材料可以与所述第二金属部409的组成材料相同，因此，所述第三通孔407中的导电材料可以与所述第二金属部409一体制作，例如，如图1所示，所述第二金属部409可以设于所述第三通孔407上方，进一步的，所述第三通孔407中的导电材料、以及所述第二金属部409可以同层、同时制备。
可以理解的，所述第二源漏极层可以通过所述第三通孔407与所述第二栅极层电性连接；具体的，所述第二源漏极层中的所述第二金属部409可以通过所述第三通孔407与所述第二栅极层中的所述金属层4012电性连接。
可以理解的，所述第二源漏极层中的所述第二源极404、所述第二漏极405、所述第一金属部408、以及所述第二金属部409可以同层、同时制备。
在一实施例中，所述第二绝缘层50包括设于所述第二薄膜晶体管层40上的第一钝化层501、设于所述第一钝化层501上的平坦层502、设于所述平坦层502上的中间层503。
其中，所述第一钝化层501的组成材料可以包括有机绝缘材料、无机绝缘材料中的至少一种。具体的，所述有机绝缘材料可以包括聚酰亚胺、聚酰胺酸、聚酰胺、聚乙烯醇、聚乙烯醇肉桂酸酯、或者其他适合的光刻胶材料中的至少一种。所述无机绝缘材料可以包括氧化硅、氮化硅、氮氧化硅中的至少一种。进一步的，所述第一钝化层501可以采用氮化硅制备。
其中，所述平坦层502的组成材料可以参考所述第一钝化层501的组成材料的相关描述。进一步的，所述平坦层502可以采用光刻胶材料制备。
其中，所述中间层503的组成材料可以参考所述第一钝化层501的组成材料的相关描述。进一步的，所述中间层503可以采用氮化硅制备。
在一实施例中，所述器件层80包括传感器层60、金属部508、触控电极801、以及像素电极70。
需要注意的是，所述传感器层60具有光敏特性，并且具有单向导电性。无光照时，所述传感器层60有很小的饱和反向漏电流，即暗电流，此时所述传感器层60相当于截止；当受到光照时，所述传感器层60的饱和反向漏电流大大增加，形成光电流，光电流随入射光强度的变化而变化。
在一实施例中，所述通孔还包括第二通孔505，所述第二通孔505与所述第二源极404相对设置，或者所述第二通孔505与所述第二漏极405相对设置，图1中以所述第二通孔505与所述第二漏极405相对设置为例；具体的，所述第二通孔505设置在所述第一钝化层501、所述平坦层502、所述中间层503上，进一步的，如图1所示，所述第二通孔505与所述第二漏极405接触设置，且所述第二通孔505贯穿部分所述第一钝化层501、全部所述平坦层502、以及全部所述中间层503；所述第二通孔505中设置有导电材料。
在一实施例中，所述传感器层60包括第一电极601，所述第一电极601设于所述中间层503上，所述第一电极601具有一预设长度，其中，所述第一电极601的组成材料可以包括导体材料，具体的，所述导体材料可以包括金属、金属氧化物、导电高分子材料中的至少一种；特别的，所述第一电极601的组成材料也可以包括透明导电材料，具体的，所述透明导电材料可以包括铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物或铟锗锌氧化物等金属氧化物中的至少一种；可以理解的，所述第二通孔505中的导电材料可以与所述第一电极601的组成材料相同，因此，所述第二通孔505中的导电材料可以与所述第一电极601一体制作，例如，如图1所示，所述第一电极601可以设于所述第二通孔505上方，进一步的，所述第二通孔505中的导电材料、以及所述第一电极601可以同层、同时制备。
可以理解的，所述第一电极601可以通过所述第二通孔505与所述第二源漏极层电性连接；具体的，所述第一电极601可以通过所述第二通孔505与所述第二源漏极层中的所述第二漏极405电性连接。
在一实施例中，所述通孔还包括第四通孔506，所述第四通孔506与所述第二金属部409相对设置；具体的，所述第四通孔506设置在所述第一钝化层501、所述平坦层502、所述中间层503上，进一步的，如图1所示，所述第四通孔506与所述第二金属部409接触设置，且所述第四通孔506贯穿部分所述第一钝化层501、全部所述平坦层502、以及全部所述中间层503；所述第四通孔506中设置有导电材料。
在一实施例中，所述金属部508设于所述中间层503上，所述金属部508与所述第一电极601同排、且相隔一预设距离设置；可以理解的，其中，所述金属部508的组成材料可以为金属导电材料；可以理解的，所述第四通孔506中的导电材料可以与所述金属部508的组成材料相同，因此，所述第四通孔506中的导电材料可以与所述金属部508一体制作，例如，如图1所示，所述金属部508可以设于所述第四通孔506上方，进一步的，所述第四通孔506中的导电材料、以及所述金属部508可以同层、同时制备。
可以理解的，所述金属部508可以通过所述第四通孔506与所述第二源漏极层电性连接；具体的，所述金属部508可以通过所述第四通孔506与所述第二源漏极层中的所述第二金属部409电性连接。
在一实施例中，所述触控电极801设于所述中间层503上，所述触控电极801可以设于所述第一金属部408远离所述第二有源层403的一侧，所述触控电极801的组成材料可以为金属或者非金属的导电材料。
可以理解的，所述触控电极801、所述第一电极601、以及所述金属部508可以同层、同时制备。
在一实施例中，所述器件层80还包括绝缘层802，所述绝缘层802设于所述中间层503、所述第二金属层508、所述第一电极601、以及所述触控电极801上，所述绝缘层802用于绝缘导电材料，所述绝缘层802的组成材料可以参考所述第一钝化层501的组成材料的相关描述。
其中，所述绝缘层802上设置有公共电极通孔8031，所述公共电极通孔8031与所述触控电极801相互接触、且贯穿所述绝缘层802，所述公共电极通孔8031中设置有导电材料。
在一实施例中，所述器件层80还包括至少一条公共电极803，所述至少一条公共电极803之间可以相互电性连接，所述公共电极803设于所述绝缘层802上，所述公共电极803的组成材料可以为金属导电材料；可以理解的，所述公共电极通孔8031中的导电材料可以与一所述公共电极803的组成材料相同，因此，所述公共电极通孔8031中的导电材料可以与所述一公共电极803一体制作，例如，如图1所示，所述一公共电极803可以设于所述公共电极通孔8031上方，进一步的，所述公共电极通孔8031中的的导电材料、以及所述一公共电极803可以同层、同时制备。
在一实施例中，所述器件层80还包括第二钝化层804，所述第二钝化层804设于所述绝缘层802、所述公共电极803上，所述第二钝化层804的组成材料可以参考所述第一钝化层502的组成材料的相关描述。
在一实施例中，所述通孔还包括第五通孔504，所述第五通孔504与所述第一金属部408相对设置；具体的，所述第五通孔504设置在所述第二绝缘层50、以及所述器件层80上，进一步的，如图1所示，所述第五通孔504与所述第一金属部408接触设置，且所述第五通孔504贯穿部分所述第一钝化层501、全部所述平坦层502、全部所述中间层503、全部所述绝缘层802、以及全部所述第二钝化层804；所述第五通孔504中设置有导电材料。
在一实施例中，所述像素电极70设于所述第二钝化层804上，所述像素电极70可以与所述第一薄膜晶体管层20一一对应。如图2所示，一所述像素电极70可以包括多条像素电极部701，所述多条像素电极部701可以沿一预设方向相互平行、且相隔一预设距离设置，可以理解的，如图1中的所述像素电极70可以看作如图2中沿AB方向的截面图，其中所述多条像素电极部701之间是相互连通的，即任一所述像素电极部701的电性情况均相同。可以理解的，所述第五通孔504中的导电材料可以与所述像素电极70的组成材料相同，因此，所述第五通孔504中的导电材料可以与一所述像素电极部701一体制作，例如，如图1所示，所述一像素电极部701可以设于所述第五通孔504上方或者与所述第五通孔504两端接触设置，进一步的，所述第五通孔504中的导电材料、以及所述像素电极部701可以同层、同时制备。
可以理解的，所述像素电极70可以通过所述第五通孔504与所述第二源漏极层电性连接；具体的，所述像素电极70可以通过所述第五通孔504与第二源漏极层中的所述第一金属部408电性连接；结合上述，所述第二源漏极层中的所述第一金属部408可以通过所述第一通孔406与所述第一源漏极层中的所述第一源极206、或者所述第一漏极207电性连接；综合可知，所述像素电极70可以通过上述连接方式和所述第一源漏极层电性连接，其中，所述第一源漏极层可以控制所述对应的像素电极70的电压大小。
在一实施例中，所述器件层80还包括第三钝化层90，所述第三钝化层90设于所述像素电极70、以及所述第二钝化层804上，所述第三钝化层90的组成材料可以参考所述第一钝化层502的组成材料的相关描述。
在一实施例中，所述传感器层60还包括感光器件通孔604，所述感光器件通孔604与所述第一电极601相对设置；具体的，所述感光器件通孔604设置在所述器件层80上，进一步的，如图1所示，所述感光器件通孔604与所述第一电极601接触设置，且所述感光器件通孔604贯穿部分所述绝缘层802、全部所述第二钝化层804、以及全部所述第三钝化层90。
在一实施例中，所述传感器层60还包括感光器件层602，所述感光器件层602设置在所述感光器件通孔604中，具体的，如图1所示，所述感光器件层602填满所述感光器件通孔604，所述感光器件层602可以包括依次设于所述第一电极601上的电子传输层6021、感光层6022、空穴传输层6023。
具体的，所述感光层6022的组成材料可以包括硅氧化物、非晶硅中的至少一种，但本发明不以此为限，只要是照光后可产生光电流的材料皆可作为所述感光层6022的组成材料。
在一实施例中，所述通孔还包括第六通孔901，所述第六通孔901与所述第二金属层508相对设置；具体的，所述第六通孔901设置在所述器件层80上，进一步的，如图1所示，所述第六通孔901与所述第二金属层508接触设置，且所述第六通孔901贯穿部分所述绝缘层802、全部所述第二钝化层804、以及全部所述第三钝化层90；所述第六通孔901中设置有导电材料。
在一实施例中，所述传感器层60还包括第二电极603，所述第二电极603设于所述感光器件层602、以及所述第三钝化层90上，所述第二电极603可以与所述第一电极601一一对应；其中，所述第二电极603的组成材料可以包括透明导电材料，具体的，所述透明导电材料可以包括铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物或铟锗锌氧化物等金属氧化物中的至少一种。可以理解的，所述第六通孔901中的导电材料可以与所述第二电极603的组成材料相同，因此，所述第六通孔901中的导电材料可以与所述第二电极603一体制作，例如，如图1所示，所述第二电极603可以设于所述第六通孔901上方或者与所述第六通孔901两端接触设置，进一步的，所述第六通孔901中的导电材料、以及所述第二电极603可以同层、同时制备。
可以理解的，所述第二电极603通过所述第六通孔901与所述金属部508电性连接；结合上述，所述金属部508可以通过所述第四通孔506与所述第二源漏极层中的所述第二金属部409电性连接；综合可知，所述第二电极603可以通过上述连接方式和所述第二金属部409电性连接。
综上所述，所述第二电极603与所述第二金属部409电性连接，以及所述第一电极601与所述第二漏极405电性连接，即所述第二漏极405、所述金属层4012可以构成一存储电容。
具体的，曝光阶段，所述感光器件层602产生的光电流通过所述第一电极601、第二电极603向所述存储电容上下两侧充电，曝光结束，所述存储电容转移出自身所带电荷；进一步的，所述第二栅极4011中的开关信号可以控制曝光时间，曝光阶段，所述第二栅极4011中的开关信号使得所述第二薄膜晶体管层40关闭，曝光结束，所述存储电容转移出自身所带电荷，形成电流，并且所述第二栅极4011中的开关信号使得所述开关晶体管第二薄膜晶体管层40打开，所述第二源极403以读取所述感光器件层602产生的光电流对应的电信号，再经过后续的信号转化，以进行指纹识别。
可以理解的，所述图1示例为LCD显示面板的实施例，实际上本发明中的显示面板还可以为OLED或者其他显示面板，只要其中的所述第二薄膜晶体管层40与所述第一薄膜晶体管层20采用如上所述的层叠设置方式，均属于本发明的保护范围。
本发明还提供显示面板的制作方法，所述方法包括如图3所示的步骤，所述步骤S10-S90对应如图4-5所示的场景示意图。
参考图3以及图4，具体如下：
S10，提供一衬底10。
在一实施例中，所述衬底10包括基板101、设于所述基板101上的遮光层102、以及设于所述基板101和所述遮光层102上的缓冲层103。
在一实施例中，所述缓冲层103包括依次设于所述基板101和所述遮光层102上的第一缓冲层1031、第二缓冲层1032。
其中，所述基板101、所述遮光层102、所述第一缓冲层1031、以及所述第二缓冲层1032可以参考上述显示面板中的相关描述。
S20，在所述衬底10上形成第一薄膜晶体管层20，所述第一薄膜晶体管层20包括第一源漏极层。
在一实施例中，所述第一薄膜晶体管层20包括设于所述衬底10上的第一有源层201、设于所述第一有源层201以及所述衬底10上的第一栅极绝缘层202、设于所述第一栅极绝缘层202上的第一栅极层203、设于所述第一栅极层203以及所述第一栅极绝缘层202上的第一内部绝缘层204、设置在所述第一栅极绝缘层202、第一内部绝缘层204上的两个源漏极通孔205、以及设置在所述第一内部绝缘层204、所述两个源漏极通孔205上的第一源漏极层，所述第一源漏极层包括第一源极206、第一漏极207。
其中，所述第一有源层201、所述第一栅极绝缘层202、所述第一栅极层203、所述第一内部绝缘层204、所述两个源漏极通孔205、所述第一源极206、以及所述第一漏极207可以参考上述显示面板中的相关描述。
S30，在所述第一薄膜晶体管层20上形成第一绝缘层30。
在一实施例中，所述第一绝缘层30设于所述第一源极206、所述第一漏极207以及所述第一内部绝缘层204上，其中，所述第一绝缘层30的组成材料可以参考上述显示面板中的所述第一内部绝缘层204的组成材料的相关描述。
S40，在所述第一绝缘层30上形成第二薄膜晶体管层40，所述第二薄膜晶体管层40包括第二栅极层、第二源漏极层。
在一实施例中，所述第二薄膜晶体管层40包括设于所述第一绝缘层30上的第二栅极层、设于所述第二栅极层上的第二栅极绝缘层402、设于所述第二栅极绝缘层402上的第二有源层403。
需要注意的是，后续步骤S50中的所述第一通孔406设置在所述第一绝缘层30和所述第二薄膜晶体管层40中的第二栅极绝缘层402上，所述第三通孔407设置在所述第二薄膜晶体管层40中的第二栅极绝缘层402上，因此所述步骤S40应该理解为：在述第一绝缘层30上形成第二栅极层、以及在所述第二栅极层上形成第二有源层403。
因此，所述步骤S40可以包括如下步骤，对应如图6所示的场景示意图。
S401，在所述第一绝缘层30上形成第二栅极层，所述第二栅极层包括第二栅极4011、金属层4012。
其中，所述金属层4012与所述第二栅极4011同层、且相隔一预设距离设置，所述第二栅极4011、所述金属层4012可以参考上述显示面板中的相关描述。
S402，在所述第一绝缘层30以及所述第二栅极层上形成第二栅极绝缘层402。
其中，所述第二栅极绝缘层402可以参考上述显示面板中的相关描述。
S403，在所述第二栅极绝缘层402上形成第二有源层403。
其中，所述第二有源层403与所述第二栅极4011相对设置，所述第二有源层403可以参考上述显示面板中的相关描述。
S50，在所述第一绝缘层30和所述第二薄膜晶体管层40上形成第一通孔406，以及在所述第二薄膜晶体管层40上形成第三通孔407，并且在所述第一通孔406、所述第三通孔407内均设置导电材料，所述第一通孔406用于将所述第二源漏极层与所述第一源漏极层电性连接，所述第三通孔407用于将所述第二源漏极层与所述第二栅极层电性连接。
在一实施例中，所述第一通孔406与所述第一源极206相对设置，或者所述第一通孔406与所述第一漏极207相对设置，图4中以所述第一通孔406与所述第一源极206相对设置为例，所述第一通孔406可以参考上述显示面板中的相关描述。
在一实施例中，所述第三通孔407与所述金属层4012相对设置，所述第三通孔407可以参考上述显示面板中的相关描述。
可以理解的，所述第二薄膜晶体管层40还包括设于第二栅极绝缘层402、以及所述第二有源层403两端的第二源漏极层，所述第二源漏极层包括第二源极404、第二漏极405。即在所述步骤S50之后，所述步骤S40中还可以包括如下步骤：
S404，在所述第二有源层403、所述第二栅极绝缘层402上形成第二源漏极层，所述第二源漏极层包括第二源极404、第二漏极405、第一金属部408、以及第二金属部409，所述第二源极404、所述第二漏极405分别设于所述第二栅极4011的左/右、右/左两侧，所述第一金属部408设于所述第二源极404远离所述第二栅极4011的一侧，所述第二金属部409设于所述第二漏极405远离所述第二栅极4011的一侧，所述金属层4012与所述第二金属部409相对设置。
其中，所述第二源极404、所述第二漏极405、所述第一金属部408、以及所述第二金属部409可以参考上述显示面板中的相关描述。
S60，在所述第二薄膜晶体管层40上形成第二绝缘层50。
在一实施例中，所述第二绝缘层50包括设于所述第二薄膜晶体管层40上的第一钝化层501、设于所述第一钝化层501上的平坦层502、设于所述平坦层502上的中间层503。
其中，所述第一钝化层501、所述平坦层502、以及所述中间层503可以参考上述显示面板中的相关描述。
参考图3以及图5，具体如下：
S70，在所述第二绝缘层50上形成第五通孔504、第二通孔505、以及第四通孔506，并且在所述第五通孔504、所述第二通孔505、以及所述第四通孔506内均设置导电材料。
在一实施例中，所述第五通孔504与所述第一金属部408相对设置，所述第二通孔505与所述第二源极404相对设置，所述第四通孔506与所述第二金属部409相对设置。
其中，所述第五通孔504、所述第二通孔505、以及所述第四通孔506可以参考上述显示面板中的相关描述。
S80，在所述第二绝缘层50上形成器件层80，所述器件层80包括像素电极70、传感器层60、以及金属部508，所述传感器层60包括第一电极601、第二电极603，所述第五通孔504用于将所述像素电极70与所述第二源漏极层电性连接，所述第二通孔505用于将所述第一电极601与所述第二源漏极层电性连接，所述第四通孔506用于将所述金属部508与所述第二源漏极层电性连接。
其中，所述步骤S80可以包括如下步骤，对应如图7所示的场景示意图。
S801，在所述第二绝缘层50上形成所述第一电极601。
在一实施例中，所述第一电极601设于所述中间层503上，所述第一电极601可以参考上述显示面板中的相关描述。
在一实施例中，所述金属部508设于所述中间层503上，所述金属部508与所述第一电极601同排、且相隔一预设距离设置，所述金属部508可以参考上述显示面板中的相关描述。
在一实施例中，所述器件层80还包括触控电极801，所述触控电极801设于所述中间层503上，所述触控电极801可以设于所述第一金属部408远离所述第二有源层403的一侧，所述触控电极801可以参考上述显示面板中的相关描述。
可以理解的，所述第一电极601、所述金属部508、所述触控电极801可以同时、且同层制备。
S802，在所述第二绝缘层50、所述第一电极601上形成绝缘层802。
在一实施例中，所述绝缘层802设于所述中间层503、所述第二金属层508、所述第一电极601、以及所述触控电极801上，所述绝缘层802可以参考上述显示面板中的相关描述。
在一实施例中，所述绝缘层802上设置有公共电极通孔8031，所述公共电极803可以参考上述显示面板中的相关描述。
在一实施例中，所述绝缘层802上与所述金属部508相对的位置上设置有第一子通孔9011，所述第一子通孔9011与所述金属部508接触设置、且贯穿所述绝缘层802。
在一实施例中，所述绝缘层802上与所述第一电极601相对的位置上设置有第一感光器件通孔6041，所述第一感光器件通孔6041与所述第一电极601接触设置、且贯穿所述绝缘层802。
S803，在所述绝缘层802上形成所述像素电极70、所述第二电极603。
具体的，所述步骤S803可以包括如下步骤，对应如图8-9所示的场景示意图。
请参考如图8所示的场景示意图，具体如下：
S8031，在所述绝缘层802上形成公共电极803。
其中，所述公共电极803可以通过所述公共电极通孔8031与所述触控电极801电性连接，所述公共电极803可以参考上述显示面板中的相关描述。
S8032，在所述绝缘层802、所述公共电极803上形成第二钝化层804。
在一实施例中，所述第二钝化层804设于所述绝缘层802、所述公共电极803上，所述第二钝化层804可以参考上述显示面板中的相关描述。
在一实施例中，所述第二钝化层804上与所述第一感光器件通孔6041相对位置设置有第二感光器件通孔6042，所述第二感光器件通孔6042与所述第一感光器件通孔6041接触设置、且贯穿所述第二钝化层804。
在一实施例中，所述第二钝化层804上与所述第一子通孔9011相对位置设置有第二子通孔9012，所述第二子通孔9012与所述第一子通孔9011接触设置、且贯穿所述第二钝化层804。
在一实施例中，所述第五通孔504除了，还设置在所述器件层80中的所述绝缘层802、以及所述第二钝化层804上，所述第五通孔504可以参考上述显示面板中的相关描述。
请参考如图9所示的场景示意图，具体如下：
S8033，在所述第二钝化层804上形成所述像素电极70。
在一实施例中，所述像素电极70可以与所述第一薄膜晶体管层20一一对应，一所述像素电极70可以包括多条像素电极部701，所述像素电极70、以及所述像素电极部701可以参考上述显示面板中的相关描述。
需要注意的是，后续步骤S90中的形成所述第六通孔901的步骤是在制备所述第二电极603之前进行的，因此所述S8033步骤之后可以进行所述步骤S90。
S90，在所述器件层80上形成第六通孔901，并且在所述第六通孔901内设置导电材料，所述第六通孔901将所述第二电极603与所述金属部508电性连接。
具体的，在所述第二钝化层804、所述像素电极70上形成第三钝化层90，以及对所述第三钝化层90进行图案化处理，形成所述第六通孔901，并且在所述第六通孔901内设置导电材料。
在一实施例中，所述第三钝化层90设于所述像素电极70、以及所述第二钝化层804上，所述第三钝化层90可以参考上述显示面板中的相关描述。
具体的，所述第三钝化层90上与所述第二感光器件通孔6042相对位置设置有第三感光器件通孔6043，所述第三感光器件通孔6043与所述第二感光器件通孔6042接触设置、且贯穿所述第三钝化层90，所述第一感光器件通孔6041、所述第二感光器件通孔6042、所述第三感光器件通孔6043共同构成感光器件通孔604。
其中，所述感光器件通孔604与所述第一电极601相对设置，所述感光器件通孔604可以参考上述显示面板中的相关描述。
具体的，所述第三钝化层90上与所述第二子通孔9012相对位置设置有第三子通孔9013，所述第三子通孔9013与所述第二子通孔9012接触设置、且贯穿所述第三钝化层90，所述第一子通孔9011、所述第二子通孔9012、所述第三子通孔9013共同构成所述第六通孔901。
其中，所述第六通孔901与所述第二金属层508相对设置，所述第六通孔901可以参考上述显示面板中的相关描述。
可以理解的，所述传感器层60还包括设于所述第一电极601上的感光器件层602、以及设于所述感光器件层602上的所述第二电极603。即在所述步骤S50之后，所述步骤S803中还可以包括如下步骤：
S8034，在所述感光器件通孔604中形成所述感光器件层602，以及在所述感光器件层602、所述第三钝化层90上、所述第六通孔901中形成所述第二电极603。
在一实施例中，所述感光器件层602可以包括依次设于所述第一电极601上的电子传输层6021、感光层6022、空穴传输层6023，所述感光器件层602可以参考上述显示面板中的相关描述。
在一实施例中，所述第二电极603可以与所述第一电极601一一对应，所述第二电极603可以参考上述显示面板中的相关描述。
本发明提供了显示面板、显示装置、以及显示面板的制作方法，所述显示面板包括衬底、第一薄膜晶体管层、第一绝缘层、第二薄膜晶体管层、第二绝缘层、器件层、以及多个通孔，所述第二薄膜晶体管层设置在所述第一薄膜晶体管层上，且所述多个通孔将相关的膜层之间进行电性连接，本发明增加了光学传感器接收到的光线，提高了显示面板内部的光学指纹识别的精度。
本发明的有益效果为：本发明提供了显示面板、显示装置、以及显示面板的制作方法，所述显示面板包括衬底、第一薄膜晶体管层、第一绝缘层、第二薄膜晶体管层、第二绝缘层、器件层、以及多个通孔，所述第二薄膜晶体管层设置在所述第一薄膜晶体管层上，且所述多个通孔将相关的膜层之间进行电性连接，本发明增加了光学传感器接收到的光线，提高了显示面板内部的光学指纹识别的精度。
以上对本发明实施例所提供的显示面板和显示装置的结构、以及显示面板的制作方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。

Claims (15)

  1. 一种显示面板，其中，所述显示面板包括：衬底、第一薄膜晶体管层、第一绝缘层、第二薄膜晶体管层、第二绝缘层、器件层、以及多个通孔；
    所述第一薄膜晶体管层，设置在所述衬底上，所述第一薄膜晶体管层包括第一源漏极层；
    所述第一绝缘层，设置在所述第一薄膜晶体管层上；
    所述第二薄膜晶体管层，设置在所述第一绝缘层上，所述第二薄膜晶体管层包括第二栅极层、第二源漏极层；
    所述第二绝缘层，设置在所述第二薄膜晶体管层上；
    所述器件层，设置在所述第二绝缘层上，所述器件层包括像素电极、传感器层、以及金属部，所述传感器层包括第一电极、第二电极；
    所述多个通孔包括第一通孔、第二通孔、第三通孔、第四通孔、第五通孔、以及第六通孔，所述第一通孔、所述第二通孔、所述第三通孔、所述第四通孔、所述第五通孔、以及所述第六通孔内均设置有导电材料；
    所述第一通孔设置在所述第一绝缘层、以及所述第二薄膜晶体管层上，所述第五通孔设置在所述第二绝缘层、以及所述器件层上，所述像素电极通过所述第五通孔与所述第二源漏极层电性连接，所述第二源漏极层通过所述第
    一通孔与所述第一源漏极层电性连接，使得所述像素电极和所述第一源漏极层电性连接；
    所述第二通孔设置在所述第二绝缘层上，所述第一电极通过所述第二通孔与所述第二源漏极层电性连接；
    所述第三通孔设置在所述第二薄膜晶体管层上，所述第四通孔设置在所述第二绝缘层上，所述第六通孔设置在所述器件层上，所述第二电极通过所述第六通孔与所述金属部电性连接，所述金属部通过所述第四通孔与所述第二源漏极层电性连接，所述第二源漏极层通过所述第三通孔与所述第二栅极层电性连接，使得所述第二电极和所述第二栅极层电性连接。
  2. 如权利要求1所述的显示面板，其中，所述第二栅极层包括第二栅极，所述第二源漏极层包括第二源极、第二漏极，所述第二源极、所述第二漏极分别设于所述第二栅极的左/右、右/左两侧；
    所述源漏极层还包括第一金属部、第二金属部，所述第一金属部设于所述第二源极远离所述第二栅极的一侧，所述第二金属部设于所述第二漏极远离所述第二栅极的一侧；
    所述像素电极通过所述第五通孔与所述第一金属部电性连接，所述第一金属部通过所述第一通孔与所述第一
    源漏极层电性连接，使得所述像素电极和所述第一源漏极层电性连接。
  3. 如权利要求2所述的显示面板，其中，所述第一电极通过所述第二通孔与所述第二漏极电性连接。
  4. 如权利要求2所述的显示面板，其中，所述第二栅极层还包括金属层，所述金属层与所述第二金属部相对设置；
    所述第二电极依次通过所述第六通孔、所述第四通孔与所述第二金属部电性连接，所述第二金属部通过所述第三通孔与所述金属层电性连接，使得所述第二电极和所述金属层电性连接。
  5. 如权利要求1所述的显示面板，其中，所述第二薄膜晶体管层还包括第二有源层，所述第二有源层设于所述第二栅极层上方，所述第二有源层的组成材料包括非晶硅或者铟镓锌氧化物中的一种。
  6. 如权利要求1所述的显示面板，其中，所述第一薄膜晶体管层还包括第一有源层，所述第一有源层设于所述第一源漏极层下方，所述第一有源层的组成材料包括多晶硅。
  7. 一种显示装置，其中，所述显示装置包括显示面板，所述显示面板包括：衬底、第一薄膜晶体管层、第一绝缘层、第二薄膜晶体管层、第二绝缘层、器件层、以及多个通孔；
    所述第一薄膜晶体管层，设置在所述衬底上，所述第
    一薄膜晶体管层包括第一源漏极层；
    所述第一绝缘层，设置在所述第一薄膜晶体管层上；
    所述第二薄膜晶体管层，设置在所述第一绝缘层上，所述第二薄膜晶体管层包括第二栅极层、第二源漏极层；
    所述第二绝缘层，设置在所述第二薄膜晶体管层上；
    所述器件层，设置在所述第二绝缘层上，所述器件层包括像素电极、传感器层、以及金属部，所述传感器层包括第一电极、第二电极；
    所述多个通孔包括第一通孔、第二通孔、第三通孔、第四通孔、第五通孔、以及第六通孔，所述第一通孔、所述第二通孔、所述第三通孔、所述第四通孔、所述第五通孔、以及所述第六通孔内均设置有导电材料；
    所述第一通孔设置在所述第一绝缘层、以及所述第二薄膜晶体管层上，所述第五通孔设置在所述第二绝缘层、以及所述器件层上，所述像素电极通过所述第五通孔与所述第二源漏极层电性连接，所述第二源漏极层通过所述第一通孔与所述第一源漏极层电性连接，使得所述像素电极和所述第一源漏极层电性连接；
    所述第二通孔设置在所述第二绝缘层上，所述第一电
    极通过所述第二通孔与所述第二源漏极层电性连接；
    所述第三通孔设置在所述第二薄膜晶体管层上，所述第四通孔设置在所述第二绝缘层上，所述第六通孔设置在所述器件层上，所述第二电极通过所述第六通孔与所述金属部电性连接，所述金属部通过所述第四通孔与所述第二源漏极层电性连接，所述第二源漏极层通过所述第三通孔与所述第二栅极层电性连接，使得所述第二电极和所述第二栅极层电性连接。
  8. 如权利要求7所述的显示装置，其中，所述第二栅极层包括第二栅极，所述第二源漏极层包括第二源极、第二漏极，所述第二源极、所述第二漏极分别设于所述第二栅极的左/右、右/左两侧；
    所述源漏极层还包括第一金属部、第二金属部，所述第一金属部设于所述第二源极远离所述第二栅极的一侧，所述第二金属部设于所述第二漏极远离所述第二栅极的一侧；
    所述像素电极通过所述第五通孔与所述第一金属部电性连接，所述第一金属部通过所述第一通孔与所述第一源漏极层电性连接，使得所述像素电极和所述第一源漏极层电性连接。
  9. 如权利要求8所述的显示装置，其中，所述第一电极通过所述第二通孔与所述第二漏极电性连接。
  10. 如权利要求8所述的显示装置，其中，所述第二栅极层还包括金属层，所述金属层与所述第二金属部相对设置；
    所述第二电极依次通过所述第六通孔、所述第四通孔与所述第二金属部电性连接，所述第二金属部通过所述第三通孔与所述金属层电性连接，使得所述第二电极和所述金属层电性连接。
  11. 如权利要求7所述的显示装置，其中，所述第二薄膜晶体管层还包括第二有源层，所述第二有源层设于所述第二栅极层上方，所述第二有源层的组成材料包括非晶硅或者铟镓锌氧化物中的一种。
  12. 如权利要求7所述的显示装置，其中，所述第一薄膜晶体管层还包括第一有源层，所述第一有源层设于所述第一源漏极层下方，所述第一有源层的组成材料包括多晶硅。
  13. 一种显示面板的制作方法，其中，所述方法包括：
    提供一衬底；
    在所述衬底上形成第一薄膜晶体管层，所述第一薄膜晶体管层包括第一源漏极层；
    在所述第一薄膜晶体管层上形成第一绝缘层；
    在所述第一绝缘层上形成第二薄膜晶体管层，所述第二薄膜晶体管层包括第二栅极层、第二源漏极层；
    在所述第一绝缘层和所述第二薄膜晶体管层上形成第一通孔，以及在所述第二薄膜晶体管层上形成第三通孔，并且在所述第一通孔、所述第三通孔内均设置导电材料，所述第一通孔用于将所述第二源漏极层与所述第一源漏极层电性连接，所述第三通孔用于将所述第二源漏极层与所述第二栅极层电性连接；
    在所述第二薄膜晶体管层上形成第二绝缘层；
    在所述第二绝缘层上形成第五通孔、第二通孔、以及第四通孔，并且在所述第五通孔、所述第二通孔、以及所述第四通孔内均设置导电材料；
    在所述第二绝缘层上形成器件层，所述器件层包括像素电极、传感器层、以及金属部，所述传感器层包括第一电极、第二电极，所述第五通孔用于将所述像素电极与所述第二源漏极层电性连接，所述第二通孔用于将所述第一电极与所述第二源漏极层电性连接，所述第四通孔用于将所述金属部与所述第二源漏极层电性连接；
    在所述器件层上形成第六通孔，并且在所述第六通孔内设置导电材料，所述第六通孔将所述第二电极与所述金属部电性连接。
  14. 如权利要求13所述的显示面板的制作方法，其中，所述在所述第一绝缘层上形成第二薄膜晶体管层，所述
    第二薄膜晶体管层包括第二栅极层、第二源漏极层的步骤
    包括：
    在所述第一绝缘层上形成第二栅极层，所述第二栅极层包括第二栅极、金属层；
    在所述第一绝缘层以及所述第二栅极层上形成第二栅极绝缘层；
    在所述第二栅极绝缘层上形成第二有源层；
    在所述第二有源层、所述第二栅极绝缘层上形成第二源漏极层，所述第二源漏极层包括第二源极、第二漏极、第一金属部、以及第二金属部，所述第二源极、所述第二漏极分别设于所述第二栅极的左/右、右/左两侧，所述第一金属部设于所述第二源极远离所述第二栅极的一侧，所述第二金属部设于所述第二漏极远离所述第二栅极的一侧，所述金属层与所述第二金属部相对设置。
  15. 如权利要求14所述的显示面板的制作方法，其中，所述在所述第二绝缘层上形成器件层，所述器件层包括像素电极和传感器层，所述传感器层包括第一电极、第二电极的步骤包括：
    在所述第二绝缘层上形成所述第一电极；
    在所述第二绝缘层、所述第一电极上形成绝缘层；
    在所述绝缘层上形成所述像素电极、所述第二电极。
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