WO2022165913A1 - 阵列基板和显示面板 - Google Patents

阵列基板和显示面板 Download PDF

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Publication number
WO2022165913A1
WO2022165913A1 PCT/CN2021/080129 CN2021080129W WO2022165913A1 WO 2022165913 A1 WO2022165913 A1 WO 2022165913A1 CN 2021080129 W CN2021080129 W CN 2021080129W WO 2022165913 A1 WO2022165913 A1 WO 2022165913A1
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WIPO (PCT)
Prior art keywords
semiconductor
layer
electrode
via hole
base substrate
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PCT/CN2021/080129
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English (en)
French (fr)
Inventor
汤富雄
龚帆
艾飞
宋继越
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武汉华星光电技术有限公司
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Priority to US17/281,268 priority Critical patent/US20230154949A1/en
Publication of WO2022165913A1 publication Critical patent/WO2022165913A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14607—Geometry of the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/042—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14678—Contact-type imagers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • Optical fingerprint recognition technology uses the principle of refraction and reflection of light. When the light is irradiated on the finger, it is received by the photosensitive sensor after being reflected by the finger. The photosensitive sensor can convert the light signal into an electrical signal for reading.
  • the effective photosensitive area of the photosensitive element in the existing photosensitive sensor is small, resulting in lower sensitivity of the photosensitive element.
  • the present application provides an array substrate and a display panel to solve the technical problem in the prior art that the effective photosensitive area of the photosensitive element is small, resulting in low sensitivity of the photosensitive element.
  • the present application provides an array substrate, which includes:
  • the switching element comprising a first semiconductor provided on the base substrate
  • the photosensitive element which is arranged on the base substrate adjacent to the switching element, the photosensitive element includes a second semiconductor and a photosensitive electrode, the second semiconductor is connected to the first semiconductor and is arranged in the same layer, the The photosensitive electrode is arranged on the side of the second semiconductor away from the base substrate, and is connected to the second semiconductor;
  • the photosensitive electrode and the second semiconductor form a Schottky junction.
  • the second semiconductor is an intrinsic type semiconductor or an N type semiconductor.
  • the first semiconductor includes a first doping part, a second doping part, a channel part, a third doping part and a fourth doped part, the fourth doped part is connected to the second semiconductor;
  • the first doping part and the fourth doping part are all N-type heavily doped, and the second doping part, the third doping part and the second semiconductor are all N-type Lightly doped.
  • the switching element further includes:
  • a gate disposed on a side of the first semiconductor away from the base substrate and insulated from the first semiconductor
  • the input electrode is disposed on a side of the first semiconductor away from the base substrate, and is connected to an end of the first semiconductor away from the second semiconductor.
  • the array substrate further includes a thin film transistor layer, and both the switching element and the photosensitive element are arranged in the thin film transistor layer.
  • the thin film transistor layer includes:
  • the semiconductor layer including the first semiconductor and the second semiconductor
  • a gate insulating layer disposed on the semiconductor layer
  • a gate layer disposed on the gate insulating layer, the gate layer including the gate
  • the interlayer insulating layer disposed on the gate insulating layer and the gate layer, the interlayer insulating layer has a first via hole, and the first via hole penetrates the interlayer insulating layer and extends to the a side of the first semiconductor away from the base substrate;
  • a source-drain electrode layer disposed on the interlayer insulating layer, the source-drain electrode layer includes the input electrode, the input electrode is connected to the first semiconductor layer through a first via hole, the first via hole A hole penetrates the interlayer insulating layer and the gate insulating layer.
  • the thin film transistor layer further includes: a flat layer disposed on the source-drain electrode layer and the interlayer insulating layer, the flat layer has a second via hole, the first Two via holes penetrate through the flat layer and expose a side of the interlayer insulating layer away from the base substrate;
  • a common electrode layer disposed on the flat layer
  • the passivation layer disposed on the common electrode layer and the flat layer, the passivation layer has a third via hole, the third via hole penetrates the passivation layer and passes through the second via hole extending to the side of the second semiconductor away from the base substrate, the diameter of the second via hole is larger than that of the third via hole, and the passivation layer covers the inner side of the second via hole wall;
  • the photosensitive electrode is connected to the second semiconductor through the third via hole.
  • the array substrate further includes a pixel electrode layer, and the pixel electrode layer is disposed on the passivation layer;
  • the photosensitive electrode and the pixel electrode layer are arranged in the same layer.
  • the source-drain electrode layer includes a source electrode, a drain electrode, a touch electrode and a fingerprint signal electrode
  • the common electrode layer includes a touch trace and a first electrode
  • the pixel electrode layer It includes a pixel electrode, a second electrode and a signal connection line.
  • the flat layer further has a fourth via hole, a fifth via hole and a sixth via hole, and the fourth via hole exposes the fingerprint signal electrode away from the base substrate.
  • the fifth via hole exposes a side of the drain electrode away from the base substrate
  • the sixth via hole exposes a side of the touch electrode away from the base substrate;
  • the passivation layer further has a seventh via hole and an eighth via hole, the seventh via hole is arranged corresponding to the fourth via hole, and the passivation layer covers the inner sidewall of the fourth via hole, The eighth via hole is disposed corresponding to the fifth via hole, and the passivation layer covers the inner sidewall of the fifth via hole; wherein, the photosensitive electrode communicates with the second via hole through the third via hole Semiconductor connection.
  • the array substrate further includes a pixel electrode layer, the pixel electrode layer is disposed on the passivation layer, and the pixel electrode layer includes a pixel electrode, a second electrode and a signal connection line;
  • the photosensitive electrode and the pixel electrode layer are arranged in the same layer.
  • the photosensitive electrode is connected to the signal connection line, and the signal connection line is connected to the fingerprint signal electrode through the seventh via hole; the pixel electrode is connected to the fingerprint signal electrode through the eighth via hole.
  • the via hole is connected with the drain electrode; the touch electrode is connected with the touch wire through the sixth via hole.
  • the array substrate has a display area and a dummy pixel area, the dummy pixel area is located at least on one side of the display area, and both the switch element and the photosensitive element are located in the dummy pixel area. pixel area.
  • the array substrate further includes a light shielding portion, the light shielding portion is disposed on the side of the base substrate close to the first semiconductor, and the light shielding portion is located on the base substrate.
  • the projection on at least covers the projection of the first semiconductor on the base substrate.
  • the projection of the light shielding portion on the base substrate covers the projection of the first semiconductor on the base substrate and the projection of the second semiconductor on the base substrate projection.
  • the material of the photosensitive electrode is indium zinc oxide, zinc oxide or indium gallium zinc oxide.
  • the materials of the first semiconductor and the second semiconductor are both polysilicon.
  • the thickness of the second semiconductor is 400 angstroms to 600 angstroms.
  • the present application also provides a display panel, which includes an array substrate, and the array substrate includes:
  • the switching element comprising a first semiconductor provided on the base substrate
  • the photosensitive element which is arranged on the base substrate adjacent to the switching element, the photosensitive element includes a second semiconductor and a photosensitive electrode, the second semiconductor is connected to the first semiconductor and is arranged in the same layer, the The photosensitive electrode is arranged on the side of the second semiconductor away from the base substrate, and is connected to the second semiconductor;
  • the photosensitive electrode and the second semiconductor form a Schottky junction.
  • the second semiconductor is an intrinsic type semiconductor or an N type semiconductor.
  • the material of the photosensitive electrode is indium zinc oxide, zinc oxide or indium gallium zinc oxide.
  • the present application provides an array substrate and a display panel.
  • the array substrate includes a switch element and a photosensitive element that are adjacently disposed on a base substrate, and the photosensitive element includes a second semiconductor and a photosensitive electrode connected to the second semiconductor.
  • the photosensitive electrode is disposed on the side of the second semiconductor away from the base substrate, and is connected to the second semiconductor.
  • the photosensitive electrode and the second semiconductor form a Schottky junction, which increases the effective photosensitive area of the photosensitive element, and the photosensitive element can form a built-in electric field in the vertical direction after receiving light, which can more effectively separate electron-hole pairs. Increase the photo-generated current, thereby improving the sensitivity of the photosensitive element.
  • FIG. 1 is a schematic diagram of a first structure of an array substrate provided by the present application.
  • FIG. 2 is a second structural schematic diagram of the array substrate provided by the present application.
  • FIG. 3 is a third structural schematic diagram of the array substrate provided by the present application.
  • FIG. 4 is a fourth schematic structural diagram of the array substrate provided by the present application.
  • FIG. 5 is a first schematic flow chart of the manufacturing method of the array substrate provided by the present application.
  • FIG. 6 is a second schematic flowchart of the manufacturing method of the array substrate provided by the present application.
  • FIG. 7 is a schematic structural diagram of a display panel provided by the present application.
  • the array substrate 100 includes a base substrate 10 , a switching element 20 and a photosensitive element 30 .
  • the switching element 20 is provided on the base substrate 10 .
  • the switching element 20 includes a first semiconductor 21 .
  • the first semiconductor 21 is provided on the base substrate 10 .
  • the photosensitive element 30 is provided on the base substrate 10 adjacent to the switching element 20 .
  • the photosensitive element 30 includes a second semiconductor 31 and a photosensitive electrode 32 .
  • the second semiconductor 31 is connected to the first semiconductor 21 and disposed in the same layer.
  • the photosensitive electrode 32 is disposed on the side of the second semiconductor 31 away from the base substrate 10 and is connected to the second semiconductor 31 .
  • the photosensitive electrode 32 and the second semiconductor 31 form a Schottky junction.
  • the switch element 20 and the photosensitive element 30 work together to realize functions such as under-screen optical fingerprint recognition.
  • the photosensitive element 30 includes a second semiconductor 31 and a photosensitive electrode 32 arranged in layers, so as to form a Schottky junction between the second semiconductor 31 and the photosensitive electrode 32, thereby increasing the effective photosensitive area of the photosensitive element 30; After the element 30 receives light, a built-in electric field can be formed in the vertical direction Y, which can more effectively separate electron-hole pairs and increase the photo-generated current, thereby improving the sensitivity of the photosensitive element 30; In the photosensitive element 30 provided in the embodiment of the present application, no additional photosensitive layer is required, thereby reducing the number of masks and reducing the production cost.
  • the Schottky junction is a simple metal-semiconductor interface, which is similar to the PN junction and has nonlinear impedance characteristics.
  • W.H. Schottky of Germany put forward a theoretical model and made a scientific explanation of this characteristic, so the interface between this metal and semiconductor was later called Schottky junction or Schottky barrier.
  • the base substrate 10 may be a glass substrate, a quartz substrate, a resin substrate, a PI (polyimide, Polyimide) flexible substrate, or other types of substrates, which will not be described in detail here.
  • PI polyimide, Polyimide
  • the switch element 20 is used to provide the bias voltage required for the operation of the photosensitive element 30 .
  • the switching element 20 is a thin film transistor, which may be a bottom gate type or a top gate type. The following embodiments of the present application are described by taking the switching element 20 as a top-gate thin film transistor as an example, but it is not limited thereto.
  • the switching element 20 further includes a gate electrode 22 and an input electrode 23 .
  • the gate electrode 22 is disposed on the side of the first semiconductor 21 away from the base substrate 10 .
  • the gate electrode 22 is insulated from the first semiconductor 21 .
  • the input electrode 23 is disposed on a side of the first semiconductor 21 away from the base substrate 10 and is connected to an end of the first semiconductor 21 away from the second semiconductor 31 .
  • the input electrode 23 is used to connect a bias voltage.
  • the switching element 20 transmits the bias voltage to the photosensitive element 30, so that the photosensitive element 30 is reversely biased. Then the switch element 20 is turned off, and when the incident light enters the photosensitive element 30, the photosensitive element 30 can be excited to generate photo-generated charges, thereby forming a photocurrent signal required for under-screen optical fingerprint recognition.
  • the material of the first semiconductor 21 is polysilicon.
  • the material of the gate electrode 22 and the input electrode 23 may be a single layer of metal with good conductivity or a stack of different metals.
  • the material of the gate electrode 22 is silver, aluminum, copper, molybdenum, molybdenum/aluminum/molybdenum (stack) or molybdenum/copper (stack).
  • the first semiconductor 21 includes a first doping portion 211 , a second doping portion 212 , a channel portion 213 , and a third doping portion 214 that are sequentially disposed on the base substrate 10 along the horizontal direction X and the fourth doped portion 215 .
  • the fourth doped portion 215 is connected to the second semiconductor 31 .
  • the first doping portion 211 , the second doping portion 212 , the channel portion 213 , the third doping portion 214 , and the fourth doping portion 215 are sequentially connected along the horizontal direction X.
  • the gate 22 is provided corresponding to the channel portion 213 .
  • the input electrode 23 is connected to the first doping part 211 .
  • the first doping portion 211 and the fourth doping portion 215 are both heavily N-type doped. Both the second doping part 212 and the third doping part 214 are N-type lightly doped.
  • the channel portion 213 is an intrinsic semiconductor.
  • the first doping part 211 , the second doping part 212 , the third doping part 214 and the fourth doping part 215 are obtained by doping the first semiconductor 21 with phosphorus ions.
  • the difference between N-type heavy doping and N-type light doping lies in the doping concentration of phosphorus ions.
  • the materials of the first semiconductor 21 and the second semiconductor 31 are both polysilicon. It is understandable that in traditional LTPS (Low In the temperature poly-silicon (low temperature poly-silicon, low-temperature poly-silicon) process, the thickness of the first semiconductor 21 and the second semiconductor 31 is relatively thin due to the limitation of the crystallization thickness of the poly-silicon by the excimer laser annealing process. If the built-in electric field exists only in the horizontal direction X, the photoelectric response of the photosensitive element 30 to incident light will be relatively low, and there will be fewer photogenerated electron-hole pairs, thereby affecting the sensitivity of the photosensitive element 30 .
  • LTPS Low In the temperature poly-silicon
  • the thickness of the first semiconductor 21 and the second semiconductor 31 is relatively thin due to the limitation of the crystallization thickness of the poly-silicon by the excimer laser annealing process. If the built-in electric field exists only in the horizontal direction X, the photoelectric response of the photosensitive element 30 to incident light will be relatively low,
  • the thickness of the second semiconductor 31 can be made thin.
  • the thickness of the second semiconductor 31 is 400 angstroms to 600 angstroms.
  • the thickness of the second semiconductor 31 is 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms or 600 angstroms.
  • the thickness of the first semiconductor 21 may be equal to the thickness of the second semiconductor 31 .
  • the thickness of the first semiconductor 21 is 400 angstroms to 600 angstroms.
  • the thickness of the first semiconductor 21 is 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms or 600 angstroms.
  • the first semiconductor 21 and the second semiconductor 31 may be formed through the same process.
  • the second semiconductor 31 is an N-type semiconductor.
  • the second semiconductor 31 , the second doping portion 212 and the third doping portion 214 are all N-type lightly doped. It can be understood that, in the conventional LTPS process, when ion implantation is performed on the first semiconductor 21 to form the second doping portion 212 and the third doping portion 214 , a full-surface ion implantation process is used. Therefore, by arranging the second semiconductor 31 and the first semiconductor 21 in the same layer in this embodiment of the present application, when the second doping part 212 and the third doping part 214 are formed, the N-type lightly doped second semiconductor can be simultaneously formed 31, thereby enhancing the strength of the built-in electric field and reducing the process process.
  • the material of the photosensitive electrode 32 is a conductive material with a high work function, so that a Schottky junction is formed between the photosensitive electrode 32 and the second semiconductor 31 .
  • the conductive material with high work function may be indium zinc oxide, zinc oxide or indium gallium zinc oxide.
  • the array substrate 100 further includes a buffer layer 12 , a gate insulating layer 13 , an interlayer insulating layer 14 , a planarization layer 18 and a passivation layer 41 .
  • the buffer layer 12 is disposed on the side of the base substrate 10 close to the first semiconductor 21 and covers the base substrate 10 .
  • the gate insulating layer 13 is disposed on the side of the gate 22 close to the base substrate 10 and covers the first semiconductor 21 , the second semiconductor 31 and the buffer layer 12 .
  • the interlayer insulating layer 14 is disposed on the side of the gate electrode 22 away from the base substrate 10 and covers the gate electrode 22 and the gate insulating layer 13 .
  • the interlayer insulating layer 14 has a first via hole 14A.
  • the first via hole 14A penetrates through the interlayer insulating layer 14 and extends to the side of the first semiconductor 21 away from the base substrate 10 .
  • the flat layer 18 is disposed on the side of the interlayer insulating layer 14 away from the base substrate 10 and covers the input electrode 23 .
  • the flat layer 18 has the second via hole 18A.
  • the second via hole 18A penetrates through the planarization layer 18 and exposes the side of the interlayer insulating layer 14 away from the base substrate 10 .
  • the passivation layer 41 is provided on the flat layer 18 .
  • the passivation layer 41 has a third via hole 41A.
  • the third via hole 41A penetrates through the passivation layer 41 and extends to the side of the second semiconductor 31 away from the base substrate 10 through the second via hole 18A.
  • the diameter of the second via hole 18A is larger than that of the third via hole 41 , and the passivation layer 41 covers the inner sidewall of the second via hole 18A.
  • the input electrode 23 is connected to the first semiconductor 21 through the first via hole 14A.
  • the photosensitive electrode 32 is connected to the second semiconductor 31 through the third via hole 41A.
  • the buffer layer 12 , the gate insulating layer 13 and the interlayer insulating layer 14 may be a single-layer structure of silicon oxide, silicon nitride or silicon oxynitride, or may be a silicon oxide/silicon nitride stack structure.
  • the buffer layer 12 serves as a transition film layer between the first semiconductor 21 and the second semiconductor 31 and the base substrate 10 , so that the bonding between the first semiconductor 21 and the second semiconductor 31 and the base substrate 10 is more stable.
  • Both the gate insulating layer 13 and the interlayer insulating layer 14 play a role of isolation.
  • the array substrate 100 further includes a light shielding portion 24 .
  • the light shielding portion 24 is disposed on the side of the base substrate 10 close to the first semiconductor 21 , and the projection of the light shielding portion 24 on the base substrate 10 at least covers the projection of the first semiconductor 21 on the base substrate 10 .
  • the light-shielding portion 24 is a single-layer or laminated structure made of opaque materials.
  • the opaque material can be molybdenum, titanium, molybdenum/titanium (laminate) or titanium/aluminum (laminate).
  • the light shielding portion 24 can absorb the external light from the side of the base substrate 10, so as to prevent the external light from irradiating the channel portion 213 and affecting the working performance of the switching element 20, and preventing the external light from being reflected by the switching element 20 and causing reflection on the display panel. , which affects the display effect of the display panel.
  • FIG. 2 is a schematic diagram of a second structure of the array substrate provided by the present application.
  • the difference from the array substrate 100 shown in FIG. 1 is that in the array substrate 100 provided by the embodiment of the present application, the projection of the light shielding portion 24 on the base substrate 10 completely covers the first semiconductor 21 on the base substrate 10 . and the projection of the second semiconductor 31 on the base substrate 10 .
  • the second semiconductor 31 has the characteristic of generating photo-generated carriers when exposed to light. Therefore, when the second semiconductor 31 receives external light from the side of the base substrate 10, a certain amount of photo-generated carriers will also be generated. current, thereby affecting the accuracy of the photosensitive element 30 .
  • the light shielding portion 24 is provided to shield the external light on the base substrate 10 side, so that the light received by the photosensitive element 30 is only the light required for the under-screen optical fingerprint recognition, thereby improving the accuracy of the photosensitive element 30 .
  • FIG. 3 is a schematic diagram of a third structure of the array substrate provided by the present application.
  • the difference from the array substrate 100 shown in FIG. 1 is that, in the array substrate 100 provided by the embodiment of the present application, the second semiconductor 31 is an intrinsic semiconductor.
  • the second semiconductor 31 and the channel portion 213 are both intrinsic type semiconductors. That is, when ion implantation is performed on the first semiconductor 21 to form the second doping part 212 and the third doping part 214 , a mask can be added to avoid ion doping on the second semiconductor 31 .
  • FIG. 4 is a schematic diagram of a fourth structure of the array substrate provided by the present application.
  • the array substrate 100 provided in this embodiment of the present application further includes a thin film transistor layer 40 .
  • Both the switching element 20 and the photosensitive element 30 are provided in the thin film transistor layer 40 .
  • the photosensitive electrode 32 is connected to the second semiconductor 31 through the fourth via hole 41A.
  • the switching element 20 and the photosensitive element 30 are both disposed in the thin film transistor layer 40, when the thin film transistor layer 40 is prepared by the traditional process, the switching element 20 and the photosensitive element 30 can be prepared together, thereby reducing the process and saving production. cost.
  • the existing PIN-type optical photoreceptor manufacturing method is to realize the N-type region and the P-type region by injecting phosphorane and borane during the chemical vapor deposition film formation process to form a diode, while the existing LTPS production method.
  • the line process realizes the N-type or P-type transformation of semiconductors through ion implantation and high-temperature activation processes. Therefore, the existing PIN-type optical photoreceptor manufacturing method cannot be compatible with the existing LTPS production line process.
  • the switching element 20 and the photosensitive element 30 provided by the embodiment of the present application are compatible with the ion implantation process of the LTPS production line, thereby realizing the mass production of the in-screen ambient light technology.
  • the thin film transistor layer 40 includes a light shielding layer 11, a buffer layer 12, a semiconductor layer 15, a gate insulating layer 13, a gate layer 16, an interlayer insulating layer 14, a source-drain electrode layer 17, a flat layer 18, a common electrode layer 19 and Passivation layer 41 .
  • the light shielding layer 11 is provided on the base substrate 10 .
  • the buffer layer 12 is provided on the light shielding layer 11 and the base substrate 10 .
  • the semiconductor layer 15 is provided on the buffer layer 12 .
  • the gate insulating layer 13 is provided on the semiconductor layer 15 and the buffer layer 12 .
  • the gate layer 16 is provided on the gate insulating layer 13 .
  • the interlayer insulating layer 14 is provided on the gate layer 16 and the gate insulating layer 13 .
  • the source-drain electrode layer 17 is provided on the interlayer insulating layer 14 .
  • the flat layer 18 is provided on the source-drain electrode layer 17 and the interlayer insulating layer 14 .
  • the common electrode layer 19 is provided on the flat layer 18 .
  • the passivation layer 41 is provided on the common electrode layer 19 .
  • the array substrate 100 further includes a pixel electrode layer 42 .
  • the pixel electrode layer 42 is provided on the passivation layer 41 .
  • the source-drain electrode layer 17 includes an input electrode 23 , a source electrode pattern 171 , a drain electrode pattern 172 , a touch electrode 173 and a fingerprint signal electrode 174 .
  • the common electrode layer 19 includes touch traces 191 and first electrodes 192 .
  • the pixel electrode layer 42 includes a photosensitive electrode 32 , a pixel electrode 421 , a second electrode 422 and a signal connection line 423 .
  • the light shielding layer 11 includes a light shielding portion 24 .
  • the semiconductor layer 15 includes a first semiconductor 21 , a second semiconductor 31 and a third semiconductor 151 .
  • the gate layer 16 includes the gate electrode 22 and the gate electrode pattern 161 . Wherein, the first electrode 192 and the second electrode 422 respectively constitute two pole plates of the storage capacitor.
  • the switching transistor 20 includes a first semiconductor 21 , a gate electrode 22 and an input electrode 23 to transmit a bias voltage to the photosensitive element 30 , so that the photosensitive element 30 is reversely biased.
  • the driving transistor 50 includes a third semiconductor 151 , a gate pattern 161 , a source pattern 171 and a drain pattern 172 , so as to drive the sub-pixel units (not shown in the figure) in the array substrate 100 .
  • the interlayer insulating layer 14 has a first via hole 14A.
  • the first via hole 14A penetrates through the interlayer insulating layer 14 and extends to the side of the first semiconductor 21 away from the base substrate 10 .
  • the input electrode 23 is connected to the first semiconductor 21 through the first via hole 14A.
  • the flat layer 18 has the second via hole 18A.
  • the second via hole 18A penetrates through the planarization layer 18 and exposes the side of the interlayer insulating layer 14 away from the base substrate 10 .
  • the passivation layer 41 is provided on the flat layer 18 .
  • the passivation layer 41 has a third via hole 41A.
  • the third via hole 41A penetrates through the passivation layer 41 and extends to the side of the second semiconductor 31 away from the base substrate 10 through the second via hole 18A.
  • the third via hole 41A is disposed corresponding to the second via hole 18A, and the passivation layer 41 covers the inner sidewall of the second via hole 18A.
  • the photosensitive electrode 32 is connected to the second semiconductor 31 through the third via hole 41A.
  • the flat layer 18 also has a fourth via hole 18B, a fifth via hole 18C and a sixth via hole 18D.
  • the fourth via hole 18B exposes a side of the fingerprint signal electrode 174 away from the base substrate 10 .
  • the fifth via hole 18C exposes a side of the drain pattern 172 away from the base substrate 10 .
  • the sixth via hole 18D exposes a side of the touch electrode 173 away from the base substrate 10 .
  • the passivation layer 41 also has a seventh via hole 41B and an eighth via hole 41C.
  • the seventh via hole 41B is disposed corresponding to the fourth via hole 18B, and the passivation layer 41 covers the inner sidewall of the fourth via hole 18B.
  • the eighth via hole 41C is disposed corresponding to the fifth via hole 18C, and the passivation layer 41 covers the inner sidewall of the fifth via hole 18C.
  • the photosensitive electrode 32 is connected to the signal connection line 423, and the signal connection line 423 is connected to the fingerprint signal electrode 174 through the seventh via hole 41B, so as to realize the transmission of the fingerprint signal.
  • the pixel electrode 421 is connected to the drain pattern 172 through the eighth via hole 41C.
  • the touch electrodes 173 are connected to the touch traces 191 through the sixth via holes 18D, so as to realize the touch function.
  • the array substrate 100 has a display area VA and a non-display area NA connected to the display area VA. Both the switching element 20 and the photosensitive element 30 are located in the non-display area NA, so that the aperture ratio of the display panel is not affected.
  • the non-display area NA is a GOA (Gate Driveron Array, gate driver on array substrate) circuit area.
  • GOA Gate Driveron Array, gate driver on array substrate
  • a double-side driving method in which the GOA circuit area is arranged on both sides of the display area VA may be adopted, or a single-side driving method in which the GOA circuit area is arranged on one side of the display area VA may be adopted.
  • the non-display area NA includes a GOA circuit area and a dummy pixel area, and the dummy pixel area is located at least on one side of the display area VA.
  • the GOA circuit area and the dummy pixel area are located on the same side of the display area VA, the GOA circuit area is located on the side of the dummy pixel area away from the display area VA.
  • the virtual pixel area is not used for screen display, and is only used to improve the display uniformity of the display panel.
  • the switch element 20 and the photosensitive element 30 are arranged in the dummy pixel area, so as not to affect the aperture ratio of the display panel, and to avoid interference to the lines in the GOA circuit area.
  • the switch element 20 and the photosensitive element 30 may also be disposed in the display area VA of the array substrate 100 , which is not limited in this application.
  • FIG. 5 is a first schematic flowchart of the manufacturing method of the array substrate provided by the present application. The specific steps include:
  • the base substrate 10 may be cleaned and pre-baked to remove foreign particles such as oil and grease on the surface of the base substrate 10 .
  • the light shielding portion 24 is formed on the base substrate 10 .
  • the base substrate 10 may be a glass substrate, a quartz substrate, a resin substrate, a PI flexible substrate or other types of substrates, which will not be described in detail here.
  • the light-shielding portion 24 is a single-layer or laminated structure made of opaque material.
  • the opaque material can be molybdenum, titanium, molybdenum/titanium (laminate) or titanium/aluminum (laminate).
  • the switching element includes a first semiconductor, and the first semiconductor is disposed on the base substrate.
  • the buffer layer 12 is deposited on the base substrate 10 and the light shielding portion 24 .
  • the material of the buffer layer 12 may be one or more of silicon oxide, silicon nitride or silicon oxynitride.
  • the buffer layer 12 may be formed by an evaporation process, a chemical vapor deposition process, a coating process, a sol-gel process or other processes.
  • a first semiconductor 21 is formed on the buffer layer 12, and ion implantation is performed on the first semiconductor 21 in two steps to form a first doping part 211, a second doping part 212, a channel part 213, and a third doping part 214 and the fourth doping part 215 .
  • the material of the first semiconductor 21 is polysilicon.
  • the thickness of the first semiconductor 21 is 400 angstroms to 600 angstroms.
  • Both the first doping portion 211 and the fourth doping portion 215 are heavily N-type doped.
  • Both the second doping part 212 and the third doping part 214 are N-type lightly doped.
  • a gate insulating layer 13 is deposited on the first semiconductor 21 and the buffer layer 12 .
  • the gate electrode 22 is formed on the gate insulating layer 13 .
  • the interlayer insulating layer 14 is formed on the gate electrode 22 and the gate insulating layer 13 .
  • the interlayer insulating layer 14 is patterned to form the first via holes 14A.
  • the first via hole 14A penetrates through the interlayer insulating layer 14 and extends to the side of the first semiconductor 21 away from the base substrate 10 .
  • the input electrode 23 is formed on the interlayer insulating layer 14 .
  • the input electrode 23 is connected to the first semiconductor 21 through the first via hole 14A.
  • the materials of the gate insulating layer 13 and the interlayer insulating layer 14 are silicon oxide, silicon nitride, silicon oxynitride or silicon oxide/silicon nitride (stack).
  • the material of the gate electrode 22 is silver, aluminum, copper, molybdenum, molybdenum/aluminum/molybdenum (stack) or molybdenum/copper (stack).
  • a photosensitive element is formed on the base substrate, the photosensitive element is disposed adjacent to the switching element on the base substrate, the photosensitive element includes a second semiconductor and a photosensitive electrode, the second The semiconductor is connected to the first semiconductor and arranged in the same layer, and the photosensitive electrode is arranged on the side of the second semiconductor away from the base substrate, and is connected to the second semiconductor.
  • the second semiconductor 31 may be formed simultaneously with the first semiconductor 21 in step 102 .
  • the ion implantation on the second semiconductor 31 may be performed at the same time to form the N-type lightly doped second semiconductor 31 .
  • a flat layer 18 is formed on the interlayer insulating layer 14 .
  • the planarization layer 18 is patterned to form the second via holes 18A.
  • the second via hole 18A penetrates through the planarization layer 18 and exposes the side of the interlayer insulating layer 14 away from the base substrate 10 .
  • a passivation layer 41 is formed on the flat layer 18 .
  • the passivation layer 41 is patterned to form third via holes 41A.
  • the passivation layer 41 covers the inner sidewall of the second via hole 18A.
  • the photosensitive electrode 32 is deposited on the passivation layer 41 .
  • the photosensitive electrode 32 is connected to the second semiconductor 31 through the third via hole 41A.
  • the material of the second semiconductor 31 is polysilicon.
  • the thickness of the second semiconductor 31 is 400 angstroms to 600 angstroms.
  • the material of the photosensitive electrode 32 is a conductive material with a high work function, so that a Schottky junction is formed between the photosensitive electrode 32 and the second semiconductor 31 .
  • the conductive material with high work function may be indium zinc oxide, zinc oxide or indium gallium zinc oxide.
  • FIG. 6 is a second schematic flowchart of the manufacturing method of the array substrate provided by the present application. The specific steps include:
  • 201 Provide a base substrate, and form a light shielding layer on the base substrate.
  • the base substrate 10 may be cleaned and pre-baked to remove foreign particles such as oil and grease on the surface of the base substrate 10 .
  • the light shielding layer 11 partially covers the base substrate 10 .
  • the light shielding layer 11 includes a light shielding portion 24 .
  • the base substrate 10 may be a glass substrate, a quartz substrate, a resin substrate, a PI flexible substrate or other types of substrates, which will not be described in detail here.
  • the opaque material can be molybdenum, titanium, molybdenum/titanium (laminate) or titanium/aluminum (laminate).
  • a buffer layer 12 is formed on the light shielding layer 11 .
  • the buffer layer 12 covers the light shielding layer 11 and the base substrate 10 .
  • the semiconductor layer 15 includes a first semiconductor 21 and a second semiconductor 31 .
  • the thickness of the semiconductor layer 15 is 400 angstroms to 600 angstroms.
  • the semiconductor layer 15 is doped with phosphorus ions by means of ion implantation.
  • the first doping portion 211 and the fourth doping portion 215 are formed in the first semiconductor 21 .
  • Both the first doping portion 211 and the fourth doping portion 215 are heavily N-type doped.
  • the gate insulating layer 13 is deposited on the semiconductor layer 15 and the buffer layer 12 .
  • the gate insulating layer 13 may be a silicon oxide layer or a silicon nitride layer, or may be a stacked structure of silicon oxide and silicon nitride.
  • a first metal layer is deposited on the gate insulating layer 13 , and the first metal layer is patterned to form the gate layer 16 .
  • Gate layer 16 includes gate 22 .
  • the material of the first metal layer is silver, aluminum, copper, molybdenum, molybdenum/aluminum/molybdenum (stack) or molybdenum/copper (stack).
  • the second ion implantation is performed on the semiconductor layer 15 using the gate layer 16 as a shielding layer.
  • the second doping portion 212 and the third doping portion 214 are formed in the first semiconductor 21 .
  • Both the second doping part 212 and the third doping part 214 are N-type lightly doped.
  • the second semiconductor 31 can also become an N-type semiconductor through the second ion implantation.
  • the interlayer insulating layer 14 is deposited on the gate layer 16 and the gate insulating layer 13 .
  • the interlayer insulating layer 14 is hydrogenated and activated by a rapid thermal annealing process, and then the interlayer insulating layer 14 is patterned by a process such as exposure and etching to form a plurality of first vias 14A.
  • the first via hole 14A penetrates through the interlayer insulating layer 14 and extends to the side of the semiconductor layer 15 away from the base substrate 10 .
  • a second metal layer is deposited on the interlayer insulating layer 14 , and the second metal layer is patterned to form the source-drain electrode layer 17 .
  • the source-drain electrode layer 17 includes a source pattern 171 , a drain pattern 172 , a touch electrode 173 , a fingerprint signal electrode 174 and an input electrode 23 .
  • the source pattern 171 and the drain pattern 172 are connected to the semiconductor layer 15 through the corresponding first via holes 14A, respectively.
  • the input electrodes 23 are connected to the first semiconductors 21 through the corresponding first vias 14A.
  • the flat layer 18 is formed on the source-drain electrode layer 17 and the interlayer insulating layer 14 .
  • the planarization layer 18 is patterned to form the second via hole 18A, the fourth via hole 18B, the fifth via hole 18C and the sixth via hole 18D.
  • the second via hole 18A penetrates through the planarization layer 18 and exposes a side of the interlayer insulating layer 14 away from the base substrate 10 .
  • the fourth via hole 18B exposes a side of the fingerprint signal electrode 174 away from the base substrate 10 .
  • the fifth via hole 18C exposes a side of the drain pattern 172 away from the base substrate 10 .
  • the sixth via hole 18D exposes a side of the touch electrode 173 away from the base substrate 10 .
  • a first transparent metal layer is deposited on the flat layer 18 , and the first transparent metal layer is patterned to form the common electrode layer 19 .
  • the common electrode layer 19 includes touch traces 191 and first electrodes 192 .
  • the touch electrodes 173 and the touch traces 191 are connected through vias to realize the touch function.
  • a passivation layer 41 is deposited on the common electrode layer 19 and the flat layer 18, and the passivation layer 41 is patterned to form the third via hole 41A, the seventh via hole 41B and the eighth via hole 41C.
  • the third via hole 41A and the third via hole 18A are provided correspondingly.
  • the passivation layer 41 covers the inner sidewall of the second via hole 18A.
  • the third via hole 41A penetrates through the passivation layer 41 and extends to the side of the second semiconductor 31 away from the base substrate 10 .
  • the seventh via hole 41B is disposed corresponding to the fourth via hole 18B, and the passivation layer 41 covers the inner sidewall of the fourth via hole 18B.
  • the eighth via hole 41C is disposed corresponding to the fifth via hole 18C, and the passivation layer 41 covers the inner sidewall of the fifth via hole 18C.
  • a second transparent metal layer is deposited on the passivation layer 41 , and the second transparent metal layer is patterned to form the pixel electrode layer 42 .
  • the pixel electrode layer 42 includes a pixel electrode 421 , a second electrode 422 , a signal connection line 423 and a photosensitive electrode 32 .
  • the first electrode 192 and the second electrode 422 respectively constitute two pole plates of the storage capacitor.
  • the photosensitive electrode 32 is connected to the signal connection line 423, and the signal connection line 423 is connected to the fingerprint signal electrode 174 through the seventh via hole 41B, so as to realize the transmission of the fingerprint signal.
  • the pixel electrode 421 is connected to the drain pattern 172 through the eighth via hole 41C.
  • the touch electrodes 173 are connected to the touch traces 191 through the sixth via holes 18D, so as to realize the touch function.
  • the photosensitive electrode 32 is connected to the second semiconductor 31 through the third via hole 41A.
  • the switching element 20 and the photosensitive element 30 can be compatible with the LTPS process, realizing the mass production of the in-screen ambient light technology, and the photosensitive element 30 with the Schottky junction can realize relatively The strong light absorbing ability improves the sensitivity of the photosensitive element 30 .
  • patterning refers to the step of forming a specific pattern structure, which can be a photolithography process.
  • the photolithography process includes forming a material layer, coating photoresist, exposing, One or more steps in the steps of developing, etching, photoresist stripping, etc., are processes understood by those skilled in the art and will not be repeated here.
  • the present application further provides a display panel
  • the display panel includes the array substrate described in any one of the above embodiments, for details, please refer to the above content, which will not be repeated here.
  • the display panel provided by the present application may be an organic light emitting diode display panel, an active matrix organic light emitting diode display panel, a passive matrix organic light emitting diode display panel, a quantum dot organic light emitting diode display panel or a micro light emitting diode display panel. There is no specific limitation.
  • FIG. 7 is a schematic structural diagram of a display panel provided by the present application.
  • the display panel 1000 provided by the embodiment of the present application further includes the GOA circuit 300 and other functional components.
  • the switching element and the photosensitive element can be arranged in the same area as the GOA circuit 300 , so that the aperture ratio of the display panel 1000 is not affected.
  • the GOA circuit 300 and other functional components in the embodiments of the present application are related technologies well known to those skilled in the art, and details are not described herein again.
  • the display panel 1000 further includes a dummy pixel area (not marked in the figure).
  • the dummy pixel area is located between the GOA circuit 300 and the display area VA.
  • the virtual pixel area is not displayed on the screen.
  • the switching element 20 and the photosensitive element 30 are located in the dummy pixel area, so that the aperture ratio of the display panel is not affected, and at the same time, interference to the lines in the GOA circuit area can be avoided.
  • the display panel provided by the present application includes an array substrate, the array substrate includes: a base substrate; a switch element is disposed on the base substrate, the switch element includes a first semiconductor, and the first semiconductor is disposed on the base substrate a base substrate; and a photosensitive element, which is arranged on the base substrate adjacent to the switching element, the photosensitive element includes a second semiconductor and a photosensitive electrode, the second semiconductor is connected to the first semiconductor and The photosensitive electrode is disposed on the side of the second semiconductor away from the base substrate, and is connected to the second semiconductor; wherein, a Schottky junction is formed between the second semiconductor and the photosensitive electrode, The effective photosensitive area of the photosensitive element is increased, thereby improving the sensitivity of the photosensitive element, thereby improving the quality of the display panel.

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Abstract

本申请提供一种阵列基板和显示面板，阵列基板包括衬底基板、相邻设置在衬底基板上的开关元件以及感光元件。开关元件包括设置在衬底基板上的第一半导体。感光元件包括与第一半导体相连且同层设置的第二半导体，以及设置在第二半导体远离衬底基板的一侧且与第二半导体连接的感光电极。感光电极与第二半导体形成肖特基结。

Description

阵列基板和显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板和显示面板。
 背景技术
目前，指纹识别技术已广泛应用于中小尺寸的面板中，其中主要有电容式、超声波式和光学式等几种方式。相比于电容式和超声波式指纹识别技术，光学指纹识别稳定性好、抗静电能力强、穿透能力好且成本较低。光学指纹识别技术利用光的折射和反射原理，当光照射到手指上，经手指反射后由感光传感器接收，感光传感器可将光信号转换为电学信号，从而进行读取。
 技术问题
现有感光传感器中的感光元件的有效光敏面积较小，导致感光元件的灵敏度较低。
 技术解决方案
本申请提供了一种阵列基板和显示面板，以解决现有技术中感光元件的有效光敏面积较小，导致感光元件的灵敏度较低的技术问题。
本申请提供一种阵列基板，其包括：
衬底基板；
开关元件，设置在所述衬底基板上，所述开关元件包括第一半导体，所述第一半导体设置在所述衬底基板上；以及
感光元件，与所述开关元件相邻设置在所述衬底基板上，所述感光元件包括第二半导体和感光电极，所述第二半导体与所述第一半导体相连且同层设置，所述感光电极设置在所述第二半导体远离所述衬底基板的一侧，且与所述第二半导体连接；
其中，所述感光电极与所述第二半导体形成肖特基结。
在本申请提供的阵列基板中，所述第二半导体为本征型半导体或者N型半导体。
在本申请提供的阵列基板中，所述第一半导体包括沿水平方向依次设置在所述衬底基板上的第一掺杂部、第二掺杂部、沟道部、第三掺杂部以及第四掺杂部，所述第四掺杂部和所述第二半导体连接；
其中，所述第一掺杂部和所述第四掺杂部均为N型重掺杂，所述第二掺杂部、所述第三掺杂部以及所述第二半导体均为N型轻掺杂。
在本申请提供的阵列基板中，所述开关元件还包括：
栅极，设置在所述第一半导体远离所述衬底基板的一侧，且与所述第一半导体绝缘设置；以及
输入电极，设置在所述第一半导体远离所述衬底基板的一侧，且与所述第一半导体远离所述第二半导体的一端连接。
在本申请提供的阵列基板中，所述阵列基板还包括薄膜晶体管层，所述开关元件和所述感光元件均设置在所述薄膜晶体管层中。
在本申请提供的阵列基板中，所述薄膜晶体管层包括：
半导体层，设置在所述衬底基板上，所述半导体层包括所述第一半导体和所述第二半导体；
栅绝缘层，设置在所述半导体层上；
栅极层，设置在所述栅绝缘层上，所述栅极层包括所述栅极；
层间绝缘层，设置在所述栅绝缘层和所述栅极层上，所述层间绝缘层具有第一过孔，所述第一过孔贯穿所述层间绝缘层并延伸至所述第一半导体远离所述衬底基板的一侧；以及
源漏电极层，设置在所述层间绝缘层上，所述源漏电极层包括所述输入电极，所述输入电极通过第一过孔与所述第一半导体层连接，所述第一过孔贯穿所述层间绝缘层以及所述栅绝缘层。
在本申请提供的阵列基板中，所述薄膜晶体管层还包括：平坦层，设置在所述源漏电极层和所述层间绝缘层上，所述平坦层具有第二过孔，所述第二过孔贯穿所述平坦层，并暴露出所述层间绝缘层远离所述衬底基板的一侧；
公共电极层，设置在所述平坦层上；以及
钝化层，设置在所述公共电极层和所述平坦层上，所述钝化层具有第三过孔，所述第三过孔贯穿所述钝化层，并通过所述第二过孔延伸至所述第二半导体远离所述衬底基板的一侧，所述第二过孔的孔径大于所述第三过孔的孔径，且所述钝化层覆盖所述第二过孔的内侧壁；
其中，所述感光电极通过所述第三过孔与所述第二半导体连接。
在本申请提供的阵列基板中，所述阵列基板还包括像素电极层，所述像素电极层设置在所述钝化层上；
其中，所述感光电极和所述像素电极层同层设置。
在本申请提供的阵列基板中，所述源漏电极层包括源极、漏极、触控电极以及指纹信号电极，所述公共电极层包括触控走线和第一电极，所述像素电极层包括像素电极、第二电极以及信号连接线。
在本申请提供的阵列基板中，所述平坦层还具有第四过孔、第五过孔以及第六过孔，所述第四过孔暴露出所述指纹信号电极远离所述衬底基板的一侧，所述第五过孔暴露出所述漏极远离所述衬底基板的一侧，所述第六过孔暴露出所述触控电极远离所述衬底基板的一侧；以及
所述钝化层还具有第七过孔和第八过孔，所述第七过孔与所述第四过孔对应设置，且所述钝化层覆盖所述第四过孔的内侧壁，所述第八过孔对应所述第五过孔设置，且所述钝化层覆盖所述第五过孔的内侧壁；其中，所述感光电极通过所述第三过孔与所述第二半导体连接。
在本申请提供的阵列基板中，所述阵列基板还包括像素电极层，所述像素电极层设置在所述钝化层上，所述像素电极层包括像素电极、第二电极以及信号连接线；
其中，所述感光电极和所述像素电极层同层设置。
在本申请提供的阵列基板中，所述感光电极与所述信号连接线连接，所述信号连接线通过所述第七过孔与所述指纹信号电极连接；所述像素电极通过所述第八过孔与所述漏极连接；所述触控电极通过所述第六过孔与所述触控走线连接。
在本申请提供的阵列基板中，所述阵列基板具有显示区和虚拟像素区，所述虚拟像素区至少位于所述显示区的一侧，所述开关元件和所述感光元件均位于所述虚拟像素区。
在本申请提供的阵列基板中，所述阵列基板还包括遮光部，所述遮光部设置在所述衬底基板靠近所述第一半导体的一侧，且所述遮光部在所述衬底基板上的投影至少覆盖所述第一半导体在所述衬底基板上的投影。
在本申请提供的阵列基板中，所述遮光部在所述衬底基板上的投影覆盖所述第一半导体在所述衬底基板上的投影以及所述第二半导体在所述衬底基板上的投影。
在本申请提供的阵列基板中，所述感光电极的材料为氧化铟锌、氧化锌或者氧化铟镓锌。
在本申请提供的阵列基板中，所述第一半导体和所述第二半导体的材料均为多晶硅。
在本申请提供的阵列基板中，所述第二半导体的厚度为400埃至600埃。
本申请还提供一种显示面板，其包括阵列基板，所述阵列基板包括：
衬底基板；
开关元件，设置在所述衬底基板上，所述开关元件包括第一半导体，所述第一半导体设置在所述衬底基板上；以及
感光元件，与所述开关元件相邻设置在所述衬底基板上，所述感光元件包括第二半导体和感光电极，所述第二半导体与所述第一半导体相连且同层设置，所述感光电极设置在所述第二半导体远离所述衬底基板的一侧，且与所述第二半导体连接；
其中，所述感光电极与所述第二半导体形成肖特基结。
在本申请提供的显示面板中，所述第二半导体为本征型半导体或者N型半导体。
在本申请提供的显示面板中，所述感光电极的材料为氧化铟锌、氧化锌或者氧化铟镓锌。
 有益效果
本申请提供一种阵列基板和显示面板，所述阵列基板包括相邻设置在衬底基板上的开关元件和感光元件，所述感光元件包括第二半导体以及与所述第二半导体连接的感光电极，所述感光电极设置在所述第二半导体远离所述衬底基板的一侧，且与所述第二半导体连接。其中，感光电极与第二半导体形成肖特基结，增加了感光元件的有效光敏面积，且感光元件接收光线后能够在垂直方向上形成内建电场，可更加有效地分离电子-空穴对，增大光生电流，从而提高感光元件的灵敏度。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的阵列基板的第一结构示意图；
图2是本申请提供的阵列基板的第二结构示意图；
图3是本申请提供的阵列基板的第三结构示意图；
图4是本申请提供的阵列基板的第四结构示意图；
图5是本申请提供的阵列基板的制作方法的第一流程示意图；
图6是本申请提供的阵列基板的制作方法的第二流程示意图；
图7是本申请提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，图1是本申请提供的阵列基板的第一结构示意图。如图1所示，阵列基板100包括衬底基板10、开关元件20以及感光元件30。开关元件20设置在衬底基板10上。开关元件20包括第一半导体21。第一半导体21设置在衬底基板10上。感光元件30与开关元件20相邻设置在衬底基板10上。感光元件30包括第二半导体31和感光电极32。第二半导体31与第一半导体21相连且同层设置。感光电极32设置在第二半导体31远离衬底基板10的一侧，且与第二半导体31连接。其中，感光电极32与第二半导体31形成肖特基结。
由此可知，在本申请实施例提供的阵列基板100中，开关元件20和感光元件30协同工作，以实现屏下光学指纹识别等功能。其中，感光元件30包括叠层设置的第二半导体31和感光电极32，以在第二半导体31和感光电极32之间形成肖特基结，增加了感光元件30的有效光敏面积；同时，感光元件30接收光线后能够在垂直方向Y上形成内建电场，可更加有效地分离电子-空穴对，增大光生电流，从而提高感光元件30的灵敏度；此外，相较于现有技术，在本申请实施例提供的感光元件30中，不需要额外设置感光层，从而可以减少光罩，降低生产成本。
其中，肖特基结是一种简单的金属与半导体的交界面，它与PN结相似，具有非线性阻抗特性。1938年德国的W.H.肖特基提出理论模型，对此特性作了科学的解释，故后来把这种金属与半导体的交界面称为肖特基结或肖特基势垒。
在本申请实施例中，衬底基板10可以为玻璃基板、石英基板、树脂基板、PI（聚酰亚胺，Polyimide）柔性基板或其他类型基板，在此不一一赘述。
在本申请实施例中，开关元件20用于提供感光元件30工作所需的偏置电压。开关元件20为薄膜晶体管，其可以为底栅型或顶栅型。本申请以下各实施例均以开关元件20为顶栅型薄膜晶体管为例进行说明，但并不限于此。
具体的，开关元件20还包括栅极22和输入电极23。栅极22设置在第一半导体21远离衬底基板10的一侧。栅极22和第一半导体21绝缘设置。输入电极23设置在第一半导体21远离衬底基板10的一侧，且与第一半导体21远离第二半导体31的一端连接。
其中，输入电极23用于接入一偏置电压。开关元件20将偏置电压传输至感光元件30，使得感光元件30发生反偏。然后开关元件20关闭，当入射光入射到感光元件30后，可以激发感光元件30产生光生电荷，从而形成屏下光学指纹识别所需的光电流信号。
其中，第一半导体21的材料为多晶硅。栅极22和输入电极23的材料可以是导电性良好的单层金属或不同金属的叠层。比如，栅极22的材料是银、铝、铜、钼、钼/铝/钼（叠层）或者钼/铜（叠层）。
在本申请实施例中，第一半导体21包括沿水平方向X依次设置在衬底基板10上的第一掺杂部211、第二掺杂部212、沟道部213、第三掺杂部214以及第四掺杂部215。第四掺杂部215和第二半导体31连接。具体的，第一掺杂部211、第二掺杂部212、沟道部213、第三掺杂部214以及第四掺杂部215沿水平方向X依次连接。栅极22对应沟道部213设置。输入电极23与第一掺杂部211连接。
其中，第一掺杂部211和第四掺杂部215均为N型重掺杂。第二掺杂部212和第三掺杂部214均为N型轻掺杂。沟道部213为本征型半导体。
具体的，第一掺杂部211、第二掺杂部212、第三掺杂部214以及第四掺杂部215均通过在第一半导体21中掺杂磷离子得到。其中，N型重掺杂和N型轻掺杂的不同之处在于磷离子的掺杂浓度不同。
在本申请实施例中，第一半导体21和第二半导体31的材料均为多晶硅。可以理解的是，在传统LTPS（Low Temperature Poly-silicon，低温多晶硅）制程中，由于受到准分子激光退火工艺对多晶硅晶化厚度的限制，第一半导体21和第二半导体31的厚度较薄。若仅在水平方向X存在内建电场，则感光元件30对入射光的光电响应会比较低，光生电子-空穴对较少，从而影响感光元件30的灵敏度。
而在本申请实施例中，由于第二半导体31和感光电极32之间形成叠层结构的肖特基结，一方面增加了感光元件30的有效光敏面积，另一方面感光元件30接收光线后能够在垂直方向Y上形成内建电场，增大光生电流。因此，第二半导体31的厚度可以做得很薄。具体的，第二半导体31的厚度为400埃至600埃。比如，第二半导体31的厚度为400埃、450埃、500埃、550埃或者600埃。
进一步的，在本申请实施例中，第一半导体21的厚度可以等于第二半导体31的厚度。第一半导体21的厚度为400埃至600埃。比如，第一半导体21的厚度为400埃、450埃、500埃、550埃或者600埃。第一半导体21和第二半导体31可通过同一工艺形成。
在本申请实施例中，第二半导体31为N型半导体。具体的，第二半导体31、第二掺杂部212以及第三掺杂部214均为N型轻掺杂。可以理解的是，在传统LTPS制程中，在对第一半导体21进行离子注入以形成第二掺杂部212和第三掺杂部214时，采用的是整面离子注入工艺。因此，本申请实施例通过将第二半导体31和第一半导体21同层设置，可以在形成第二掺杂部212和第三掺杂部214时，同时形成N型轻掺杂的第二半导体31，从而增强内建电场的强度，并减少工艺制程。
在本申请实施例中，感光电极32的材料为功函数高的导电材料，以便感光电极32和第二半导体31之间形成肖特基结。其中，功函数高的导电材料可以是氧化铟锌、氧化锌或者氧化铟镓锌。
此外，阵列基板100还包括缓冲层12、栅绝缘层13、层间绝缘层14、平坦层18和钝化层41。缓冲层12设置在衬底基板10靠近第一半导体21的一侧，并覆盖衬底基板10。栅绝缘层13设置在栅极22靠近衬底基板10的一侧，并覆盖第一半导体21、第二半导体31以及缓冲层12。层间绝缘层14设置在栅极22远离衬底基板10的一侧，并覆盖栅极22和栅绝缘层13。层间绝缘层14具有第一过孔14A。第一过孔14A贯穿层间绝缘层14并延伸至第一半导体21远离衬底基板10的一侧。平坦层18设置在层间绝缘层14远离衬底基板10的一侧，且覆盖输入电极23。平坦层18具有第二过孔18A。第二过孔18A贯穿平坦层18并暴露出层间绝缘层14远离衬底基板10的一侧。钝化层41设置在平坦层18上。钝化层41具有第三过孔41A。第三过孔41A贯穿钝化层41，并通过第二过孔18A延伸至第二半导体31远离衬底基板10的一侧。第二过孔18A的孔径大于第三过孔41的孔径，且钝化层41覆盖第二过孔18A的内侧壁。
其中，输入电极23通过第一过孔14A与第一半导体21连接。感光电极32通过第三过孔41A和第二半导体31连接。
其中，缓冲层12、栅绝缘层13以及层间绝缘层14可以是氧化硅、氮化硅或氮氧化硅单层结构，也可以是氧化硅/氮化硅叠层结构。缓冲层12作为第一半导体21以及第二半导体31和衬底基板10之间的过渡膜层，使第一半导体21以及第二半导体31和衬底基板10之间的结合更稳固。栅绝缘层13以及层间绝缘层14均起到了隔离的作用。
在本申请实施例中，请继续参阅图1，阵列基板100还包括遮光部24。遮光部24设置在衬底基板10靠近第一半导体21的一侧，且遮光部24在衬底基板10上的投影至少覆盖第一半导体21在衬底基板10上的投影。
其中，遮光部24为采用不透光材料制成的单层或叠层结构。不透光材料可为钼、钛、钼/钛(叠层)或者钛/铝(叠层)。遮光部24可吸收来自衬底基板10一侧的外部光线，避免外部光线照射沟道部213后影响开关元件20的工作性能，以及避免外部光线被开关元件20反射后，在显示面板上产生反光，影响显示面板的显示效果。
在本申请另一实施例中，请参阅图2，图2是本申请提供的阵列基板的第二结构示意图。与图1所示的阵列基板100的不同之处在于，在本申请实施例提供的阵列基板100中，遮光部24在衬底基板10上的投影完全覆盖第一半导体21在衬底基板10上的投影以及第二半导体31在衬底基板10上的投影。
可以理解的是，第二半导体31具有在受到光照的情况下产生光生载流子的特性，因此，第二半导体31接收到来自衬底基板10一侧的外部光线时，也会产生一定的光生电流，从而对感光元件30的精准度产生影响。本申请实施例通过设置遮光部24，以遮挡衬底基板10侧的外部光线，可以保证感光元件30接收的光线仅为屏下光学指纹识别所需的光线，从而提高感光元件30的精准度。
在本申请另一实施例中，请参阅图3，图3是本申请提供的阵列基板的第三结构示意图。与图1所示的阵列基板100的不同之处在于，在本申请实施例提供的阵列基板100中，第二半导体31为本征型半导体。
具体的，第二半导体31和沟道部213均为本征型半导体。即在对第一半导体21进行离子注入以形成第二掺杂部212和第三掺杂部214时，可增加一道光罩，避免对第二半导体31进行离子掺杂。
请参阅图4，图4是本申请提供的阵列基板的第四结构示意图。与图1所示的阵列基板100的不同之处在于，本申请实施例提供的阵列基板100还包括薄膜晶体管层40。开关元件20和感光元件30均设置在薄膜晶体管层40中。且感光电极32通过第四过孔41A与第二半导体31连接。
其中，由于开关元件20和感光元件30均设置在薄膜晶体管层40中，因此在利用传统工艺制程制备薄膜晶体管层40时，可以一同制备开关元件20和感光元件30，从而减少工艺制程，节约生产成本。
可以理解的是，现有PIN型光学感光器的制作方法是通过在化学气相沉积成膜过程中注入磷烷和硼烷来实现N型区和P型区，以构成二极管，而现有LTPS产线工艺实现半导体的N型或者P型转变是通过离子注入和高温活化工艺，因此，现有PIN型光学感光器的制作方法无法兼容现有的LTPS产线工艺。而本申请实施例提供的开关元件20和感光元件30可兼容LTPS产线的离子注入工艺，从而实现屏内环境光技术的量产。
其中，薄膜晶体管层40包括遮光层11、缓冲层12、半导体层15、栅绝缘层13、栅极层16、层间绝缘层14、源漏电极层17、平坦层18、公共电极层19以及钝化层41。
具体的，遮光层11设置在衬底基板10上。缓冲层12设置在遮光层11和衬底基板10上。半导体层15设置在缓冲层12上。栅绝缘层13设置在半导体层15和缓冲层12上。栅极层16设置在栅绝缘层13上。层间绝缘层14设置在栅极层16和栅绝缘层13上。源漏电极层17设置在层间绝缘层14上。平坦层18设置在源漏电极层17和层间绝缘层14上。公共电极层19设置在平坦层18上。钝化层41设置在公共电极层19上。
进一步的，阵列基板100还包括像素电极层42。像素电极层42设置在钝化层41上。
进一步的，源漏电极层17包括输入电极23、源极图案171、漏极图案172、触控电极173以及指纹信号电极174。公共电极层19包括触控走线191和第一电极192。像素电极层42包括感光电极32、像素电极421、第二电极422以及信号连接线423。遮光层11包括遮光部24。半导体层15包括第一半导体21、第二半导体31以及第三半导体151。栅极层16包括栅极22和栅极图案161。其中，第一电极192和第二电极422分别构成存储电容的两个极板。
其中，开关晶体管20包括第一半导体21、栅极22和输入电极23，以将偏置电压传输至感光元件30，使得感光元件30发生反偏。驱动晶体管50包括第三半导体151、栅极图案161、源极图案171和漏极图案172，以驱动阵列基板100中的子像素单元（图中未标示）。
具体的，层间绝缘层14具有第一过孔14A。第一过孔14A贯穿层间绝缘层14并延伸至第一半导体21远离衬底基板10的一侧。输入电极23通过第一过孔14A与第一半导体21连接。平坦层18具有第二过孔18A。第二过孔18A贯穿平坦层18并暴露出层间绝缘层14远离衬底基板10的一侧。钝化层41设置在平坦层18上。钝化层41具有第三过孔41A。第三过孔41A贯穿钝化层41，并通过第二过孔18A延伸至第二半导体31远离衬底基板10的一侧。第三过孔41A与第二过孔18A对应设置，且钝化层41覆盖第二过孔18A的内侧壁。感光电极32通过第三过孔41A与第二半导体31连接。
进一步的，平坦层18还具有第四过孔18B、第五过孔18C以及第六过孔18D。第四过孔18B暴露出指纹信号电极174远离衬底基板10的一侧。第五过孔18C暴露出漏极图案172远离衬底基板10的一侧。第六过孔18D暴露出触控电极173远离衬底基板10的一侧。
钝化层41还具有第七过孔41B和第八过孔41C。第七过孔41B与第四过孔18B对应设置，且钝化层41覆盖第四过孔18B的内侧壁。第八过孔41C对应第五过孔18C设置，且钝化层41覆盖第五过孔18C的内侧壁。
其中，感光电极32与信号连接线423连接，信号连接线423通过第七过孔41B与指纹信号电极174连接，以实现指纹信号的传输。像素电极421通过第八过孔41C与漏极图案172连接。触控电极173通过第六过孔18D与触控走线191连接，以实现触控功能。
在本申请实施例中，阵列基板100具有显示区VA和连接显示区VA的非显示区NA。开关元件20和感光元件30均位于非显示区NA，从而不影响显示面板的开口率。
具体的，在本申请一实施例中，非显示区NA为GOA（Gate Driveron Array，阵列基板栅极驱动技术）电路区。开关元件20和感光元件30均位于GOA电路区，从而不影响显示面板的开口率。
其中，本申请实施例可以采用GOA电路区设置在显示区VA两侧的双侧驱动方式，也可以采用GOA电路区设置在显示区VA一侧的单侧驱动方式。
在本申请另一实施例中，非显示区NA包括GOA电路区和虚拟像素区，虚拟像素区至少位于显示区VA的一侧。当GOA电路区和虚拟像素区位于显示区VA的同一侧时，GOA电路区位于虚拟像素区远离显示区VA的一侧。
其中，虚拟像素区不进行画面显示，仅用于提高显示面板的显示均匀性。则将开关元件20和感光元件30设置于虚拟像素区，从而不影响显示面板的开口率，避免对GOA电路区的线路产生干扰。
需要说明的是，开关元件20和感光元件30也可以设置在阵列基板100的显示区VA，本申请对此不作限定。
本申请还提供一种阵列基板的制作方法，请同时参阅图1和图5，图5是本申请提供的阵列基板的制作方法的第一流程示意图，具体步骤包括：
101、提供一衬底基板。
具体的，可对衬底基板10进行清洗以及预烘烤，以去除衬底基板10表面的油类、油脂等异物微粒。
然后，在衬底基板10上形成遮光部24。
其中，衬底基板10可以为玻璃基板、石英基板、树脂基板、PI柔性基板或其他类型基板，在此不一一赘述。遮光部24为采用不透光材料制成的单层或叠层结构。不透光材料可为钼、钛、钼/钛(叠层)或者钛/铝(叠层)。
102、在所述衬底基板上形成一开关元件，所述开关元件包括第一半导体，所述第一半导体设置在所述衬底基板上。
具体的，在衬底基板10和遮光部24上沉积缓冲层12。缓冲层12的材料可以是氧化硅、氮化硅或氮氧化硅中的一种或多种。缓冲层12可采用蒸镀工艺、化学气相沉积工艺、涂覆工艺、溶胶-凝胶工艺或其他工艺形成。
在缓冲层12上形成第一半导体21，分两步对第一半导体21进行离子注入处理，以形成第一掺杂部211、第二掺杂部212、沟道部213、第三掺杂部214以及第四掺杂部215。
其中，第一半导体21的材料为多晶硅。第一半导体21的厚度为400埃至600埃。第一掺杂部211和第四掺杂部215均为N型重掺杂。第二掺杂部212和第三掺杂部214均为N型轻掺杂。
在第一半导体上21和缓冲层12上沉积栅绝缘层13。在栅绝缘层13上形成栅极22。在栅极22和栅绝缘层13上形成层间绝缘层14。对层间绝缘层14进行图案化处理，以形成第一过孔14A。第一过孔14A贯穿层间绝缘层14并延伸至第一半导体21远离衬底基板10的一侧。在层间绝缘层14上形成输入电极23。输入电极23通过第一过孔14A与第一半导体21连接。
其中，栅绝缘层13以及层间绝缘层14的材料是氧化硅、氮化硅、氮氧化硅或者氧化硅/氮化硅（叠层）。栅极22的材料是银、铝、铜、钼、钼/铝/钼（叠层）或者钼/铜（叠层）。
103、在所述衬底基板上形成一感光元件，所述感光元件与所述开关元件相邻设置在所述衬底基板上，所述感光元件包括第二半导体和感光电极，所述第二半导体与所述第一半导体相连且同层设置，所述感光电极设置在所述第二半导体远离所述衬底基板的一侧，且与所述第二半导体连接。
具体的，第二半导体31可以在步骤102中与第一半导体21同时形成。在对第一半导体21进行离子注入时，可同时对第二半导体31进行离子注入，以形成N型轻掺杂的第二半导体31。
进一步的，在层间绝缘层14上形成平坦层18。对平坦层18进行图案化处理，以形成第二过孔18A。第二过孔18A贯穿平坦层18并暴露出层间绝缘层14远离衬底基板10的一侧。在平坦层18上形成钝化层41。对钝化层41进行图案化处理，以形成第三过孔41A。钝化层41覆盖第二过孔18A的内侧壁。在钝化层41伤沉积感光电极32。感光电极32通过第三过孔41A与第二半导体31连接。
其中，第二半导体31的材料为多晶硅。第二半导体31的厚度为400埃至600埃。感光电极32的材料为功函数高的导电材料，以便感光电极32和第二半导体31之间形成肖特基结。其中，功函数高的导电材料可以是氧化铟锌、氧化锌或者氧化铟镓锌。
请同时参阅图4和图6，图6是本申请提供的阵列基板的制作方法的第二流程示意图，具体步骤包括：
201、提供一衬底基板，在衬底基板上形成遮光层。
具体的，可对衬底基板10进行清洗以及预烘烤，以去除衬底基板10表面的油类、油脂等异物微粒。
然后，在衬底基板10上沉积不透光材料，再采用曝光蚀刻等方式将其图案化，形成一遮光层11。遮光层11部分覆盖衬底基板10。遮光层11包括遮光部24。
其中，衬底基板10可以为玻璃基板、石英基板、树脂基板、PI柔性基板或其他类型基板，在此不一一赘述。不透光材料可为钼、钛、钼/钛(叠层)或者钛/铝(叠层)。
202、在所述衬底基板和所述遮光层上形成缓冲层和半导体层。
具体的，在遮光层11上形成一缓冲层12。缓冲层12覆盖遮光层11和衬底基板10。
在缓冲层12上沉积非晶硅层，并对非晶硅层进行快速热退火或者激光镭射退火，以形成多晶硅层。对多晶硅层进行图案化处理，以形成半导体层15。半导体层15包括第一半导体21和第二半导体31。
其中，半导体层15的厚度为400埃至600埃。
203、对所述半导体层进行第一次离子注入。
具体的，采用离子注入的方式，对半导体层15进行磷离子掺杂。由此，在第一半导体21中形成第一掺杂部211和第四掺杂部215。第一掺杂部211和第四掺杂部215均为N型重掺杂。
204、在所述半导体层和所述缓冲层上形成栅绝缘层和栅极层，并采用自对准方式对所述半导体层进行第二次离子注入。
具体的，在半导体层15和缓冲层12上沉积栅绝缘层13。其中，栅绝缘层13可以是氧化硅层或氮化硅层，也可以是氧化硅和氮化硅的叠层结构。
在栅绝缘层13上沉积第一金属层，对第一金属层进行图案化处理，以形成栅极层16。栅极层16包括栅极22。其中，第一金属层的材料是银、铝、铜、钼、钼/铝/钼（叠层）或者钼/铜（叠层）。
以栅极层16作为遮挡层对半导体层15进行第二次离子注入。由此，在第一半导体21中形成第二掺杂部212和第三掺杂部214。第二掺杂部212和第三掺杂部214均为N型轻掺杂。同时，第二半导体31也可通过第二次离子注入成为N型半导体。
205、在所述栅极层和所述栅绝缘层上形成层间绝缘层，并对所述层间绝缘层进行图案化处理。
具体的，在栅极层16和栅绝缘层13上沉积层间绝缘层14。采用快速热退火工艺对层间绝缘层14进行氢化和活化，再采用曝光蚀刻等工艺对层间绝缘层14进行图案化处理，以形成多个第一过孔14A。第一过孔14A贯穿层间绝缘层14，并延伸至半导体层15远离衬底基板10的一侧。
206、在所述层间绝缘层上形成源漏电极层。
在层间绝缘层14上沉积第二金属层，对第二金属层进行图案化处理，以形成源漏电极层17。
其中，源漏电极层17包括源极图案171、漏极图案172、触控电极173、指纹信号电极174以及输入电极23。源极图案171和漏极图案172分别通过相应的第一过孔14A与半导体层15连接。输入电极23通过相应的第一过孔14A与第一半导体21连接。
207、在所述源漏电极层和所述层间绝缘层上形成平坦层，并对所述平坦层进行图案化处理。
具体的，在源漏电极层17和层间绝缘层14上形成平坦层18。对平坦层18进行图案化处理，以形成第二过孔18A、第四过孔18B、第五过孔18C以及第六过孔18D。第二过孔18A贯穿平坦层18，并暴露出层间绝缘层14远离衬底基板10的一侧。第四过孔18B暴露出指纹信号电极174远离衬底基板10的一侧。第五过孔18C暴露出漏极图案172远离衬底基板10的一侧。第六过孔18D暴露出触控电极173远离衬底基板10的一侧。
208、在所述平坦层上形成公共电极层。
具体的，在平坦层18上沉积第一透明金属层，对第一透明金属层进行图案化处理，以形成公共电极层19。
其中，公共电极层19包括触控走线191和第一电极192。触控电极173和触控走线191通过过孔连接以实现触控功能。
209、在所述公共电极层和所述平坦层上形成钝化层，并对所述钝化层进行图案化处理。
具体的，在公共电极层19和平坦层18上沉积钝化层41，并对钝化层41进行图案化处理，以形成第三过孔41A、第七过孔41B和第八过孔41C。第三过孔41A和第三过孔18A对应设置。且钝化层41覆盖第二过孔18A的内侧壁。第三过孔41A贯穿钝化层41，并延伸至第二半导体31远离衬底基板10的一侧。第七过孔41B与第四过孔18B对应设置，且钝化层41覆盖第四过孔18B的内侧壁。第八过孔41C对应第五过孔18C设置，且钝化层41覆盖第五过孔18C的内侧壁。
210、在所述钝化层上形成像素电极层。
具体的，在钝化层41上沉积第二透明金属层，并对第二透明金属层进行图案化处理，以形成像素电极层42。
其中，像素电极层42包括像素电极421、第二电极422、信号连接线423以及感光电极32。第一电极192和第二电极422分别构成存储电容的两个极板。感光电极32与信号连接线423连接，信号连接线423通过第七过孔41B与指纹信号电极174连接，以实现指纹信号的传输。像素电极421通过第八过孔41C与漏极图案172连接。触控电极173通过第六过孔18D与触控走线191连接，以实现触控功能。感光电极32通过第三过孔41A与第二半导体31连接。
在本申请实施例提供的阵列基板的制作方法中，开关元件20和感光元件30能够兼容LTPS制程，实现了屏内环境光技术的量产，同时具有肖特基结的感光元件30能够实现较强的光吸收光能力，提高了感光元件30的灵敏度。
需要说明的是，在本申请的描述中，“图案化”是指形成具有特定的图形结构的步骤，其可为光刻工艺，光刻工艺包括形成材料层、涂布光刻胶、曝光、显影、刻蚀、光刻胶剥离等步骤中的一步或多步，此为本技术领域的技术人员所理解的工艺制程，在此不再赘述。
相应的，本申请还提供一种显示面板，该显示面板包括以上任一实施例所述的阵列基板，具体可参阅以上内容，在此不再赘述。此外，本申请提供的显示面板可以是有机发光二极管显示面板、主动矩阵有机发光二极管显示面板、被动矩阵有机发光二极管显示面板、量子点有机发光二极管显示面板或者微发光二极管显示面板，本申请对此不作具体限定。
在本申请一实施例中，请参阅图7，图7是本申请提供的显示面板的结构示意图。本申请实施例提供的显示面板1000还包括GOA电路300和其他功能部件。开关元件和感光元件可与GOA电路300设置在同一区域，从而不影响显示面板1000的开口率。此外，本申请实施例中的GOA电路300和其他功能部件是本领域技术人员所熟知的相关技术，在此不再赘述。
在本申请另一实施例中，显示面板1000还包括虚拟像素区（图中未标示）。虚拟像素区位于GOA电路300和显示区VA之间。虚拟像素区不进行画面显示。开关元件20和感光元件30位于虚拟像素区，从而不影响显示面板的开口率，同时也可避免对GOA电路区的线路产生干扰。
本申请提供的显示面板包括阵列基板，所述阵列基板包括：衬底基板；开关元件，设置在所述衬底基板上，所述开关元件包括第一半导体，所述第一半导体设置在所述衬底基板上；以及感光元件，与所述开关元件相邻设置在所述衬底基板上，所述感光元件包括第二半导体和感光电极，所述第二半导体与所述第一半导体相连且同层设置，所述感光电极设置在所述第二半导体远离所述衬底基板的一侧，且与所述第二半导体连接；其中，第二半导体和感光电极之间形成肖特基结，增大了感光元件的有效光敏面积，从而提高了感光元件的灵敏度，进而提高了显示面板的品质。
以上对本申请提供的阵列基板、阵列基板的制作方法以及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其包括：
    衬底基板；
    开关元件，设置在所述衬底基板上，所述开关元件包括第一半导体，所述第一半导体设置在所述衬底基板上；以及
    感光元件，与所述开关元件相邻设置在所述衬底基板上，所述感光元件包括第二半导体和感光电极，所述第二半导体与所述第一半导体相连且同层设置，所述感光电极设置在所述第二半导体远离所述衬底基板的一侧，且与所述第二半导体连接；
    其中，所述感光电极与所述第二半导体形成肖特基结。
  2. 根据权利要求1所述的阵列基板，其中，所述第二半导体为本征型半导体或者N型半导体。
  3. 根据权利要求2所述的阵列基板，其中，所述第一半导体包括沿水平方向依次设置在所述衬底基板上的第一掺杂部、第二掺杂部、沟道部、第三掺杂部以及第四掺杂部，所述第四掺杂部和所述第二半导体连接；
    其中，所述第一掺杂部和所述第四掺杂部均为N型重掺杂，所述第二掺杂部、所述第三掺杂部以及所述第二半导体均为N型轻掺杂。
  4. 根据权利要求1所述的阵列基板，其中，所述开关元件还包括：
    栅极，设置在所述第一半导体远离所述衬底基板的一侧，且与所述第一半导体绝缘设置；以及
    输入电极，设置在所述第一半导体远离所述衬底基板的一侧，且与所述第一半导体远离所述第二半导体的一端连接。
  5. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括薄膜晶体管层，所述开关元件和所述感光元件均设置在所述薄膜晶体管层中。
  6. 根据权利要求5所述的阵列基板，其中，所述薄膜晶体管层包括：
    半导体层，设置在所述衬底基板上，所述半导体层包括所述第一半导体和所述第二半导体；
    栅绝缘层，设置在所述半导体层上；
    栅极层，设置在所述栅绝缘层上，所述栅极层包括所述栅极；
    层间绝缘层，设置在所述栅绝缘层和所述栅极层上，所述层间绝缘层具有第一过孔，所述第一过孔贯穿所述层间绝缘层并延伸至所述第一半导体远离所述衬底基板的一侧；以及
    源漏电极层，设置在所述层间绝缘层上，所述源漏电极层包括所述输入电极，所述输入电极通过所述第一过孔与所述第一半导体层连接。
  7. 根据权利要求6所述的阵列基板，其中，所述薄膜晶体管层还包括：
    平坦层，设置在所述源漏电极层和所述层间绝缘层上，所述平坦层具有第二过孔，所述第二过孔贯穿所述平坦层，并暴露出所述层间绝缘层远离所述衬底基板的一侧；
    公共电极层，设置在所述平坦层上；以及
    钝化层，设置在所述公共电极层和所述平坦层上，所述钝化层具有第三过孔，所述第三过孔贯穿所述钝化层，并通过所述第二过孔延伸至所述第二半导体远离所述衬底基板的一侧，所述第二过孔的孔径大于所述第三过孔的孔径，且所述钝化层覆盖所述第二过孔的内侧壁；
    其中，所述感光电极通过所述第三过孔与所述第二半导体连接。
  8. 根据权利要求7所述的阵列基板，其中，所述阵列基板还包括像素电极层，所述像素电极层设置在所述钝化层上；
    其中，所述感光电极和所述像素电极层同层设置。
  9. 根据权利要求8所述的阵列基板，其中，所述源漏电极层包括源极、漏极、触控电极以及指纹信号电极，所述公共电极层包括触控走线和第一电极，所述像素电极层包括像素电极、第二电极以及信号连接线。
  10. 根据权利要求9所述的阵列基板，其中，所述平坦层还具有第四过孔、第五过孔以及第六过孔，所述第四过孔暴露出所述指纹信号电极远离所述衬底基板的一侧，所述第五过孔暴露出所述漏极远离所述衬底基板的一侧，所述第六过孔暴露出所述触控电极远离所述衬底基板的一侧。
    所述钝化层还具有第七过孔和第八过孔，所述第七过孔与所述第四过孔对应设置，且所述钝化层覆盖所述第四过孔的内侧壁，所述第八过孔对应所述第五过孔设置，且所述钝化层覆盖所述第五过孔的内侧壁。
  11. 根据权利要求10所述的阵列基板，其中，所述感光电极与所述信号连接线连接，所述信号连接线通过所述第七过孔与所述指纹信号电极连接；所述像素电极通过所述第八过孔与所述漏极连接；所述触控电极通过所述第六过孔与所述触控走线连接。
  12. 根据权利要求5所述的阵列基板，其中，所述阵列基板具有显示区和虚拟像素区，所述虚拟像素区至少位于所述显示区的一侧，所述开关元件和所述感光元件均位于所述虚拟像素区。
  13. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括遮光部，所述遮光部设置在所述衬底基板靠近所述第一半导体的一侧，且所述遮光部在所述衬底基板上的投影至少覆盖所述第一半导体在所述衬底基板上的投影。
  14. 根据权利要求13所述的阵列基板，其中，所述遮光部在所述衬底基板上的投影覆盖所述第一半导体在所述衬底基板上的投影以及所述第二半导体在所述衬底基板上的投影。
  15. 根据权利要求1所述的阵列基板，其中，所述感光电极的材料为氧化铟锌、氧化锌或者氧化铟镓锌。
  16. 根据权利要求1所述的阵列基板，其中，所述第一半导体和所述第二半导体的材料均为多晶硅。
  17. 根据权利要求16所述的阵列基板，其中，所述第二半导体的厚度为400埃至600埃。
  18. 一种显示面板，其包括阵列基板，所述阵列基板包括：
    衬底基板；
    开关元件，设置在所述衬底基板上，所述开关元件包括第一半导体，所述第一半导体设置在所述衬底基板上；以及
    感光元件，与所述开关元件相邻设置在所述衬底基板上，所述感光元件包括第二半导体和感光电极，所述第二半导体与所述第一半导体相连且同层设置，所述感光电极设置在所述第二半导体远离所述衬底基板的一侧，且与所述第二半导体连接；
    其中，所述感光电极与所述第二半导体形成肖特基结。
  19. 根据权利要求18所述的显示面板，其中，所述第二半导体为本征型半导体或者N型半导体。
  20. 根据权利要求18所述的显示面板，其中，所述感光电极的材料为氧化铟锌、氧化锌或者氧化铟镓锌。
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