CN101577285A - 影像显示系统及其制造方法 - Google Patents

影像显示系统及其制造方法 Download PDF

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CN101577285A
CN101577285A CNA2009101356046A CN200910135604A CN101577285A CN 101577285 A CN101577285 A CN 101577285A CN A2009101356046 A CNA2009101356046 A CN A2009101356046A CN 200910135604 A CN200910135604 A CN 200910135604A CN 101577285 A CN101577285 A CN 101577285A
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photo
image display
display system
film transistor
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勒米殊·卡卡德
佐野景一
薛富元
刘驰中
张圣文
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TPO Displays Corp
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Toppoly Optoelectronics Corp
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Abstract

本发明公开了一种影像显示系统及其制造方法。该影像显示系统包括薄膜晶体管阵列基板。上述薄膜晶体管阵列基板包括具有由多个薄膜晶体管所组成的阵列的基板；以及至少一感光元件，设置于该基板上，其中该感光元件包括非晶硅膜层且具有垂直于该基板的电流方向。

Description

影像显示系统及其制造方法
技术领域
本发明涉及包括薄膜晶体管液晶显示装置(thin film transistor liquidcrystal display，TFT-LCD)的影像显示系统，且特别是涉及一种薄膜晶体管阵列基板(thin film transistor array substrate)及其制造方法，其内设置有含非晶硅膜层的至少一感光元件(light-sensing element)。
背景技术
液晶显示装置(liquid crystal display，LCD)一般包括有下部基板、上部基板与夹置于其间的液晶层。上部基板通常包括彩色滤光片(color filter)与共同电极(common electrode)，而下部基板即为已知的薄膜晶体管阵列基板(thinfilm transistor array substrate，下称TFT阵列基板)。为于液晶显示装置中提供如环境光感测、触控感测与影像感测等其它功能，便需于其内的TFT阵列基板上设置感光元件。
图1显示了已知液晶显示装置中所应用的TFT阵列基板10，其内设置有感光元件。在此，TFT阵列基板10包括透明基板12以及形成于其上的选择性缓冲层14。于TFT阵列基板上10定义有驱动电路区(driver region)40以及像素区(pixel region)50。于TFT阵列基板10的驱动电路区40内形成有n型薄膜晶体管(n-type TFT，下称n型TFT)60、p型薄膜晶体管(p-type TFT，下称p型TFT)70以及感光元件(light-sensing element)80，而于TFT阵列基板10的像素区50内则形成有n型TFT 85以及储存电容器(storage capacitor)90。
于驱动电路区40内的感光装置80则包括了横向地连接的p型掺杂区16D、非掺杂区(non-doped region)16A、n型掺杂区16C以及另一n型掺杂区16B，进而形成PINN型感光二极管(photodiode)。另外，导电接触物24形成并穿过了层间介电层20与栅介电层18而实体接触了p型掺杂区16D与n型掺杂区16B。而感光装置80内形成于位于层间介电层20上的透明导电层30则作为栅电极之用，以调整通过上述PIN-N型感光二极管的电流。上述透明导电层30亦使得环境光可抵达PIN-N型感光二极管处。感光装置80的设置使得显示装置具备了如环境光感测、触控感测以及影像感测等额外功能。
虽然于图1内显示了感光装置80于驱动电路区40的设置情形，然而其可视所需功能而定而可设置于驱动电路区40或像素区50内。对于节能需求而言，可将感光装置设置于驱动电路区40之内，而对于影像感测或光学触控感测等需求而言，可将感光装置80设置于像素区50内。感光装置80以及这些TFT 60、70与85等可应用已知显示装置的制作而同时形成于TFT阵列基板10上。然而，上述制作仍存在有缺点。举例来说，当将感光装置80设置于像素区50内以提供如触控感测或影像感测等功能时，其将占据了像素区内的部分区域而因此降低了像素透光区域或开口率(aperture ratio)。此外，当n型TFT 60与85的有源层(active layer)采用低温多晶硅膜层时，p型TFT 70与PIN-N结构的感光装置80其亦将采用此低温多晶硅膜层。由于多晶硅膜层的感光度(photosensitivity)极差，且其于显示器背光(backlight)存在情形下对于环境光的感测度将更为降低。而非晶硅膜层的感光度远优于多晶硅膜层的感光度，因此采用了非晶硅感光膜层为优选选择。然而，随着使用时间的增加而其内非晶硅膜层感测度的劣化亦为上述结构所遭遇的问题之一。由于上述感光装置80采用感光二极管结构(或称光TFT)，其具有水平于透明基板12的电流方向而具有极高的电流密度。在此，电流密度值主要关于所应用的有源层的厚度。因此，由于非晶硅内的硅-氢键结在高电流密度下容易断键而恐随着使用时间的延长而造成感光度的显著下降，故对于非晶硅TFT感光元件而言可靠度问题为其一大考验。
有鉴于此，便需要适用于显示装置的一种TFT阵列基板，以于其内应用有优选感光装置，藉以满足高感光率以及高可靠度的需求，且不会对于TFT阵列基板的制作造成额外工艺步骤的增加。
发明内容
本发明提供了一种影像感测装置及其制造方法。
依据实施例，本发明的影像感测装置包括：
薄膜晶体管阵列基板，其包括具有由多个薄膜晶体管所组成的阵列的基板；以及至少一感光元件，设置于该基板上，其中该感光元件包括非晶硅膜层且具有垂直于该基板的电流方向。
依据另一实施例，本发明的影像感测装置的制造方法，包括：
提供具有薄膜晶体管阵列的基板；于该基板上形成底电极；于该底电极上形成包括非晶硅膜层的感光元件；以及形成顶电极于该感光元件之上。
为了让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举优选实施例，并配合附图，作详细说明如下：
附图说明
图1为示意图，显示了用于显示装置的已知薄膜晶体管(TFT)阵列基板；
图2、3、4、5为一系列示意图，分别显示了于本发明实施例的薄膜晶体管阵列基板的制作过程中的剖面情形；
图6为依据本发明另一实施例的薄膜晶体管阵列基板；
图7为依据本发明又一实施例的薄膜晶体管阵列基板；
图8为依据本发明另一实施例的薄膜晶体管阵列基板；
图9为依据本发明又一实施例的薄膜晶体管阵列基板；
图10为依据本发明另一实施例的薄膜晶体管阵列基板；
图11为依据本发明又一实施例的薄膜晶体管阵列基板；
图12为依据本发明另一实施例的薄膜晶体管阵列基板；
图13为依据本发明又一实施例的薄膜晶体管阵列基板；以及
图14显示了影像显示系统的示意图，其包括本发明的薄膜晶体管阵列基板。
附图标记说明
10～TFT阵列基板；        12～透明基板；
14～缓冲层；             16A～非掺杂区；
16B、16C～n型掺杂区；    16D～p型掺杂区；
18～栅介电层；           20～层间介电层；
24～导电接触物；         30～透明导电层；
40～驱动电路区；         50～像素区；
60、85～n型薄膜晶体管；  70～p型薄膜晶体管；
80～感光元件；           90～储存电容器；
100～TFT阵列基板；       102～透明基板；
104～透明基板；          106A～沟道区；
106B、106D～源极/漏极区；106C～轻掺杂源极/漏极区；
108～栅绝缘层；          110A、110B～栅电极；
110C～第二电极；         112～层间介电层；
114、116、118～导电构件；122、122’～第一膜层；
124、124’～第二膜层；   126～第三膜层；
128～平坦层/保护层；     130、130’～感光元件；
132、134～开口；         136～像素电极；
136A～顶电极；           140～驱动电路区；
150～像素区；            160、180～n型TFT；
170～p型TFT；            190～储存电容器；
195～感光装置；          300～显示面板；
400～输入装置；          500～感光装置；
OP1、OP2～接触孔。
具体实施方式
于下文中，“覆盖基板”、“于膜层之上”或“位于膜层上”等描述仅显示了相较于基础膜层表面的相对位置关系而无论中间膜层的存在情形。因此，这些描述可能不仅显示了膜层的直接接触情形，而可能更显示一或多个层叠膜层之间的非接触情形。
本发明提供了新颖的影像显示系统的制造方法。本发明的影像显示系统具有薄膜晶体管阵列基板(下称TFT阵列基板)，其上设置有至少一感光元件。TFT阵列基板的制作请参照图2-5的示意图。图6-11则显示了于其它实施例中的TFT阵列基板的实施情形。为了简化附图，在上述附图中仅绘示了多个薄膜晶体管的制作情形。
请参照图2，TFT阵列基板100包括驱动电路区140以及像素区150，其上包括选择性缓冲层104形成于透明基板102。一般而言，缓冲层104可包括如氧化硅、氮化硅或上述材料组合的材料，且亦可为由氧化硅与氮化硅等材料所形成的叠层结构，而透明基板102则可包括如玻璃、塑胶或陶瓷基板的透明绝缘材料或如金属或金属合金的不透明材料。塑胶基板则可包括由至少聚乙烯对苯二甲酯(polyethyleneterephthalate)、聚酯(polyester)、聚碳酸酯(polycarbonates)、聚丙烯酸酯(polyacrylates)或是聚苯乙烯(polystyrene)其中之一所形成的一个或多个材料膜层。
请参照图2，在TFT阵列基板100上形成有多个电子元件，如位于驱动电路区140内的n型TFT 160与p型TFT 170以及位于像素区150内的n型TFT 180与储存电容器190。上述电子元件顺应地为层间介电层112所覆盖，而层间介电层112的材料则包括绝缘氧化物、氮化物或上述绝缘材料的组合。适当的绝缘材料例如为氮化硅及氧化硅。
于图2中，驱动电路区140内的n型TFT 160与像素区150内的n型TFT 180皆包括由一对n型掺杂半导体层所构成的源极/漏极区106B、由本征(intrinsic)半导体层所形成且位于源极/漏极区106B间的沟道区106A、由n型掺杂半导体层所形成且位于沟道区106A与源极/漏极区106B间的一对轻掺杂源极/漏极区106C(LDD区)、覆盖源极/漏极区106B与沟道区106A以及LDD区106C的如氧化硅膜层的栅绝缘层108以及位于栅绝缘层108上的栅电极110A。
另外，位于驱动电路区140内的p型TFT 170则包括由p型掺杂半导体层所形成的一对源极/漏极区106D、由本征半导体层所形成且位于源极/漏极区106D间的沟道区106A、覆盖源极/漏极区106D与沟道区106A的如氧化硅膜层的栅绝缘层108以及位于栅绝缘层108上的栅电极110B。
再者，形成于像素区150内的储存电容器190则包括n型TFT 180的源极/漏极区106B一部分的n型掺杂半导体层的第一电极。第一电极为栅绝缘层108所覆盖，而第二电极110C形成于第一电极上，而其间的栅绝缘层108部分则作为储存电容器190的储存区域。
位于基板102上如n型TFT 160与180、p型TFT 170与储存电容器190等电子装置，其可采用已知TFT工艺与储存电容器工艺所形成，故不在此进一步描述其制造情形以简化附图。上述有源层可包括多晶硅(polysilicon)、非晶硅(amorphous silicon)、微晶硅(microcrystalline silicon)、氧化锌(zinc oxide)或金属氧化物半导体(metal oxide semiconductor)等材料。
接着，请参照图3，形成具有开口的阻剂层(未显示)于层间介电层112之上。接着采用此阻剂层作为掩模而蚀刻层间介电层112，形成多个接触孔OP1以及多个接触孔OP2，以分别露出位于驱动电路区140与位于像素区150之内源极/漏极区106B/106D及栅极110A与110B。蚀刻层间介电层112的工艺可包括湿蚀刻或干蚀刻工艺。于形成接触孔OP1与OP2之后接着移除阻剂层。
接着，在层间介电层112之上形成如金属层的导电层(未显示)，并使之填入于这些接触孔OP1与OP2之内。接着通过已知光刻与蚀刻工艺(未显示)图案化导电层以进而形成导电构件114与116，其分别包括形成于接触孔OP1/OP2内的插拴部以及形成于层间介电层112上邻近于接触孔OP1/OP2的导线部。在此，在像素区150内的覆盖储存电容器190的层间介电层112上则同时形成了导电构件118。
请参照图4，接着于像素区150内导电构件118上形成感光元件130。感光元件130绘示为包括了依序堆叠于导电构件118上的第一膜层122、第二膜层124与第三膜层126的三膜层复合结构。第一膜层122、第二膜层124与第三膜层126可形成有NIP或PIN结构，其中N代表n型硅层、I代表未掺杂的非晶硅层，而P代表p型硅层。第一膜层122、第二膜层124以及第三膜层126的制作可通过依序施行三个硅膜层的沉积后接着选择性的蚀刻这些膜层而形成感光元件130。第一膜层122与第三膜层126的掺杂可于其沉积时原位地(in-situ)达成，或可于其沉积之后通过额外的离子布值工艺并搭配适当的掺质而形成。于形成感光元件130之后，接着形成平坦层或保护层128，其材料例如为氮化硅或聚亚酰胺，以覆盖n型TFT 160与180、p型TFT 170、储存电容器190以及感光元件130。
请参照图5，接着于像素区150内平坦层128形成开口132与134，以分别露出感光元件130与n型TFT 180的导电构件114。接着沉积透明导电层(未显示)并图案化此透明导电层以分别形成像素电极136与顶电极136A。像素电极136与顶电极136A分别顺应地填入于开口134与132内，而接触n型TFT 180中所露出的导电构件114与感光元件130顶面。上述透明导电层可包括铟锡氧化物(ITO)、铟锌氧化物(IZO)、铝锌氧化物(AZO)或氧化锌(ZnO)或其它材料或上述材料的组合。依据不同的实施例需求，透明导电层可通过如溅镀、电子束蒸镀、热蒸镀或化学气相沉积工艺所形成。
如图5所示，覆盖感光元件130的顶电极136A、感光元件130以及导电构件118(作为底电极之用)形成了感光装置195，其适用于如环境光感测、触控感测、影像感测、发电及/或显示装置中像素中存储单元装置(memory-in-pixel)等应用。
如图5所示的TFT阵列基板100具有以下优点。由于感光装置195形成于位于储存电容器190上，因此像素区150的开口率并不会因此缩减。再者，由于感光装置195具有堆叠结构，因而具有垂直于TFT阵列基板100的电流方向，进而提供了具有较低电流密度且较为可靠的感光装置195。再者，由于感光装置195的感光元件130由非晶硅材料次膜层所形成，故其感光元件的感光率相较于采用多晶硅材料的感光元件可更为增加，且于当TFT 160、170与180采用低温多晶硅工艺所形成时亦不会受到影响。此外，感光元件130可通过不透光的导电构件118与110C而遮蔽来自于显示器的背光，因此来自于感光层的感光信号皆由环境光所产生。如此有助于改善于如触控感测与环境光感测等应用时的感光准确度。而于如太阳能电池的应用方面，则可采用更为薄化或采用透明材料的电极118与110C，以允许光子自背光处抵达感光元件130以更增加来自于背光的能量产生。于其它实施例中，感光元件亦可形成于像素区内不位于储存电容器上的其它位置。而于此实施例中，虽然开口率会受到影响，但仍可保留前述的所有优点。
图6显示依据另一实施例的TFT阵列基板100的剖面图。于本实施例中，感光装置195包括双膜层结构的感光元件130’，其包括依序形成于导电构件118上的第一膜层122’与第二膜层124’堆叠结构。第一膜层122’与第二膜层124’可为堆叠的NI、IN、PI或IP结构，其中N代表n型硅膜层，I代表未经掺杂的非晶硅膜层，而P代表p型硅膜层。
图7显示依据另一实施例的TFT阵列基板100。于本实施例中，感光装置195设置于驱动电路区140内。在此，感光装置195具有相似于图5所示的结构且位于层间介电层112之上。
于上述图2-7内所示薄膜晶体管绘示为具有顶部栅极结构(top gatestructure)的薄膜晶体管，但并不以上述实施情形加以限制本发明。于图2-7内所示的薄膜晶体管亦可部分或全部替代为具有底部栅极结构(bottom gate)的薄膜晶体管。请参照图8与图9，显示具有底栅极结构的TFT阵列基板的实施例。于本些实施例中，感光装置195具有相似于图6与图7所示的结构且设置于栅绝缘层108上。如图8所示，TFT阵列基板100的感光装置195形成于像素区150内。如图9所示，感光装置195亦可形成于驱动电路区140内。于图8与图9内所示的薄膜晶体管160、170与180以及感光装置195内的构件采用形同于图6与图7所示情形的相同标号。
如图8与图9所示的具有底部电极结构的薄膜晶体管160、170与180的薄膜晶体管阵列基板100的制作如下所述：
形成薄膜晶体管160、170与180的栅极(如栅电极110A/110B/110C)于基板102上。形成第一介电层(如栅绝缘层108)于栅极上。形成包括源极/漏极层(如源极/漏极区106B/106D)的有源层(由沟道区106A与106B/106D所组成的膜层)于第一介电层上。形成第一导电层(未显示)于有源层与第一介电层上并图案化此导电层以形成底电极(如底电极118)以及接触该源极/漏极区的源极/漏极电极(如源极/漏极电极114)。接着形成感光元件(如感光元件130)于底电极上。形成第二介电层(如保护层128)于第一介电层与感光元件上。形成第一开口(如开口132)与第二开口(如开口134)于第二介电层内，露出源极/漏极电极与感光元件。形成第二导电层于第二介电层上与第二开口与第三开口内并图案化此第二导电层以形成顶电极(如顶电极136A)以及接触源极/漏极电极的像素电极(如像素电极136)。
于其它实施例中，则可形成多个电性上相串联或相并联的感光装置195于TFT阵列基板100的像素区150及/或驱动电路区140内。如图10所示，显示相串联的两感光装置195的剖面情形。这些感光装置195形成于像素区150内，而于保护层128内则形成有多个开口132A，以分别露出感光装置195的底电极118。于保护层128上形成有多个顶电极136，其与前一感光装置195的顶电极118相连接。如图11所示，亦可采用并联方式相连接两感光装置195，其分别连接其底电极与顶电极。对于如感光、触控感测以及环境光感测等应用方面，前述的感光装置195经串联后且随着相连接的感光装置195数量的增加有助于降低其暗电流(dark current)且可保持个别的感光元件所提供的一定光电流量，进而改善其感光率。而于如太阳能电池或像素中存储单元结构等应用方面，前述感光装置195经串联后且随着相连接的感光装置195数量的增加亦有助于开启电压的增加。经并联的感光装置则可增加光电流且维持开起电压的一定值。并联连接的感光装置所具有的较高光电流值对于如太阳能电池以及感光方面应用极为有用。
图12为俯视示意图，显示了如图5、6与图8所示的TFT阵列基板110，其具有形成于像素区150内的感光装置195。图13则为俯视示意图，显示了如图7与图9所示的TFT阵列基板100，其具有形成于驱动电路区140内的感光装置。同样地，如图12与图13所示的TFT阵列基板100上可形成有一或多个感光装置195。
图14绘示了影像显示系统，其包括了显示面板300与电子装置500。如图14所示，显示面板300包括了TFT阵列基板，例如图5、6、7、8与图9所示的TFT阵列基板100。显示面板300适用于多种电子装置的应用。
一般而言，电子装置500通常包括有显示面板300与输入装置400。再者，输入装置400可与影像显示装置300耦接，以提供适当的信号(例如影像信号)至影像显示面板300以产生影像。电子装置500例如为移动电话、数字相机、个人数字助理(PDA)、笔记型电脑、桌上型电脑、电视、车用显示器、携带型DVD播放器、全球定位系统、数字相框或导航荧幕等电子装置。
虽然本发明已以优选实施例披露如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的为准。

Claims (15)

1.一种影像显示系统，包括：
薄膜晶体管阵列基板，包括：
基板，具有由多个薄膜晶体管所组成的阵列；以及
至少一感光元件，设置于该基板上，其中该感光元件包括非晶硅膜
层且具有垂直于该基板的电流方向。
2.如权利要求1所述的影像显示系统，其中该感光元件为NI、IN、PI、IP、NIP或PIN的堆叠结构，N代表n型硅层，I代表未经掺杂的非晶硅层，而P代表p型硅层。
3.如权利要求1所述的影像显示系统，还包括设置于该感光元件下方的底电极以及设置于该感光元件上方的顶电极。
4.如权利要求3所述的影像显示系统，其中该顶电极包括透明导电材料。
5.如权利要求1所述的影像显示系统，其中该薄膜晶体管包括由微晶硅、非晶硅、多晶硅、氧化锌或金属氧化物半导体材料所形成的有源层。
6.如权利要求1所述的影像显示系统，其中该薄膜晶体管具有顶栅极结构或底栅极结构。
7.如权利要求1所述的影像显示系统，其中该基板上包括像素区与驱动电路区，而该至少一感光元件位于该像素区内、该驱动电路区内或该像素区与该驱动电路区内。
8.如权利要求7所述的影像显示系统，还包括储存电容器位于该像素区内，其中该至少一感光元件位于该储存电容器的上方。
9.如权利要求1所述的影像显示系统，还包括多个感光元件，其中多个感光元件电性上相串联或相并联。
10.如权利要求1所述的影像显示系统，还包括显示面板，其中该薄膜晶体管阵列基板为该显示面板的一部分。
11.如权利要求10所述的影像显示系统，还包括电子装置，其中该电子装置包括：
该显示面板；以及
输入装置，耦接于该显示面板以于操作时输入信号至该显示面板并使得该显示面板产生影像。
12.如权利要求11所述的影像显示系统，其中该电子装置为移动电话、数字相机、个人数字助理、笔记型电脑、桌上型电脑、电视、车用显示器、携带型DVD播放器、全球定位系统、数字相框或导航荧幕。
13.一种影像显示系统的制造方法，包括：
提供具有薄膜晶体管阵列的基板；
于该基板上形成底电极；
于该底电极上形成包括非晶硅膜层的感光元件；以及
形成顶电极于该感光元件之上。
14.如权利要求13所述的影像显示系统的制造方法，还包括：
形成包括源极/漏极区的有源层于该基板之上；
形成栅绝缘层于该有源层之上；
形成栅极于该栅绝缘层之上，其中该有源层、该栅绝缘层与该栅极形成了具有顶栅极结构的薄膜晶体管；
形成第一介电层于该薄膜晶体管之上；
形成接触孔于该第一介电层内，露出该薄膜晶体管的源极/漏极区；
形成第一导电层于该第一介电层与该接触孔之上；以及
图案化该导电层，以形成该底电极以及接触该源极/漏极区的源极/漏极电极。
15.如权利要求13所述的影像显示系统的制造方法，还包括：
形成栅极于该基板之上；
形成第一介电层于该栅极之上；
形成包括源极/漏极层的有源层于该第一介电层上；
形成第一导电层于该有源层与该第一介电层之上；
图案化该导电层以形成该底电极以及接触该源极/漏极区的源极/漏极电极；
形成第二介电层于该第一介电层之上；
形成第一开口与第二开口于该第二介电层内，露出该源极/漏极电极与该感光元件；
形成第二导电层于该第二介电层上与该第一开口与该第二开口内；以及
图案化该第二导电层以形成该顶电极以及接触该源极/漏极电极的像素电极。
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