WO2014169543A1 - 阵列基板、制备方法以及液晶显示装置 - Google Patents

阵列基板、制备方法以及液晶显示装置 Download PDF

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Publication number
WO2014169543A1
WO2014169543A1 PCT/CN2013/080063 CN2013080063W WO2014169543A1 WO 2014169543 A1 WO2014169543 A1 WO 2014169543A1 CN 2013080063 W CN2013080063 W CN 2013080063W WO 2014169543 A1 WO2014169543 A1 WO 2014169543A1
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Prior art keywords
electrode
pixel
substrate
drain electrode
passivation layer
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PCT/CN2013/080063
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English (en)
French (fr)
Inventor
赵海廷
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合肥京东方光电科技有限公司
京东方科技集团股份有限公司
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Priority to US14/379,818 priority Critical patent/US9671655B2/en
Publication of WO2014169543A1 publication Critical patent/WO2014169543A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a liquid crystal display device. Background technique
  • a liquid crystal display device is one of flat panel display devices.
  • the main component of the liquid crystal display device is a liquid crystal panel.
  • the liquid crystal panel mainly includes a color filter substrate and an array substrate, and the liquid crystal substrate and the array substrate are filled with liquid crystal.
  • An electrode for generating an electric field is further disposed in the array substrate or the color filter substrate, and the structural arrangement of the electrodes can determine the deflection of the liquid crystal, thereby affecting the display of the liquid crystal panel.
  • the liquid crystal panel has a plurality of pixel points (generally including RGB three sub-pixel units); in the imaging process, each pixel point is controlled by a thin film transistor (called a TFT) prepared in the array substrate to realize active driving, Thereby achieving image display.
  • a TFT thin film transistor
  • the thin film transistor is the key to realize the display of the LCD display device, which is directly related to the development direction of the high performance flat panel display device.
  • the ADS type array substrate usually includes two layers of electrodes on the same side of the liquid crystal cell, one of which is a slit electrode and the other of which is a plate electrode.
  • the electric field generated between the edge of the slit electrode and the plate electrode layer and the electric field generated between the slit electrodes form a multi-dimensional electric field, so that liquid crystal molecules in the liquid crystal cell can be deflected, thereby improving the working efficiency of the liquid crystal and increasing The perspective.
  • the advanced super-dimensional field conversion technology can increase the aperture ratio of the pixel, thereby improving the brightness, reducing the power consumption, improving the quality level of the liquid crystal display panel, and improving the picture quality of the TFT-LCD product.
  • the electrode in the lower layer of the sub-pixel unit is a plate-shaped common electrode, and the electrode of the upper layer is a slit-shaped pixel electrode; in the high aperture ratio ADS (High aperture ADS, the tube is called H
  • the lower electrode of the sub-pixel unit is a plate-shaped pixel electrode, the pixel electrode is connected to the drain electrode of the TFT, and the upper electrode is a slit-shaped common electrode.
  • an embodiment of the present invention provides an array substrate, a preparation method, and a liquid crystal display device.
  • the signal of the pixel electrode or the drain electrode in the inner layer is directly led to the uppermost layer of the sub-pixel unit by using the test electrode. It is very convenient to test the electrical performance of the TFT, and solve the problem that the original design TFT electrical performance is difficult to measure.
  • an array substrate includes a substrate and a plurality of sub-pixel units disposed on the substrate, the sub-pixel unit including a thin film transistor, a pixel electrode, a common electrode, and a passivation layer, the film
  • the transistor includes an active layer on both sides of the active layer, the drain electrode extending over the gate insulating layer to overlap the pixel electrode, or the drain electrode extending above the pixel electrode to overlap the pixel electrode.
  • the test electrode is made of the same material as the common electrode, and is formed by at least one of indium gallium oxide, indium oxide, indium tin oxide, and indium gallium tin oxide.
  • test electrode is included in each sub-pixel unit of the array substrate; or: one of the N sub-pixel units is included in each of the N adjacent sub-pixel units.
  • Test electrode wherein N is a positive integer greater than or equal to 2.
  • a liquid crystal display device comprising the above array substrate is provided.
  • a method of fabricating an array substrate comprising: forming a thin film transistor, a pixel electrode, a common electrode, and a passivation layer on a substrate, the thin film transistor including an active layer, a gate electrode, and a source An electrode and a drain electrode, the passivation layer being formed over the source electrode, the drain electrode, and the pixel electrode; forming a via hole in the passivation layer over the drain electrode; and forming from the embodiment according to the present invention , the preparation method comprises:
  • Step S1 forming a pattern including a gate electrode on the substrate;
  • Step S2 forming a gate insulating layer pattern on the substrate on which the step S1 is completed;
  • Step S3 forming a pattern including an active layer on the substrate on which step S2 is completed;
  • Step S4 forming a pattern including a pixel electrode on the substrate on which step S3 is completed, and forming a pattern including a source electrode and a drain electrode, the pixel electrode being electrically connected to the drain electrode;
  • Step S5 forming a passivation layer pattern on the substrate on which step S4 is completed, the passivation layer pattern covers the source electrode, the drain electrode and the pixel electrode, and a via hole is formed in the passivation layer above the drain electrode;
  • Step S6 forming a pattern including a common electrode and a test electrode on the substrate on which step S5 is completed.
  • the step S1 comprises: forming a metal film on the substrate, and forming a pattern including a gate electrode and a gate line by a patterning process, the gate line being connected to the gate electrode.
  • the step S2 comprises: forming a gate insulating film on the substrate on which the step S1 is completed, and forming a gate insulating layer pattern by one patterning process.
  • the step S3 includes: forming an active layer film on the substrate on which the step S2 is completed, forming a pattern including an active layer by a patterning process, wherein the active layer is located on the gate insulating layer The position of the gate electrode.
  • the step S4 includes: Step S41: forming a pixel electrode film on the substrate on which the step S3 is completed, forming a pattern including a pixel electrode by a patterning process, the pixel electrode being located in the gate insulating layer a region on which the active layer is not formed; Step S42: forming a metal thin film on the substrate on which step S41 is completed, and forming a pattern including a source electrode, a drain electrode, and a data line by a patterning process, the source electrode and the drain electrode Located on two sides above the active layer, the source electrode is connected to the data line, and the drain electrode extends above the pixel electrode to overlap the pixel electrode.
  • the step S4 includes:
  • Step S41 forming a metal thin film on the substrate on which the step S3 is completed, forming a pattern including a source electrode, a drain electrode, and a data line by a patterning process, the source electrode and the drain electrode being located on both sides of the active layer, The source electrode is connected to the data line, and the drain electrode extends to the gate insulating layer;
  • Step S42 forming a pixel electrode film on the substrate on which step S41 is completed, forming a pattern including a pixel electrode by one patterning process, the pixel electrode not being formed on the gate insulating layer In the region having the active layer, the pixel electrode overlaps with a drain electrode extending over the gate insulating layer.
  • the step S5 includes: forming a passivation layer film on the substrate on which the step S4 is completed, forming a passivation layer pattern by one patterning process, the passivation layer pattern covering the source electrode and the A drain electrode and the pixel electrode are described, and a via hole is formed in the passivation layer above the drain electrode.
  • the step S6 includes: forming a common electrode film on the substrate on which the step S5 is completed, and forming a pattern including a common electrode and a test electrode over the passivation layer by one patterning process, the test An electrode passes through the via from an upper surface of the drain electrode and protrudes from a surface of the passivation layer, and the test electrode is insulated from the common electrode.
  • Embodiment 1 is a schematic plan view of an array substrate in Embodiment 1 of the present invention.
  • 2A-2F and 3A-3F are a plan view showing a flow of preparation of the array substrate of Fig. 1 and a cross-sectional view taken along line A-A' of Fig. 1;
  • 2A is a schematic plan view showing formation of a gate electrode and a gate line
  • Figure 3A is a cross-sectional view corresponding to Figure 2A;
  • 2B is a schematic plan view showing formation of a gate insulating layer and an active layer
  • Figure 3B is a cross-sectional view corresponding to Figure 2B;
  • 2C is a schematic plan view showing formation of a pixel electrode
  • Figure 3C is a cross-sectional view corresponding to Figure 2C;
  • 2D is a schematic plan view showing formation of a source electrode and a drain electrode
  • Figure 3D is a cross-sectional view corresponding to Figure 2D;
  • 2E is a schematic plan view showing formation of a passivation layer and via holes therein;
  • Figure 3E is a cross-sectional view corresponding to Figure 2E;
  • 2F is a schematic plan view showing the formation of a common electrode and a test electrode
  • Fig. 3F is a cross-sectional view corresponding to Fig. 2F.
  • 10 substrate
  • 11 gate electrode
  • 12 gate line
  • 21 gate insulating layer
  • 22 active layer
  • 31-pixel electrode 41-data line
  • 42-source electrode 41-drain electrode
  • - passivation layer 52 - via
  • 61 - common electrode 62 - test electrode.
  • An array substrate includes a substrate and a plurality of sub-pixel units disposed on the substrate, the sub-pixel unit including a thin film transistor, a pixel electrode, a common electrode, and a passivation layer, the thin film transistor
  • the active layer, the gate electrode, the source electrode and the drain electrode are electrically connected to the pixel electrode
  • the passivation layer covers the source electrode, the drain electrode and the pixel electrode
  • the sub-pixel unit further includes a test electrode electrically connected to the pixel electrode and exposed on a surface of the sub-pixel unit.
  • the substrate may be a glass substrate, a quartz substrate, a plastic substrate, or the like.
  • a liquid crystal display device includes the above array substrate.
  • a method of fabricating an array substrate according to an embodiment of the present invention includes the steps of forming a thin film transistor, a pixel electrode, a common electrode, and a passivation layer on a substrate, the thin film transistor including an active layer, a gate electrode, a source electrode, and a drain a passivation layer formed over the source electrode, the drain electrode, and the pixel electrode; a via hole formed in the passivation layer above the drain electrode; and forming a via hole from the upper surface of the drain electrode And protruding from the test electrode on the surface of the passivation layer.
  • a via hole is formed in a passivation layer above a drain electrode of a thin film transistor and a test electrode is disposed, and a signal of a pixel electrode or a drain electrode in an inner layer is directly led to an uppermost layer of the sub-pixel unit, It is convenient to test the electrical properties of the TFT; the liquid crystal display device using the array substrate also has the same effect.
  • the embodiment provides an array substrate, including a substrate and a plurality of sub-pixel units disposed on the substrate, the sub-pixel unit including a thin film transistor, a pixel electrode, a common electrode, and a passivation layer, wherein the thin film transistor includes a source layer, a gate electrode, a source electrode and a drain electrode, the drain electrode being electrically connected to the pixel electrode, the passivation layer covering the source electrode, the drain electrode and the pixel electrode, wherein the sub-pixel unit further comprises The pixel electrode is electrically connected and the test electrode is exposed on the surface of the sub-pixel unit.
  • the gate electrode 11, the active layer 22, the pixel electrode 31, the source electrode 42 and the drain electrode 43, the passivation layer 51, and the common electrode 61 are laminated in this order.
  • a pass hole 52 is formed in a region of the passivation layer 51 corresponding to the drain electrode 43.
  • a test electrode 62 is formed on the surface of the passivation layer 51 from the drain electrode 62. The test electrode 62 and the drain electrode 43 electrical connection.
  • the area of the cross section of the surface portion of the test electrode 62 protruding from the passivation layer 51 is larger than the area of the cross section of the via 52. In this way, it is ensured that the test electrode 62 can completely fill the via 52, which facilitates the complete electrical connection between the test electrode 62 and the pixel electrode or the drain electrode under the passivation layer 51, and reduces the contact resistance; and also facilitates the test electrode 62 in subsequent tests.
  • the test probe is crimped during the process.
  • the common electrode 61 is disposed above the passivation layer 51, is distributed in a comb shape, and is insulated from the test electrode 62.
  • the common electrode 61 has a comb-like distribution. As shown in FIG. 1, the common electrode 61 has a plurality of connected slit electrodes distributed over the passivation layer 51. An island-shaped electrode exposed to the surface layer of the passivation layer 51.
  • the test electrode 62 is the same material as the common electrode 61, that is, the pixel electrode 31, the test electrode 62, and the common electrode 61 can be indium gallium Zinc Oxide (IGZO) or indium oxide (Indium Zinc Oxide). , IZO ), at least one of Indium Tin Oxide (ITO), and Indium Gallium Tin Oxide (IGTO).
  • a gate insulating layer 21 is further disposed, the gate insulating layer 21 is located above the gate electrode 11, and the active layer 22 is located above the gate insulating layer 21 corresponding to the gate electrode 11.
  • the source electrode 42 and the drain electrode 43 are located on both sides above the active layer 22, and the drain electrode 43 extends over the gate insulating layer 21 to overlap the pixel electrode 31, or the drain electrode 43 extends to The pixel electrode 31 overlaps the pixel electrode 31, whereby the layers in which the two electrodes are located are adjacent to each other and are in direct contact. Since the test electrode 62 is electrically connected to the drain electrode 43, and the drain electrode 43 and the pixel electrode 31 are electrically connected, the test electrode 62 and the pixel electrode 31 are also electrically connected.
  • the passivation layer 51 may be formed of at least one of silicon oxide, silicon nitride, tantalum oxide or aluminum oxide; the gate electrode 11, the source electrode 42 and the drain electrode 43 may be made of molybdenum or molybdenum-niobium alloy. Forming at least one of aluminum, aluminum bismuth alloy, titanium or copper; the gate insulating layer 21 may be at least one of silicon oxide, silicon nitride, tantalum oxide, silicon oxynitride, and aluminum oxide. form.
  • the active layer 22 may be formed of an amorphous silicon material or a similar semiconductor material.
  • an electric field formed between the pixel electrode 31 and the common electrode 61 causes the liquid crystal molecules to be deflected, and the light transmittance is controlled to perform image display.
  • a method for fabricating the above array substrate comprising: forming a thin film transistor, a pixel electrode, a common electrode, and a passivation layer on a substrate, the thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode, a passivation layer formed over the source electrode, the drain electrode, and the pixel electrode; a step of forming a via hole in the passivation layer above the drain electrode; and forming a through hole from the upper surface of the drain electrode and protruding a step of testing the electrode on the surface of the passivation layer.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching process, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • Photolithography process refers to a process including film formation, exposure, development, etc., correspondingly requires the use of photoresist, mask, exposure machine, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the photoresist used can be a positive or negative photoresist.
  • Step S1 forming a pattern including a gate electrode on the substrate.
  • a metal thin film ie, a gate electrode metal thin film
  • a pattern including the gate electrode 11 and the gate line 12 is formed by one patterning process, and the gate electrode 11 is formed. Connected to the gate line 12.
  • the metal thin film is formed by, for example, a deposition method, a sputtering method, or a thermal evaporation method, and the thickness of the metal thin film may range from about ⁇ -7 ⁇ .
  • a photoresist is first coated on the metal film, and the photoresist is exposed, developed, etched, and stripped by using a mask to form the gate electrode 11 and the gate line 12. Graphics.
  • a cross-sectional view 3A shows a cross-sectional view of one TFT in the array substrate
  • a plan view 2A shows a plane of two TFTs in the array substrate.
  • the other cross-sectional views mentioned below are the same as the respective plan views.
  • Step S2 forming a gate insulating layer pattern on the substrate on which step S1 is completed, and forming a gate insulating layer pattern by one patterning process.
  • a gate insulating film is formed on the substrate 10 on which the step S1 is completed, and a pattern of the gate insulating layer (GI) is formed by one patterning process.
  • the gate insulating film can be formed by a chemical vapor deposition (CVD) method, and the thickness of the gate insulating film formed is in the range of about ⁇ -6 ⁇ .
  • CVD chemical vapor deposition
  • the gate insulating layer 21 is formed over the gate electrode 11, the gate line 12, and extends to the peripheral lead region of the array substrate.
  • a gate line driving signal introducing electrode is disposed in a peripheral lead region of the array substrate.
  • the gate insulating layer 21 is provided with a via hole at a position corresponding to the gate line driving signal introducing electrode, and the gate line 12 and the gate line driving signal introducing electrode are bonded together through the via hole.
  • Step S3 A pattern including an active layer is formed on the substrate on which the step S2 is completed.
  • an active layer film is formed on the substrate 10 on which the step S2 is completed, and a pattern including the active layer 22 is formed by a patterning process, and the active layer 22 is located in the gate insulating layer. 21 corresponds to the position of the gate electrode 11.
  • the thickness of the active layer film may range from about 100 ⁇ 600 to 600 ⁇ ⁇ .
  • a photoresist is applied on the active layer film, and the photoresist is exposed, developed, etched, and stripped using a mask to form the gate electrode active layer 22. Graphics.
  • the active layer film can be dry etched to form a pattern of active layer 22. At this time, the active layer 22 for one TFT is formed as a silicon island.
  • the gate insulating layer 21 is generally formed of a transparent material (silicon oxide, silicon nitride, tantalum oxide, silicon oxynitride, aluminum oxide). In order not to obstruct the observation of the plan view, the gate insulating layer 21 is omitted in the plan view of Fig. 2B so that the relative positional relationship of the gate electrode 11, the gate line 12 and the active layer 22 can be better shown.
  • Step S4 forming a pattern including the pixel electrode on the substrate on which the step S3 is completed and forming a pattern including the source electrode and the drain electrode, the pixel electrode being electrically connected to the drain electrode.
  • step S4 may include the following steps S41-S42:
  • Step S41 forming a pixel electrode film on the substrate on which step S3 is completed, and forming a pattern including the pixel electrode 31 by a patterning process, the pixel electrode 31 being located in a region where the gate insulating layer is not formed with the active layer.
  • a pixel electrode film is formed on the substrate 10 on which the step S3 is completed, and a pattern including the pixel electrode 31 is formed by one patterning process, and the pixel electrode 31 is located on the gate insulating layer 21.
  • the region of the active layer 22 is not formed.
  • the pixel electrode film can be formed by chemical vapor deposition, sputtering or thermal evaporation, and the thickness of the pixel electrode film is about ⁇ - ⁇ .
  • a photoresist is applied on the pixel electrode film, and the photoresist is exposed, developed, etched, and stripped using a mask to form a pattern of the pixel electrode 31.
  • the pixel electrode 31 has a rectangular shape to facilitate an increase in the aperture ratio of the pixel.
  • the shape of the pixel electrode 31 may also be other shapes such as a wedge shape or a circular shape, but the present invention is not limited thereto.
  • Step S42 forming a metal thin film on the substrate on which step S41 is completed, and forming a pattern including a source electrode, a drain electrode, and a data line by a patterning process, the source electrode and the drain electrode being located on two sides above the active layer, The source electrode is connected to the data line, and the drain electrode extends above the pixel electrode to overlap the pixel electrode.
  • a metal thin film ie, a source/drain metal film
  • the source electrode 42, the drain electrode 43, and the data line are formed by one patterning process.
  • a pattern of 41, the source electrode 42 and the drain electrode 43 are located on both sides of the active layer 22, the source electrode 42 is connected to the data line 41, and the drain electrode 43 extends to the pixel electrode 31 Pick up.
  • the metal thin film can be formed by a deposition method, a sputtering method, or a thermal evaporation method.
  • a photoresist is first coated on the metal film, and the photoresist is exposed, developed, etched, and stripped by using a mask to form the source electrode 42 and the drain electrode 43.
  • the graph of the data line 41 is not limited to a photoresist.
  • step S4 may further include the following Steps S41, -S42,:
  • Step S41 forming a metal thin film on the substrate on which the step S3 is completed, forming a pattern including a source electrode, a drain electrode, and a data line by a patterning process, the source electrode and the drain electrode being located on both sides of the active layer, The source electrode is connected to the data line, and the drain electrode extends onto the gate insulating layer.
  • Step S42 forming a pixel electrode film on the substrate on which the step S41 is completed, forming a pattern including a pixel electrode by a patterning process, the pixel electrode being located on a region of the gate insulating layer where the active layer is not formed, The pixel electrode overlaps with a drain electrode extending over the gate insulating layer.
  • Step S5 forming a passivation layer pattern on the substrate on which step S4 is completed, the passivation layer pattern covering the source electrode, the drain electrode and the pixel electrode and opening a via hole in the passivation layer above the drain electrode.
  • a passivation layer film is formed on the substrate 10 on which the step S4 is completed, and a passivation layer 51 (PVX) pattern is formed by one patterning process, and the passivation layer 51 is patterned.
  • the source electrode 42, the drain electrode 43 and the pixel electrode 31, and the passivation layer 51 above the drain electrode 43 is provided with a via 52, the drain electrode 43 and the pixel electrode 31 Electrically connected through the vias 52.
  • the passivation layer film may be formed by a deposition method, a sputtering method, or a thermal evaporation method, and the passivation layer film may have a thickness ranging from about 100 ⁇ 600 to 600 ⁇ ⁇ .
  • a photoresist is applied on the passivation layer film, and the photoresist is exposed, developed, etched, and stripped using a mask to form a passivation layer 51 and The pattern of the holes 52.
  • the passivation layer 51 is formed over the data line 41, the source electrode 42 and the drain electrode 43 and extends to the peripheral lead region of the array substrate, and the data line driving signal introduction electrode is provided in the peripheral lead region of the array substrate, and is passivated.
  • the layer 51 is provided with a via hole at a position corresponding to the data line driving signal introducing electrode, and the data line 41 and the data line driving signal introducing electrode are bonded together through the via.
  • the passivation layer 51 is generally formed of a transparent material (silicon oxide, silicon nitride, hafnium oxide or aluminum oxide). In order not to obstruct the observation of the plan view, the passivation layer 51 is omitted in the plan view of Fig. 2E so as to better show the relative positional relationship of other structures.
  • Step S6 forming a pattern including a common electrode and a test electrode on the substrate on which step S5 is completed, the test The test electrode and the common electrode are insulated.
  • a common electrode film is formed on the substrate 10 on which the step S5 is completed, and a pattern including the common electrode 61 and the test electrode 62 is formed over the passivation layer 51 by one patterning process.
  • the test electrode 62 passes through the via 52 from the upper surface of the drain electrode 43 and protrudes from the surface of the passivation layer 51. At this time, the test electrode 62 is electrically connected to the drain electrode 43 under the passivation layer 51 through the via 52, that is, the signal of the pixel electrode 31 is directed above the passivation layer 51.
  • the common electrode film may be formed by a deposition method, a sputtering method, or a thermal evaporation method.
  • a photoresist is applied on the common electrode film, and the photoresist is exposed, developed, etched, and stripped using a mask to form the common electrode 61 and the test electrode 62.
  • the common electrode 61 is a slit electrode distributed in a comb shape
  • the test electrode 62 is an island electrode located above the drain electrode.
  • the number of patterning processes can also be reduced by using a halftone or gray tone mask or the like in forming the respective layer structures, and the embodiment of the present invention is not limited thereto.
  • the test probe when it is required to perform electrical performance testing on the TFT in a certain sub-pixel unit, the test probe can be directly contacted to the test electrode in the corresponding sub-pixel unit, so that the measurement is very convenient. Moreover, the measurement process is non-destructive and, therefore, does not have any effect on the sub-pixel unit or the array substrate.
  • the TFT in the sub-pixel unit When the TFT in the sub-pixel unit is short-circuited during the test, that is, the channel between the source electrode and the drain electrode is incompletely etched, resulting in bridging and causing a short-circuit fault, the corresponding display area of the sub-pixel unit Will be a bright spot. Since the sub-pixel unit in this embodiment has a test electrode formed in the same layer as the common electrode, as a remedy, the source electrode and the drain electrode are simply cut off by a laser, and the test electrode electrically connected to the drain electrode is connected.
  • the voltage of the common electrode can be loaded on the pixel electrode of the corresponding sub-pixel unit, that is, the pixel electrode and the common electrode have the same voltage (pressure difference is 0), so that the bright spot can be Set to dark spots to improve the quality of the display panel.
  • each of the sub-pixel units in the array substrate includes a test electrode; or, one of each of the N adjacent sub-pixel units includes a test electrode, where N is greater than or equal to A positive integer of 2. That is, based on the remedial work of the test electrode in the array substrate in which a bright spot occurs due to a short-circuit fault of the TFT, each sub-pixel in the array substrate can be single.
  • the element is designed as a structure with a test electrode, and a set of sub-pixel units can also be used according to the application environment or condition of the liquid crystal display device using the array substrate, for example, when N is 3 or 9, 3 or 9
  • One of the sub-pixel units adopts the above-described design with test electrodes in order to obtain better display quality.
  • An embodiment of the present invention provides a liquid crystal display device including the above array substrate.
  • the electrode in the lower layer is a plate-shaped pixel electrode, and the pixel electrode is connected to the drain electrode of the TFT.
  • the upper layer is a common electrode in a slit shape in a slit shape.
  • a multi-dimensional electric field is formed by the electric field generated between the slit electrode edge and the plate electrode layer and the electric field generated between the slit electrodes, so that all liquid crystal molecules in the liquid crystal cell can be deflected, thereby realizing image display.
  • the pixel electrode is a plate electrode, and those skilled in the art can understand that, in order to form a multi-dimensional electric field, the pixel electrode can also be set as a slit electrode. It suffices to dispose the slit electrodes of the pixel electrode and the common electrode.
  • a via hole is formed in a region corresponding to the drain electrode in the passivation layer of the sub-pixel unit, and a test electrode connected to the drain electrode is formed at the same time as the common electrode is formed, due to the pixel electrode and the drain electrode
  • the pole is electrically connected, so that the pixel electrode is electrically connected to the test electrode, which is equivalent to directing the signal of the pixel electrode or the drain electrode in the inner layer to the uppermost layer of the sub-pixel unit, so that the electrical performance of the TFT can be conveniently tested. Solved the problem that the original design TFT electrical performance can not be measured.
  • the test electrode can be conveniently electrically connected to the common electrode adjacent thereto, thereby making The pixel electrode of the short-circuited TFT has the same loading voltage as the common voltage, so that the bright spot can be converted into a dark spot, and the quality level of the liquid crystal display panel is improved.
  • Example 2
  • the active layer in the sub-pixel unit of the array substrate of the present embodiment is formed of a metal oxide semiconductor material.
  • the active layer is formed by indium gallium oxide, indium oxide, indium gallium tin oxide, and the electron mobility between the source electrode and the drain electrode is formed because the active layer is formed of a metal oxide semiconductor.
  • the present invention is not limited to the material of the active layer in the array substrate.
  • a material such as polysilicon is also suitable for the thin film transistor. And the corresponding array substrate, not listed here.
  • a via hole is formed in the passivation layer above the drain electrode of the thin film transistor and a test electrode is disposed, and the test electrode directly directs the signal of the pixel electrode or the drain electrode in the inner layer to the sub-pixel unit.
  • the surface can easily test the electrical properties of the TFT and solve the problem that the original design TFT electrical performance cannot be measured.
  • Embodiments of the present invention also provide a liquid crystal display device including the above array substrate. Since the above array substrate for facilitating TFT performance test is used, the test process of the liquid crystal display device is completed; at the same time, since the array substrate can conveniently solve the bright spot defect caused by the short circuit failure of the TFT, the display of the liquid crystal display device can be improved. quality.

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Abstract

一种阵列基板、制备方法以及液晶显示装置，阵列基板包括基板以及设置于基板上的多个子像素单元，子像素单元包括薄膜晶体管、像素电极（31）、公共电极（61）和钝化层（51），薄膜晶体管包括有源层（22）、栅电极（11）、源电极（42）及漏电极（43），漏电极（42）与像素电极（31）电连接，钝化层（51）覆盖源电极（42）、漏电极（43）和像素电极（31），子像素单元还包括与像素电极（31）电连接且在子像素单元的表面裸露的测试电极（62）。通过测试电极（62），可以很方便地测试TFT的电学性能，还可以提升液晶显示装置的品质等级。

Description

阵列基板、 制备方法以及液晶显示装置 技术领域
本发明的实施例涉及一种阵列基板、 制备方法以及液晶显示装置。 背景技术
随着科学技术的发展， 平板显示装置已取代笨重的 CRT显示装置并曰 益深入人们的日常生活中。 液晶显示装置（筒称 LCD )是平板显示装置中 的一种。液晶显示装置的主要构成部件是液晶面板，液晶面板主要包括彩膜 基板和阵列基板，彩膜基板和阵列基板之间填充有液晶。在阵列基板或彩膜 基板中还设置有用于产生电场的电极， 电极的结构设置可以决定液晶的偏 转，进而影响液晶面板的显示。液晶面板上具有多个像素点（一般包括 RGB 三个子像素单元）； 在成像过程中， 每一像素点都由制备在阵列基板中的薄 膜晶体管（筒称 TFT )来控制， 实现有源驱动， 从而实现图像显示。 薄膜晶 体管作为控制开关， 是实现 LCD显示装置显示的关键， 直接关系到高性能 平板显示装置的发展方向。
随着液晶显示技术的发展， 同时为了满足人们对高亮度、 高对比度、低 能耗的要求， 高级超维场转换技术（ADvanced Super Dimension Switch, 筒 称 ADS, 又称 ADSDS )应运而生。 ADS型阵列基板中通常包括位于液晶 盒同一侧的两层电极， 其中一层为狭缝电极， 另一层为板状电极。 通过狭缝 电极边缘与板状电极层间产生的电场、以及狭缝电极之间产生的电场共同形 成多维电场，使液晶盒内的液晶分子都能够发生偏转，从而提高了液晶工作 效率并增大了视角。 高级超维场转换技术可以提高像素的开口率，进而提升 亮度， 降低能耗， 提升液晶显示面板的品质等级， 提高 TFT-LCD产品的画 面品质。
一般而言， 在 ADS型阵列基板中， 子像素单元中处于下层的电极为板 状的公共电极， 上层的电极为狭缝状的像素电极； 在高开口率 ADS ( High aperture ADS, 筒称 H-ADS )型阵列基板中， 子像素单元中处于下层的电 极为板状的像素电极， 像素电极与 TFT的漏电极相连， 而上层的电极为狭 缝状的公共电极。 在 H-ADS型阵列基板中， 由于像素电极被其上方的钝化 层（PVX )与公共电极所覆盖， 所以在阵列基板制备完成后， 对子像素单元 中的 TFT进行电学特性测试（例如 TFT开关电流、 阈值电压及电子迁移率 的测试） 时， 测试探针无法接触到像素电极或漏电极， 导致 TFT特性无法 测量， 进一步导致对 TFT电学性能的监控相当不便。 因此， 如何提高阵列 基板中像素电极的测试便捷性，提高阵列基板的产品质量成为目前业界 待 解决的问题。 发明内容
本发明的实施例为了克服上述不足，提供一种阵列基板、制备方法以及 液晶显示装置，通过使用测试电极将处于内层的像素电极或漏电极的信号直 接引到子像素单元的最上层， 可以很方便地测试 TFT的电学性能， 解决了 原有设计 TFT电学性能难以测量的问题。
根据本发明的一个方面提供一种阵列基板，其包括基板以及设置于所述 基板上的多个子像素单元， 所述子像素单元包括薄膜晶体管、像素电极、公 共电极和钝化层，所述薄膜晶体管包括有源层位于有源层上方的两侧，所述 漏电极延伸至栅绝缘层上方与所述像素电极搭接，或者所述漏电极延伸至像 素电极上方与所述像素电极搭接。
根据本发明的一个实施例， 所述测试电极与所述公共电极的材料相同， 均采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少一种形成。
根据本发明进一步的实施例，所述阵列基板中每一个子像素单元中均包 括有所述测试电极； 或者， 每 N个相邻的子像素单元中的其中一个子像素 单元中包括有所述测试电极， 其中， N为大于等于 2的正整数。
根据本发明的另一个方面提供一种液晶显示装置， 包括上述的阵列基 板。
根据本发明的另一个方面提供一种阵列基板的制备方法， 包括：在基板 上形成薄膜晶体管、像素电极、公共电极和钝化层的步骤， 所述薄膜晶体管 包括有源层、 栅电极、 源电极和漏电极， 所述钝化层形成于所述源电极、 漏 电极和像素电极之上；在漏电极上方的钝化层中形成过孔； 以及形成从所述 根据本发明的一个实施例， 该制备方法包括：
步骤 S1: 在基板上形成包括栅电极的图形； 步骤 S2: 在完成步骤 SI的基板上形成栅绝缘层图形；
步骤 S3: 在完成步骤 S2的基板上形成包括有源层的图形；
步骤 S4:在完成步骤 S3的基板上形成包括像素电极的图形以及形成包 括源电极和漏电极的图形， 所述像素电极与所述漏电极电连接；
步骤 S5: 在完成步骤 S4的基板上形成钝化层图形， 所述钝化层图形覆 盖所述源电极、漏电极和像素电极，并且在漏电极上方的钝化层中开设过孔； 步骤 S6:在完成步骤 S5的基板上形成包括公共电极和测试电极的图形， 面。
根据本发明进一步的实施例， 所述步骤 S1包括： 在基板上形成金属薄 膜，通过一次构图工艺形成包括栅电极和栅线的图形，所述栅线和所述栅电 极相连。
根据本发明进一步的实施例， 所述步骤 S2包括： 在完成步骤 S1的基 板上形成栅绝缘层薄膜， 通过一次构图工艺形成栅绝缘层图形。
根据本发明进一步的实施例， 所述步骤 S3包括： 在完成步骤 S2的基 板上形成有源层薄膜，通过一次构图工艺形成包括有源层的图形，所述有源 层位于栅绝缘层上对应栅电极的位置。
根据本发明进一步的实施例， 所述步骤 S4包括： 步骤 S41: 在完成步 骤 S3的基板上形成像素电极薄膜， 通过一次构图工艺形成包括像素电极的 图形，所述像素电极位于所述栅绝缘层上未形成有所述有源层的区域； 步骤 S42: 在完成步骤 S41的基板上形成金属薄膜， 通过一次构图工艺形成包括 源电极、漏电极和数据线的图形，所述源电极和漏电极位于所述有源层上方 两侧，所述源电极与所述数据线相连，所述漏电极延伸至所述像素电极上方 与像素电极搭接。
或者， 根据本发明的进一步的实施例， 所述步骤 S4包括：
步骤 S41，： 在完成步骤 S3的基板上形成金属薄膜， 通过一次构图工艺 形成包括源电极、漏电极和数据线的图形，所述源电极和漏电极位于所述有 源层上方两侧，所述源电极与所述数据线相连，所述漏电极延伸至所述栅绝 缘层上；
步骤 S42，： 在完成步骤 S41，的基板上形成像素电极薄膜， 通过一次构 图工艺形成包括像素电极的图形，所述像素电极位于所述栅绝缘层上未形成 有所述有源层的区域， 所述像素电极与延伸到栅绝缘层上方的漏电极搭接。 根据本发明的一个实施例， 所述步骤 S5包括： 在完成步骤 S4的基板 上形成钝化层薄膜，通过一次构图工艺形成钝化层图形，所述钝化层图形覆 盖所述源电极、所述漏电极和所述像素电极，并且在所述漏电极上方的所述 钝化层中开设有过孔。
根据本发明的一个实施例， 所述步骤 S6包括： 在完成步骤 S5的基板 上形成公共电极薄膜 ,通过一次构图工艺在所述钝化层上方形成包括公共电 极和测试电极的图形，所述测试电极从所述漏电极上表面穿过所述过孔并突 出于所述钝化层的表面， 所述测试电极与所述公共电极绝缘。 附图说明
下面将结合附图， 对根据本发明实施例提供的阵列基板、 制备方法以及 液晶显示装置的具体实施方式进行详细地说明， 其中：
图 1为本发明实施例 1中阵列基板的平面示意图；
图 2A-2F和图 3A-3F为图 1中阵列基板的制备流程的平面示意图和 沿图 1中 A-A'剖面线的剖面图； 其中：
图 2A为形成栅电极和栅线的平面示意图；
图 3A为图 2A对应的剖视图；
图 2B为形成栅绝缘层和有源层的平面示意图；
图 3B为图 2B对应的剖视图；
图 2C为形成像素电极的平面示意图；
图 3C为图 2C对应的剖视图；
图 2D为形成源电极和漏电极的平面示意图；
图 3D为图 2D对应的剖视图；
图 2E为形成钝化层和其中的过孔的平面示意图；
图 3E为图 2E对应的剖视图；
图 2F为形成公共电极和测试电极的平面示意图；
图 3F为图 2F对应的剖视图。
图中： 10—基板； 11—栅电极； 12—栅线； 21—栅绝缘层； 22—有源 层； 31 -像素电极； 41 -数据线； 42 -源电极； 43 -漏电极； 51 -钝化层； 52 -过孔； 61 -公共电极； 62 -测试电极。 具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具 体实施方式对本发明阵列基板、 制备方法以及液晶显示装置作进一步详细、 完整的描述。显然， 所描述的实施例仅是本发明的一部分示例性实施例， 而 不是全部的实施例。基于所描述的本发明的示例性实施例，本领域普通技术 人员在无需创造性劳动的前提下所获得的所有其它实施例都属于本发明的 保护范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人员所理解的通常意义。本发明专利申请说明书以及权 利要求书中使用的"第一"、 "第二 "以及类似的词语并不表示任何顺序、 数量 或者重要性， 而只是用来区分不同的组成部分。 同样， "一个"、 "一次"、 "一" 或者"该"等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者"包含"等类似的词语意指出现该词前面的元件或者物件涵盖出现在该 词后面列举的元件或者物件及其等同， 而不排除其他元件或者物件。 "连接" 或者"相连"等类似的词语并非限定于物理的或者机械的连接，而是可以包括 电性的连接， 不管是直接的还是间接的。 "上"、 "下"、 "左"、 "右"等仅用于 表示相对位置关系， 当被描述对象的绝对位置改变后，则该相对位置关系也 可能相应地改变。
根据本发明的实施例提供的阵列基板，其包括基板以及设置于所述基板 上的多个子像素单元， 所述子像素单元包括薄膜晶体管、像素电极、公共电 极和钝化层， 所述薄膜晶体管包括有源层、 栅电极、 源电极及漏电极， 所述 漏电极与所述像素电极电连接，所述钝化层覆盖所述源电极、漏电极和像素 电极，所述子像素单元还包括与所述像素电极电连接，且在所述子像素单元 的表面棵露的测试电极。 基板可以为玻璃基板、 石英基板或塑料基板等。
根据本发明的实施例提供的液晶显示装置， 包括上述的阵列基板。 根据本发明的实施例提供的阵列基板的制备方法，包括在基板上形成薄 膜晶体管、像素电极、公共电极和钝化层的步骤， 所述薄膜晶体管包括有源 层、 栅电极、 源电极和漏电极， 所述钝化层形成于所述源电极、 漏电极和像 素电极之上；在漏电极上方的钝化层中形成过孔； 以及形成从所述漏电极上 表面穿过所述过孔并突出于所述钝化层表面的测试电极的步骤。 该阵列基板以及制备方法，通过在薄膜晶体管的漏电极上方的钝化层开 设过孔并设置测试电极，将处于内层的像素电极或漏电极的信号直接引到了 子像素单元的最上层， 可以很方便地测试 TFT的电学性能； 使用该阵列基 板的液晶显示装置也具有同样的效果。
实施例 1 :
本实施例提供了一种阵列基板，包括基板以及设置于所述基板上的多个 子像素单元， 所述子像素单元包括薄膜晶体管、像素电极、公共电极和钝化 层， 所述薄膜晶体管包括有源层、 栅电极、 源电极及漏电极， 所述漏电极与 所述像素电极电连接， 所述钝化层覆盖所述源电极、 漏电极和像素电极， 其 中所述子像素单元还包括与所述像素电极电连接并且在所述子像素单元的 表面棵露的测试电极。
如图 1所示， 在子像素单元中， 栅电极 11、 有源层 22、 像素电极 31、 源电极 42与漏电极 43、 钝化层 51以及公共电极 61依次层叠设置。 所述钝 化层 51对应着所述漏电极 43的区域开设有过孔 52, 测试电极 62从所述漏 极 62形成在钝化层 51的表面上，所述测试电极 62与所述漏电极 43电连接。
在本实施例中，所述测试电极 62突出于所述钝化层 51的表面部分的横 截面的面积大于所述过孔 52的横截面的面积。 这样， 既可以保证测试电极 62能将过孔 52完全填充，有利于测试电极 62和钝化层 51下方的像素电极 或漏电极的完全电连接， 降低接触电阻； 也便于测试电极 62在后续测试过 程中与测试探针压接。
在本实施例的阵列基板中，所述公共电极 61设置于所述钝化层 51的上 方， 呈梳状分布， 且与所述测试电极 62绝缘。 所述公共电极 61呈梳状分布 是指如图 1所示，公共电极 61为多条相连的狭缝电极分布于钝化层 51上方。 暴露于钝化层 51表层的孤岛状电极。
所述测试电极 62与所述公共电极 61的材料相同， 即像素电极 31、 测 试电极 62以及公共电极 61均可以采用氧化铟镓辞 ( Indium Gallium Zinc Oxide, IGZO )、氧化铟辞 ( Indium Zinc Oxide, IZO )、氧化铟锡 ( Indium Tin Oxide, ITO )、 氧化铟镓锡（ Indium Gallium Tin Oxide, IGTO ) 中的至少一 种形成。 在本实施例的阵列基板中， 还包括栅绝缘层 21 , 所述栅绝缘层 21位于 所述栅电极 11的上方， 所述有源层 22位于所述栅绝缘层 21上方对应栅电 极 11的位置， 所述源电极 42、 漏电极 43位于有源层 22上方的两侧， 所述 漏电极 43延伸至栅绝缘层 21上方与所述像素电极 31搭接， 或者所述漏电 极 43延伸至像素电极 31上方与所述像素电极 31搭接， 由此两个电极所在 的层彼此相邻而直 触。 由于测试电极 62与漏电极 43电连接， 而漏电极 43和像素电极 31电连接，进而所述测试电极 62与像素电极 31也是电连接 的。
所述钝化层 51可以采用硅氧化物、 硅氮化物、 铪氧化物或铝氧化物中 的至少一种形成； 所述栅电极 11、 源电极 42和漏电极 43可以采用钼、 钼 铌合金、 铝、 铝钕合金、 钛或铜中的至少一种形成； 所述栅绝缘层 21可以 采用硅氧化物、 硅氮化物、铪氧化物、 硅氮氧化物、 铝氧化物中的至少一种 形成。 在本实施例中， 所述有源层 22可以采用非晶硅材料或类似的半导体 材料形成。
在液晶显示面板工作过程中，像素电极 31与公共电极 61之间形成的电 场使得液晶分子发生偏转， 控制透光率以进行图像显示。
上述阵列基板的一种制备方法， 包括： 在基板上形成薄膜晶体管、像素 电极、 公共电极和钝化层的步骤， 所述薄膜晶体管包括有源层、 栅电极、 源 电极和漏电极， 所述钝化层形成于所述源电极、 漏电极和像素电极之上； 在 漏电极上方的钝化层中形成过孔的步骤；以及形成从所述漏电极上表面穿过 所述过孔并突出于所述钝化层表面的测试电极的步骤。
在阐述具体制备方法之前，应该理解， 在本发明中， 构图工艺可只包括 光刻工艺， 或包括光刻工艺以及刻蚀工艺， 同时还可以包括打印、喷墨等其 他用于形成预定图形的工艺； 光刻工艺是指包括成膜、 曝光、显影等工艺过 程， 相应地需要利用光刻胶、掩模板、 曝光机等。 可根据本发明中所形成的 结构选择相应的构图工艺。 所使用的光刻胶可以为正性或负性光刻胶。
阵列基板制备方法的具体示例包括如下步骤：
步骤 S1: 在基板上形成包括栅电极的图形。
在本步骤中： 如图 2A、 3A所示， 先在基板 10上形成金属薄膜（即栅 电极金属薄膜）， 通过一次构图工艺形成包括栅电极 11和栅线 12的图形， 所述栅电极 11和所述栅线 12相连。 形成金属薄膜例如采用沉积法、溅射法或热蒸发法，金属薄膜的厚度范 围可为约 ιοοοΑ-7θθθΑ。在所述构图工艺中，先在金属薄膜上涂敷一层光刻 胶， 采用掩模板对所述光刻胶进行曝光、 显影、 刻蚀、 剥离， 以形成包括栅 电极 11与栅线 12的图形。
这里，为了能更突出地示意本实施例中阵列基板在制备过程中的剖面结 构， 剖视图 3A示出了阵列基板中一个 TFT的剖面图， 而平面图 2A示出了 阵列基板中两个 TFT的平面示意图， 下面提到的其它各剖视图与各平面图 与此同。
步骤 S2: 在完成步骤 S1的基板上形成栅绝缘层图形， 通过一次构图工 艺形成栅绝缘层图形。
在本步骤中： 如图 3B所示， 在完成步骤 S1的基板 10上形成栅绝缘层 薄膜， 通过一次构图工艺形成栅绝缘层（GI ) 的图形。
可以采用化学气相沉积（CVD ) 法形成栅绝缘层膜， 形成的栅绝缘层 薄膜的厚度范围为约 ιοοοΑ-6θθθΑ。
这里， 栅绝缘层 21形成在栅电极 11、 栅线 12的上方并延伸至阵列基 板的外围引线区域。在阵列基板的外围引线区域设置有栅线驱动信号引入电 极。 栅绝缘层 21在对应栅线驱动信号引入电极的位置开设有过孔， 栅线 12 与栅线驱动信号引入电极通过过孔绑定（bonding )在一起。
步骤 S3: 在完成步骤 S2的基板上形成包括有源层的图形。
在本步骤中： 如图 2B、 3B所示， 在完成步骤 S2的基板 10上形成有源 层薄膜，通过一次构图工艺形成包括有源层 22的图形，所述有源层 22位于 栅绝缘层 21上对应栅电极 11的位置。
有源层薄膜的厚度范围可为约 100θΑ-600θΑ。在所述构图工艺中，先在 有源层薄膜上涂敷一层光刻胶， 采用掩模板对所述光刻胶进行曝光、 显影、 刻蚀、 剥离， 以形成栅电极有源层 22的图形。 在一个实施例中， 可以对有 源层薄膜进行干法刻蚀以形成有源层 22的图形。 此时， 用于一个 TFT的有 源层 22形成为一个硅岛。
这里， 栅绝缘层 21—般采用透明材料（硅氧化物、 硅氮化物、 铪氧化 物、 硅氮氧化物、 铝氧化物）形成。 为了不会造成对平面图的观察的阻碍， 在图 2B的平面示意图中略去了栅绝缘层 21 , 以便能更好地示出栅电极 11、 栅线 12与有源层 22的相对位置关系。 步骤 S4:在完成步骤 S3的基板上形成包括像素电极的图形以及形成包 括源电极和漏电极的图形， 所述像素电极与所述漏电极电连接。
步骤 S4的一个具体示例可包括如下的步骤 S41-S42:
步骤 S41 : 在完成步骤 S3的基板上形成像素电极膜， 通过一次构图工 艺形成包括像素电极 31的图形，所述像素电极 31位于所述栅绝缘层未形成 有所述有源层的区域。
在本步骤 S41中， 如图 2C、 3C所示， 在完成步骤 S3的基板 10上形成 像素电极薄膜， 通过一次构图工艺形成包括像素电极 31的图形， 像素电极 31位于所述栅绝缘层 21上未形成有所述有源层 22的区域。
可以采用化学气相沉积法、溅射法或热蒸发法形成像素电极薄膜，像素 电极薄膜的厚度范围为约 ιοοΑ-ΐοοοΑ。 在所述构图工艺中， 先在像素电极 薄膜上涂敷一层光刻胶， 采用掩模板对所述光刻胶进行曝光、 显影、 刻蚀、 剥离，以形成像素电极 31的图形。在本实施例中，像素电极 31为矩形形状， 以利于提高像素的开口率。
应该理解的是， 像素电极 31的形状也可以为其他形状， 例如楔形或圓 形， 但是本发明不限于此。
步骤 S42: 在完成步骤 S41的基板上形成金属薄膜， 通过一次构图工艺 形成包括源电极、漏电极和数据线的图形，所述源电极和漏电极位于所述有 源层上方两侧，所述源电极与所述数据线相连，所述漏电极延伸至所述像素 电极上方与所述像素电极搭接。
在本步骤 S42中： 如图 2D、 3D所示， 在完成步骤 S41的基板 10上形 成金属薄膜（即源漏电极金属薄膜），通过一次构图工艺形成包括源电极 42、 漏电极 43和数据线 41的图形，所述源电极 42和漏电极 43位于所述有源层 22的上方两侧， 所述源电极 42与数据线 41相连， 所述漏电极 43延伸至与 所述像素电极 31搭接。
可以采用沉积法、溅射法或热蒸发法形成金属薄膜。在所述构图工艺中， 先在金属薄膜上涂敷一层光刻胶,采用掩模板对所述光刻胶进行曝光、显影、 刻蚀、 剥离， 以形成包括源电极 42、 漏电极 43和数据线 41的图形。
这里应该理解的是，本实施例并不限定形成源电极、漏电极与形成像素 电极的顺序，在实际形成薄膜晶体管或阵列基板的过程中可根据工艺条件或 操作便利性进行灵活安排。 也就是说， 步骤 S4的另一个示例还可包括如下 的步骤 S41，-S42，：
步骤 S41，： 在完成步骤 S3的基板上形成金属薄膜， 通过一次构图工艺 形成包括源电极、漏电极和数据线的图形，所述源电极和漏电极位于所述有 源层上方两侧，所述源电极和所述数据线相连，所述漏电极延伸至所述栅绝 缘层上。
步骤 S42，： 在完成步骤 S41，的基板上形成像素电极薄膜， 通过一次构 图工艺形成包括像素电极的图形，所述像素电极位于所述栅绝缘层上未形成 有所述有源层的区域， 所述像素电极与延伸到栅绝缘层上方的漏电极搭接。
步骤 S5: 在完成步骤 S4的基板上形成钝化层图形， 所述钝化层图形覆 盖所述源电极、 漏电极和像素电极并且在漏电极上方的钝化层中开设有过 孔。
在本步骤 S5中， 如图 2E、 3E所示， 在完成步骤 S4的基板 10上形成 钝化层薄膜， 通过一次构图工艺形成钝化层 51 ( PVX ) 图形， 所述钝化层 51图形覆盖所述源电极 42、 所述漏电极 43和所述像素电极 31 , 并且所述 漏电极 43上方的所述钝化层 51中开设有过孔 52,所述漏电极 43与所述像 素电极 31通过所述过孔 52电连接。
可以采用沉积法、溅射法或热蒸发法形成钝化层薄膜，钝化层薄膜的厚 度范围可为约 100θΑ-600θΑ。在所述构图工艺中，先在钝化层薄膜上涂敷一 层光刻胶， 采用掩模板对所述光刻胶进行曝光、 显影、 刻蚀、 剥离， 以形成 包括钝化层 51和过孔 52的图形。
此时， 钝化层 51形成在数据线 41、 源电极 42和漏电极 43的上方并延 伸至阵列基板的外围引线区域，在阵列基板的外围引线区域设置有数据线驱 动信号引入电极， 钝化层 51在对应数据线驱动信号引入电极的位置开设有 过孔， 所述数据线 41与数据线驱动信号引入电极通过过孔绑定（bonding ) 在一起。
在本步骤中， 与栅绝缘层 21类似，钝化层 51—般采用透明材料 (硅氧 化物、 硅氮化物、 铪氧化物或铝氧化物）形成。 为了不造成对平面图的观 察的阻碍， 在图 2E的平面示意图中略去了钝化层 51 , 以便能更好地示出其 他结构的相对位置关系。
步骤 S6:在完成步骤 S5的基板上形成包括公共电极和测试电极的图形， 所述测试 面， 所述测试电极和所述公共电极绝缘。
在本步骤 S6中： 如图 2F、 3F所示， 在完成步骤 S5的基板 10上形成 公共电极薄膜， 通过一次构图工艺在所述钝化层 51上方形成包括公共电极 61和测试电极 62的图形，所述测试电极 62从所述漏电极 43上表面穿过所 述过孔 52并突出于所述钝化层 51的表面。 此时， 所述测试电极 62通过过 孔 52与钝化层 51下方的漏电极 43电连接，即将像素电极 31的信号引到钝 化层 51的上方。
形成公共电极薄膜可采用沉积法、溅射法或热蒸发法。在所述构图工艺 中，先在公共电极薄膜上涂敷一层光刻胶，采用掩模板对所述光刻胶进行曝 光、 显影、 刻蚀、 剥离， 以形成包括公共电极 61和测试电极 62的图形。 公 共电极 61为呈梳状分布的狭缝电极，测试电极 62为位于漏电极上方的孤岛 电极。
在上述阵列基板的制备方法中，在形成各层结构时，还可以通过使用半 色调或灰色调掩模板等方式来减少构图工艺的次数，本发明的实施例并不限 于此。
在本实施例的阵列基板中， 当需要对某个子像素单元中的 TFT进行电 学性能测试时，可以直接将测试探针接触到相应的子像素单元中的测试电极 上， 因此， 测量非常方便， 而且测量过程是非损坏性的， 因此， 不会对子像 素单元或阵列基板造成任何影响。
当测试过程中发现子像素单元中的 TFT发生短路时， 即源电极与漏电 极之间的沟道因刻蚀不完全，导致出现桥连并引起短路故障时，这个子像素 单元对应的显示区域将会成为亮点。由于本实施例中的子像素单元具有与公 共电极同层形成的测试电极，作为一种补救措施，此时只需用激光将源电极 与漏电极切断，并将与漏电极电连接的测试电极与旁边的公共电极电连接在 一起， 即可将公共电极的电压加载在对应的子像素单元的像素电极上， 即像 素电极与公共电极具有相同的电压（压差为 0 ), 从而可以将亮点设置成暗 点， 提高了显示面板的品质。
在本实施例中， 阵列基板中每一个子像素单元中均包括有测试电极；或 者， 每 N个相邻的子像素单元中的一个子像素单元中包括有测试电极， 其 中， N为大于等于 2的正整数。 即，基于上述阵列基板中测试电极对因 TFT 出现短路故障而出现亮点的补救功措施，可以将阵列基板中的每个子像素单 元都设计成带有测试电极的结构，也可以根据采用该阵列基板的液晶显示装 置的应用环境或条件， 将一组子像素单元， 例如， 当 N为 3或 9时， 将 3 个或 9个子像素单元中的一个子像素单元采用上述的具有测试电极的设计， 以便能获得更好的显示品质。
本发明的一个实施例提供了一种包括上述阵列基板的液晶显示装置，在 该液晶显示装置的每个像素单元中，处于下层的电极为板状的像素电极，像 素电极与 TFT的漏电极相连， 而上层的为狭缝状呈梳状分布的公共电极。 通过狭缝电极边缘与板状电极层间产生的电场、以及狭缝电极之间产生的电 场共同形成多维电场，使液晶盒内的所有液晶分子都能够发生偏转，从而实 现图像显示。
需要说明的是， 本发明实施例中均以所述像素电极为板状电极进行说 明， 本领域技术人员可以理解的是， 为了形成多维电场， 也可以将像素电极 设置为狭缝状电极，这时只需将像素电极和公共电极的狭缝电极错位设置即 可。
本实施例的阵列基板中，在子像素单元的钝化层中对应着漏电极的区域 形成一个过孔， 并在形成公共电极的同时形成一个与漏电极相连的测试电 极， 由于像素电极与漏电极电连接， 因此像素电极与测试电极电连接， 这样 就相当于将处于内层的像素电极或漏电极的信号直接引到了子像素单元的 最上层， 从而可以很方便地测试 TFT的电学性能， 解决了原有设计 TFT电 学性能无法测量的问题。 同时， 由于像素电极设置有与公共电极同在一层的 测试电极， 当出现某个 TFT因短路故障而发生亮点不良时， 可很方便地将 测试电极与其旁边的公共电极进行电连接， 从而使得该短路故障的 TFT的 像素电极具有与公共电压相同的加载电压， 以便能将亮点转化为暗点，提升 液晶显示面板的品质等级。 实施例 2:
本实施例与实施例 1的区别在于，本实施例阵列基板的子像素单元中的 有源层采用金属氧化物半导体材料形成。
在本实施例中， 所述有源层采用氧化铟镓辞、 氧化铟辞、 氧化铟镓锡形 成， 由于有源层采用金属氧化物半导体形成，使得源电极与漏电极之间的电 子迁移率增加， 因此能更好地改善源电极与漏电极之间的电子迁移率。 事实上， 本发明对阵列基板中有源层的材料没有限制， 除了实施例 1 中的非晶硅材料、实施例 2中的金属氧化物半导体材料之外，多晶硅等材料 也适用于该薄膜晶体管以及相应的阵列基板中， 这里不再列举。
本实施例中阵列基板的其他结构以及制备方法具体可参考实施例 1 ,这 里不再详述。
本发明实施例的阵列基板中，通过在薄膜晶体管的漏电极上方的钝化层 开设过孔并设置测试电极，测试电极将处于内层的像素电极或漏电极的信号 直接引到了子像素单元的表面， 可以很方便地测试 TFT的电学性能， 解决 了原有设计 TFT电学性能无法测量的问题。 同时， 当出现某个 TFT因短路 故障而发生亮点不良时，可很方便地将测试电极与其旁边的公共电极进行电 连接， 从而使得该短路故障的 TFT的像素电极具有与公共电压相同的加载 电压， 以便能将亮点转化为暗点， 提高液晶显示面板的品质等级。
本发明的实施例还提供一种包括上述阵列基板的液晶显示装置。由于使 用了上述方便 TFT性能测试的阵列基板， 从而筒化了液晶显示装置的测试 过程； 同时， 由于阵列基板能方便的解决由于 TFT短路故障而发生的亮点 不良， 从而能提高液晶显示装置的显示品质。
可以理解的是， 以上实施方式仅仅是为了说明本发明的原理而采用的示 例性实施方式， 然而本发明并不局限于此。

Claims

权利要求书
1. 一种阵列基板， 包括：
基板； 以及
设置于所述基板上的多个子像素单元， 所述子像素单元包括薄膜晶体 管、 像素电极、 公共电极和钝化层， 所述薄膜晶体管包括有源层、 栅电极、 源电极及漏电极，所述漏电极与所述像素电极电连接，所述钝化层覆盖所述 源电极、漏电极和像素电极，其中所述子像素单元还包括与所述像素电极电 连接， 且在所述子像素单元的表面棵露的测试电极。
2.根据权利要求 1所述的阵列基板， 其中， 在所述子像素单元中， 所 述钝化层覆盖所述漏电极的区域开设有过孔，所述测试电极从所述漏电极上 表面穿过所述过孔并突出于所述钝化层的表面，所述测试电极与所述漏电极 电连接。
3.根据权利要求 1或 2所述的阵列基板， 其中所述测试电极突出于所 述钝化层的表面部分的横截面的面积大于所述过孔的横截面的面积。
4.根据权利要求 1-3任一项所述的阵列基板， 其中所述公共电极设置 于所述钝化层的上方， 呈梳状分布， 并且与所述测试电极绝缘。
5.根据权利要求 1-4任一项所述的阵列基板， 还包括栅绝缘层， 所述 栅绝缘层位于所述栅电极的上方，所述有源层位于所述栅绝缘层上方对应栅 电极的位置， 所述源电极、 漏电极位于有源层上方的两侧， 所述漏电极延伸 至所述栅绝缘层上方与所述像素电极搭接，或者所述漏电极延伸至所述像素 电极上方与所述像素电极搭接。
6.根据权利要求 1-5任一项所述的阵列基板， 其中所述测试电极与所 述公共电极的材料相同， 均采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟 镓锡中的至少一种形成。
7.根据权利要求 1-6任一项所述的阵列基板， 其中所述阵列基板中每 一个子像素单元中均包括有所述测试电极； 或者， 每 N个相邻的子像素单 元中的一个子像素单元中包括有所述测试电极，其中， N为大于等于 2的正 整数。
8. 一种液晶显示装置， 包括权利要求 1-7任一项所述的阵列基板。
9. 一种阵列基板的制备方法， 包括：
在基板上形成薄膜晶体管、像素电极、公共电极和钝化层的步骤， 所述 薄膜晶体管包括有源层、栅电极、 源电极和漏电极， 所述钝化层形成于所述 源电极、 漏电极和像素电极之上；
在漏电极上方的钝化层中形成过孔的步骤； 以及 试电极的步骤。
10.根据权利要求 9所述的制备方法， 其中，
步骤 S1: 在基板上形成包括栅电极的图形；
步骤 S2: 在完成步骤 S1的基板上形成栅绝缘层图形；
步骤 S3: 在完成步骤 S2的基板上形成包括有源层的图形；
步骤 S4:在完成步骤 S3的基板上形成包括像素电极的图形以及形成包 括源电极和漏电极的图形， 所述像素电极与所述漏电极电连接；
步骤 S5: 在完成步骤 S4的基板上形成钝化层图形， 所述钝化层图形覆 盖所述源电极、漏电极和像素电极，且在所述漏电极上方的钝化层中开设有 所述过孔；
步骤 S6:在完成步骤 S5的基板上形成包括公共电极和测试电极的图形， 面。
11.根据权利要求 10所述的制备方法， 其中所述步骤 S1包括： 在基板 上形成金属薄膜，通过一次构图工艺形成包括栅电极和栅线的图形，所述栅 电极和所述栅线相连。
12.根据权利要求 10或 11所述的制备方法， 其中所述步骤 S2包括： 在完成步骤 S1的基板上形成栅绝缘层薄膜， 通过一次构图工艺形成栅绝缘 层图形。
13.根据权利要求 10-12任一所述的制备方法， 其中所述步骤 S3包括： 在完成步骤 S2的基板上形成有源层薄膜， 通过一次构图工艺形成包括有源 层的图形， 所述有源层位于栅绝缘层上对应栅电极的位置。
14.根据权利要求 10-13任一所述的制备方法， 其中所述步骤 S4包括： 步骤 S41 : 在完成步骤 S3的基板上形成像素电极薄膜， 通过一次构图 工艺形成包括像素电极的图形，所述像素电极位于所述栅绝缘层上未形成有 所述有源层的区域；
步骤 S42: 在完成步骤 S41的基板上形成金属薄膜， 通过一次构图工艺 形成包括源电极、漏电极和数据线的图形，所述源电极和漏电极位于所述有 源层上方两侧，所述源电极和数据线相连，所述漏电极延伸至所述像素电极 上方与像素电极搭接。
15.根据权利要求 10-13任一所述的制备方法， 其中所述步骤 S4包括： 步骤 S41，： 在完成步骤 S3的基板上形成金属薄膜， 通过一次构图工艺 形成包括源电极、漏电极和数据线的图形，所述源电极和漏电极位于所述有 源层上方两侧，所述源电极和所述数据线相连，所述漏电极延伸至所述栅绝 缘层上。
步骤 S42，： 在完成步骤 S41，的基板上形成像素电极薄膜， 通过一次构 图工艺形成包括像素电极的图形，所述像素电极位于所述栅绝缘层上未形成 有所述有源层的区域， 所述像素电极与延伸到栅绝缘层上方的漏电极搭接。
16.根据权利要求 10-15任一所述的制备方法， 其中所述步骤 S5包括： 在完成步骤 S4的基板上形成钝化层薄膜， 通过一次构图工艺形成钝化层图 形， 所述钝化层图形覆盖所述源电极、 所述漏电极和所述像素电极， 且所述 漏电极上方的所述钝化层中开设有过孔。
17.根据权利要求 10-16任一所述的制备方法， 其中所述步骤 S6包括： 在完成步骤 S5 的基板上形成公共电极薄膜， 通过一次构图工艺在所述钝化 层上方形成包括公共电极和测试电极的图形， 所述测试电极从所述漏电极上 表面穿过所述过孔并突出于所述钝化层的表面， 所述测试电极和所述公共电 极绝缘。
PCT/CN2013/080063 2013-04-18 2013-07-25 阵列基板、制备方法以及液晶显示装置 WO2014169543A1 (zh)

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