CN103217840B - 一种阵列基板、制备方法以及液晶显示装置 - Google Patents
一种阵列基板、制备方法以及液晶显示装置 Download PDFInfo
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Abstract
本发明属于显示技术领域,具体涉及一种阵列基板、制备方法以及液晶显示装置。一种阵列基板,包括基板以及设置于所述基板上的多个子像素单元,所述子像素单元包括薄膜晶体管、像素电极、公共电极和钝化层,所述薄膜晶体管包括有源层、栅电极、源电极及漏电极,所述漏电极与所述像素电极电连接,所述钝化层覆盖所述源电极、漏电极和像素电极,所述子像素单元还包括与所述像素电极电连接,且在所述子像素单元的表面裸露的测试电极。该阵列基板通过测试电极,将处于内层的像素电极的信号直接引到了子像素单元的最上层,可以很方便地测试TFT的电学性能;同时,还可以将因TFT不良而引起的亮点转化为暗点,提升液晶显示面板的品质等级。
Description
技术领域
本发明属于显示技术领域,具体涉及一种阵列基板、制备方法以及液晶显示装置。
背景技术
随着科学技术的发展,平板显示装置已取代笨重的CRT显示装置日益深入人们的日常生活中,液晶显示装置(Liquid CrystalDisplay:简称LCD)是平板显示装置中的一种。液晶显示装置的主要构成部件是液晶面板,液晶面板主要包括彩膜基板和阵列基板,彩膜基板和阵列基板之间填充有液晶。其中,在阵列基板或彩膜基板中还设置有用于产生电场的电极,根据电极的结构设置可以决定液晶的偏转,进而影响液晶面板的显示。液晶面板上具有多个像素点(一般包括RGB三个子像素单元),在成像过程中,每一像素点都由集成在阵列基板中的薄膜晶体管(Thin FilmTransistor:简称TFT)来控制,实现有源驱动,从而实现图像显示。薄膜晶体管作为控制开关,是实现LCD显示装置显示的关键,直接关系到高性能平板显示装置的发展方向。
随着液晶显示技术的发展,同时为了满足人们对高亮度、高对比度、低能耗的要求,高级超维场转换技术(ADvanced SuperDimension Switch,简称ADS,又称ADSDS)应运而生。在现有技术中,ADS型阵列基板中通常包括位于液晶盒同一侧的两层电极,其中一层为狭缝电极,另一层为板状电极。通过狭缝电极边缘与板状电极层间产生的电场、以及狭缝电极之间产生的电场共同形成多维电场,使液晶盒内的液晶分子都能够发生偏转,从而提高了液晶工作效率并增大了视角。高级超维场转换技术可以提高像素的开口率,进而提升亮度,降低能耗,提升液晶显示面板的品质等级,提高TFT-LCD产品的画面品质。
一般的,在ADS型阵列基板中,子像素单元中处于下层的电极为板状的公共电极(Com),上层的电极为狭缝状的像素电极(Pixel);在H-ADS(High aperture ADS,高开口率ADS)型阵列基板中,子像素单元中处于下层的电极为板状的像素电极,像素电极与TFT的漏电极相连,而上层的为狭缝状的公共电极。在H-ADS型阵列基板中,由于像素电极被其上方的钝化层(PVX)与公共电极所覆盖,在阵列基板制备完成后,对子像素单元中的TFT进行电学特性测试(例如TFT开关电流、阈值电压及电子迁移率的测试)时,测试探针无法接触到像素电极或漏电极,导致TFT特性无法测量,进一步导致对TFT电学性能的监控相当不便。因此,如何提高阵列基板中像素电极的测试便捷性,提高阵列基板的产品质量成为目前业界亟待解决的问题。
发明内容
本发明所要解决的技术问题是针对现有技术中存在的上述不足,提供一种阵列基板、制备方法以及液晶显示装置,通过测试电极将处于内层的像素电极或漏电极的信号直接引到了子像素单元的最上层,可以很方便地测试TFT的电学性能,解决了原有设计TFT电学性能难以测量的问题。
解决本发明技术问题所采用的技术方案是提供一种阵列基板,包括基板以及设置于所述基板上的多个子像素单元,所述子像素单元包括薄膜晶体管、像素电极、公共电极和钝化层,所述薄膜晶体管包括有源层、栅电极、源电极及漏电极,所述漏电极与所述像素电极电连接,所述钝化层覆盖所述源电极、漏电极和像素电极,所述子像素单元还包括与所述像素电极电连接,且在所述子像素单元的表面裸露的测试电极。
优选的是,在所述子像素单元中,所述钝化层覆盖所述漏电极的区域开设有过孔,所述测试电极从所述漏电极上表面穿过所述过孔并突出于所述钝化层的表面,所述测试电极与所述漏电极电连接。
优选的是,所述测试电极突出于所述钝化层的表面部分的横截面的面积大于所述过孔的横截面的面积。
优选的是,所述公共电极设置于所述钝化层的上方,呈梳状分布,且与所述测试电极绝缘。
优选的是,还包括栅绝缘层,所述栅绝缘层位于所述栅电极的上方,所述有源层位于所述栅绝缘层上方对应栅电极的位置,所述源电极、漏电极位于有源层上方的两侧,所述漏电极延伸至栅绝缘层上方与所述像素电极搭接,或者所述漏电极延伸至像素电极上方与所述像素电极搭接。
优选的是,所述测试电极与所述公共电极的材料相同,均采用氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡中的至少一种形成。
进一步优选的是,所述阵列基板中每一个子像素单元中均包括有所述测试电极;或者,每N个相邻的子像素单元中的其中一个子像素单元中包括有所述测试电极,其中,N为大于等于2的正整数。
一种液晶显示装置,包括上述的阵列基板。
一种阵列基板的制备方法,包括在基板上形成薄膜晶体管、像素电极、公共电极和钝化层的步骤,所述形成薄膜晶体管的步骤包括形成有源层、栅电极、源电极和漏电极的步骤,所述钝化层形成于所述源电极、漏电极和像素电极之上,还包括在漏电极上方的钝化层中形成过孔,以及形成从所述漏电极上表面穿过所述过孔并突出于所述钝化层表面的测试电极的步骤。
优选的是,具体包括如下步骤:
步骤S1:在基板上形成包括栅电极的图形;
步骤S2:在完成步骤S1的基板上形成栅绝缘层图形;
步骤S3:在完成步骤S2的基板上形成包括有源层的图形;
步骤S4:在完成步骤S3的基板上形成包括像素电极的图形以及形成包括源电极和漏电极的图形,所述像素电极与所述漏电极电连接;
步骤S5:在完成步骤S4的基板上形成钝化层图形,所述钝化层图形覆盖所述源电极、漏电极和像素电极,且在漏电极上方的钝化层中开设有过孔;
步骤S6:在完成步骤S5的基板上形成包括公共电极和测试电极的图形,所述测试电极从所述漏电极上表面穿过所述过孔并突出于所述钝化层的表面。
进一步优选的是,所述步骤S1具体为:在基板上形成金属薄膜,通过一次构图工艺形成包括栅电极和栅线的图形,所述栅线和所述栅电极相连。
进一步优选的是,所述步骤S2具体为:在完成步骤S1的基板上形成栅绝缘层薄膜,通过一次构图工艺形成栅绝缘层图形。
进一步优选的是,所述步骤S3具体为:在完成步骤S2的基板上形成有源层薄膜,通过一次构图工艺形成包括有源层的图形,所述有源层位于栅绝缘层上对应栅电极的位置。
进一步优选的是,所述步骤S4具体为:
步骤S41:在完成步骤S3的基板上形成像素电极薄膜,通过一次构图工艺形成包括像素电极的图形,所述像素电极位于所述栅绝缘层上未形成有所述有源层的区域;
步骤S42:在完成步骤S41的基板上形成金属薄膜,通过一次构图工艺形成包括源电极、漏电极和数据线的图形,所述源电极和漏电极位于所述有源层上方两侧,所述源电极与所述数据线相连,所述漏电极延伸至所述像素电极上方与像素电极搭接。
或者,进一步优选的是,所述步骤S4具体为:
步骤S41:在完成步骤S3的基板上形成金属薄膜,通过一次构图工艺形成包括源电极、漏电极和数据线的图形,所述源电极和漏电极位于所述有源层上方两侧,所述源电极与所述数据线相连,所述漏电极延伸至所述栅绝缘层上。
步骤S42:在完成步骤S41的基板上形成像素电极薄膜,通过一次构图工艺形成包括像素电极的图形,所述像素电极位于所述栅绝缘层上未形成有所述有源层的区域,所述像素电极与延伸到栅绝缘层上方的漏电极搭接。
优选的是,所述步骤S5具体为:在完成步骤S4的基板上形成钝化层薄膜,通过一次构图工艺形成钝化层图形,所述钝化层图形覆盖所述源电极、所述漏电极和所述像素电极,且在所述漏电极上方的所述钝化层中开设有过孔。
优选的是,所述步骤S6具体为:在完成步骤S5的基板上形成公共电极薄膜,通过一次构图工艺在所述钝化层上方形成包括公共电极和测试电极的图形,所述测试电极从所述漏电极上表面穿过所述过孔并突出于所述钝化层的表面,所述测试电极和所述公共电极绝缘。
本发明的有益效果是:该阵列基板通过在薄膜晶体管的漏电极上方的钝化层开设过孔并设置测试电极,将处于内层的像素电极或漏电极的信号直接引到了子像素单元的最上层,可以很方便地测试TFT的电学性能;同时,还可以将因TFT不良而引起的亮点转化为暗点,提升液晶显示面板的品质等级。
附图说明
图1为本发明实施例1中阵列基板的平面示意图;
图2A-2F和图3A-3F为图1中阵列基板的制备流程的剖视图和沿图1中A-A′剖面线的平面示意图;
其中:
图2A分别为形成栅电极和栅线的剖视图;
图3A为图2A对应的平面示意图;
图2B分别为形成栅绝缘层和有源层的剖视图;
图3B为图2B对应的平面示意图;
图2C分别为形成像素电极的剖视图;
图3C为图2C对应的平面示意图;
图2D分别为形成源电极和漏电极的剖视图;
图3D为图2D对应的平面示意图;
图2E分别为形成钝化层和其中的过孔的剖视图;
图3E为图2E对应的平面示意图;
图2F分别为形成公共电极和测试电极的剖视图;
图3F为图2F对应的平面示意图。
图中:10-基板;11-栅电极;12-栅线;21-栅绝缘层;22-有源层;31-像素电极;41-数据线;42-源电极;43-漏电极;51-钝化层;52-过孔;61-公共电极;62-测试电极。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明阵列基板、制备方法以及液晶显示装置作进一步详细描述。
该阵列基板,包括基板以及设置于所述基板上的多个子像素单元,所述子像素单元包括薄膜晶体管、像素电极、公共电极和钝化层,所述薄膜晶体管包括有源层、栅电极、源电极及漏电极,所述漏电极与所述像素电极电连接,所述钝化层覆盖所述源电极、漏电极和像素电极,所述子像素单元还包括与所述像素电极电连接,且在所述子像素单元的表面裸露的测试电极。
一种液晶显示装置,包括上述的阵列基板。
一种阵列基板的制备方法,包括在基板上形成薄膜晶体管、像素电极、公共电极和钝化层的步骤,所述形成薄膜晶体管的步骤包括形成有源层、栅电极、源电极和漏电极的步骤,所述钝化层形成于所述源电极、漏电极和像素电极之上,还包括在漏电极上方的钝化层中形成过孔,以及形成从所述漏电极上表面穿过所述过孔并突出于所述钝化层表面的测试电极的步骤。
该阵列基板以及制备方法,通过在薄膜晶体管的漏电极上方的钝化层开设过孔并设置测试电极,将处于内层的像素电极或漏电极的信号直接引到了子像素单元的最上层,可以很方便地测试TFT的电学性能;使用该阵列基板的液晶显示装置也具有同样的效果。
实施例1:
一种阵列基板,包括基板以及设置于所述基板上的多个子像素单元,所述子像素单元包括薄膜晶体管、像素电极、公共电极和钝化层,所述薄膜晶体管包括有源层、栅电极、源电极及漏电极,所述漏电极与所述像素电极电连接,所述钝化层覆盖所述源电极、漏电极和像素电极,所述子像素单元还包括与所述像素电极电连接,且在所述子像素单元的表面裸露的测试电极。
如图1所示,在所述子像素单元中,栅电极11、有源层22、像素电极31、源电极42与漏电极43、钝化层51以及公共电极61依次部分层叠设置。其中,所述钝化层51对应着所述漏电极43的区域开设有过孔52(Via hole),测试电极62从所述漏电极43上表面穿过所述过孔52并突出于所述钝化层51的表面,所述测试电极62与所述漏电极43电连接。
在本实施例中,所述测试电极62突出于所述钝化层51的表面部分的横截面的面积大于所述过孔52的横截面的面积。这样,既可以保证测试电极62能将过孔52完全填充,有利于测试电极62和钝化层51下方的像素电极或漏电极的完全电连接,降低接触电阻;也便于测试电极62在后续测试过程中与测试探针压接。
在本实施例的阵列基板中,所述公共电极61设置于所述钝化层51的上方,呈梳状分布,且与所述测试电极62绝缘。所述公共电极61呈梳状分布是指如图1所示,公共电极61为多条相连的狭缝电极分布于钝化层51上方。所述测试电极62为位于漏电极43上方且穿过钝化层上的过孔52,暴露于钝化层51表层的孤岛状电极。
其中,所述测试电极62与所述公共电极61的材料相同,即像素电极31、测试电极2以及公共电极61均采用氧化铟镓锌、氧化铟锌(Indium Zinc Oxide,简称IZO)、氧化铟锡(Indium TinOxide,简称ITO)、氧化铟镓锡中的至少一种形成。
在本实施例的阵列基板中,还包括栅绝缘层21,所述栅绝缘层21位于所述栅电极11的上方,所述有源层22位于所述栅绝缘层21上方对应栅电极11的位置,所述源电极42、漏电极43位于有源层22上方的两侧,所述漏电极43延伸至栅绝缘层21上方与所述像素电极31搭接,或者所述漏电极43延伸至像素电极31上方与所述像素电极31搭接。由于测试电极62与漏电极43电连接,而漏电极43和像素电极31电连接,进而所述测试电极62与像素电极31也是电连接的。
其中,所述钝化层51可以采用硅氧化物、硅氮化物、铪氧化物或铝氧化物中的至少一种形成;所述栅电极11、源电极42和漏电极43可以均采用钼、钼铌合金、铝、铝钕合金、钛或铜中的至少一种形成;所述栅绝缘层21可以采用硅氧化物、硅氮化物、铪氧化物、硅氮氧化物、铝氧化物中的至少一种形成。在本实施例中,所述有源层22采用非晶硅材料形成。
在液晶显示面板工作过程中,像素电极31与公共电极61之间形成的电场使得液晶分子发生偏转,控制透光率,最终形成图像显示。
上述的阵列基板制备方法,包括在基板上形成薄膜晶体管、像素电极、公共电极和钝化层的步骤,所述形成薄膜晶体管的步骤包括形成有源层、栅电极、源电极和漏电极的步骤,所述钝化层形成于所述源电极、漏电极和像素电极之上,还包括在漏电极上方的钝化层中形成过孔,以及形成从所述漏电极上表面穿过所述过孔并突出于所述钝化层表面的测试电极的步骤。
在阐述具体制备方法之前,应该理解,在本发明中,构图工艺,可只包括光刻工艺,或,包括光刻工艺以及刻蚀步骤,同时还可以包括打印、喷墨等其他用于形成预定图形的工艺;光刻工艺,是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
该制备方法具体包括如下步骤:
步骤S1):在基板上形成包括栅电极的图形。
在本步骤中:如图2A、3A所示,先在基板10上形成金属薄膜(即栅电极金属薄膜),通过一次构图工艺形成包括栅电极11(Gate)和栅线12的图形,所述栅电极11和所述栅线12相连。
其中,形成金属薄膜采用沉积法、溅射法或热蒸发法,金属薄膜的厚度范围为在所述构图工艺中,先在金属薄膜上涂敷一层光刻胶,采用掩模板对所述光刻胶进行曝光、显影、刻蚀、剥离,以形成包括栅电极11与栅线12的图形。
这里,为能更突出地示意本实施例中阵列基板在制备过程中的剖面结构,剖面图2A示出了阵列基板中一个TFT的剖面图,而平面图3A示出了阵列基板中两个TFT的平面示意图,以下各平面图与各剖面图与此同。
步骤S2):在完成步骤S1)的基板上形成栅绝缘层图形,通过一次构图工艺形成栅绝缘层图形。
在本步骤中:如图2B所示,在完成步骤S1)的基板10上形成栅绝缘层薄膜,通过一次构图工艺形成栅绝缘层(GI)的图形。
其中,形成栅绝缘层膜采用化学气相沉积(Chemical VaporDeposition,简称CVD)法,栅绝缘层薄膜的厚度范围为
这里,栅绝缘层21形成在栅电极11、栅线12的上方并延伸至阵列基板的外围引线区域,在阵列基板的外围引线区域设置有栅线驱动信号引入电极,栅绝缘层21在对应栅线驱动信号引入电极的位置开设有过孔,所述栅线12与栅线驱动信号引入电极通过过孔绑定(bonding)在一起。
步骤S3):在完成步骤S2)的基板上形成包括有源层的图形。
在本步骤中:如图2B、3B所示,在完成步骤S2)的基板10上形成有源层薄膜,通过一次构图工艺形成包括有源层22(Active)的图形,所述有源层22位于栅绝缘层21上对应栅电极11的位置。
其中,有源层薄膜的厚度范围为在所述构图工艺中,先在有源层薄膜上涂敷一层光刻胶,采用掩模板对所述光刻胶进行曝光、显影、刻蚀、剥离,以形成栅电极有源层22的图形,优选对有源层薄膜进行干法刻蚀以形成有源层22的图形。此时,有源层22形成一个硅岛。
这里,栅绝缘层21一般采用透明材料(硅氧化物、硅氮化物、铪氧化物、硅氮氧化物、铝氧化物)形成,对平面图的观察不会造成阻碍,因此在图3B的平面示意图中略去栅绝缘层21的示意,以便能更好地示出栅电极11、栅线12与有源层22的相对位置关系。
步骤S4):在完成步骤S3)的基板上形成包括像素电极的图形以及形成包括源电极和漏电极的图形,所述像素电极与所述漏电极电连接。
步骤S4)具体的包括:
步骤S41):在完成步骤S3)的基板上形成像素电极膜,通过一次构图工艺形成包括像素电极的图形,所述像素电极位于所述栅绝缘层未形成有所述有源层的区域。
在本步骤中:如图2C、3C所示,在完成步骤S3)的基板10上形成像素电极薄膜,通过一次构图工艺形成包括像素电极31的图形,所述像素电极31位于所述栅绝缘层21上未形成有所述有源层22的区域。
其中,形成像素电极薄膜采用化学气相沉积法、溅射法或热蒸发法,像素电极薄膜的厚度范围为在所述构图工艺中,先在像素电极薄膜上涂敷一层光刻胶,采用掩模板对所述光刻胶进行曝光、显影、刻蚀、剥离,以形成像素电极31的图形。在本实施例中,像素电极31为矩形形状,可以提高像素的开口率。这里应该理解的是,像素电极31的形状也可以为其他形状,例如楔形或圆形,这里不做限定。
步骤S42):在完成步骤S41)的基板上形成金属薄膜,通过一次构图工艺形成包括源电极、漏电极和数据线的图形,所述源电极和漏电极位于所述有源层上方两侧,所述源电极与所述数据线相连,所述漏电极延伸至所述像素电极上方与像素电极搭接。
在本步骤中:如图2D、3D所示,在完成步骤S41)的基板10上形成金属薄膜(即源漏电极金属薄膜),通过一次构图工艺形成包括源电极42、漏电极43和数据线41的图形,所述源电极42和漏电极43位于所述有源层22的上方两侧,所述源电极42与数据线41相连,所述漏电极43延伸至与所述像素电极31搭接。
其中,形成金属薄膜采用沉积法、溅射法或热蒸发法。在所述构图工艺中,先在金属薄膜上涂敷一层光刻胶,采用掩模板对所述光刻胶进行曝光、显影、刻蚀、剥离,以形成包括源电极42、漏电极43和数据线41的图形。
这里应该理解的是,本实施例并不限定形成源电极、漏电极与形成像素电极的顺序,在实际形成薄膜晶体管或阵列基板的过程中可根据工艺条件或操作便利性进行灵活安排。也就是说,步骤S4)还可具体的包括:
步骤S41):在完成步骤S3)的基板上形成金属薄膜,通过一次构图工艺形成包括源电极、漏电极和数据线的图形,所述源电极和漏电极位于所述有源层上方两侧,所述源电极和所述数据线相连,所述漏电极延伸至所述栅绝缘层上。
步骤S42):在完成步骤S41)的基板上形成像素电极薄膜,通过一次构图工艺形成包括像素电极的图形,所述像素电极位于所述栅绝缘层上未形成有所述有源层的区域,所述像素电极与延伸到栅绝缘层上方的漏电极搭接。
步骤S5):在完成步骤S4)的基板上形成钝化层图形,所述钝化层图形覆盖所述源电极、漏电极和像素电极且在漏电极上方的钝化层中开设有过孔。
在本步骤中:如图2E、3E所示,在完成步骤S4)的基板10上形成钝化层薄膜,通过一次构图工艺形成钝化层51(PVX)图形,所述钝化层51图形覆盖所述源电极42、所述漏电极43和所述像素电极31,且所述漏电极43上方的所述钝化层51中开设有过孔52,所述漏电极43与所述像素电极31通过所述过孔52电连接。
其中,形成钝化层薄膜采用沉积法、溅射法或热蒸发法,钝化层薄膜的厚度范围为在所述构图工艺中,先在钝化层薄膜上涂敷一层光刻胶,采用掩模板对所述光刻胶进行曝光、显影、刻蚀、剥离,以形成包括钝化层51和过孔52的图形。
此时,钝化层51形成在数据线41、源电极42和漏电极43的上方并延伸至阵列基板的外围引线区域,在阵列基板的外围引线区域设置有数据线驱动信号引入电极,钝化层51在对应数据线驱动信号引入电极的位置开设有过孔,所述数据线41与数据线驱动信号引入电极通过过孔绑定(bonding)在一起。
在本步骤中,与栅绝缘层21类似,钝化层51一般采用透明材料(硅氧化物、硅氮化物、铪氧化物或铝氧化物)形成,对平面图的观察不会造成阻碍,因此在图3E的平面示意图中略去钝化层51的示意,以便能更好地示出其他结构的相对位置关系。
步骤S6):在完成步骤S5)的基板上形包括公共电极和测试电极的图形,所述测试电极从所述漏电极上表面穿过所述过孔并突出于所述钝化层的表面,所述测试电极和所述公共电极绝缘。
在本步骤中:如图2F、3F所示,在完成步骤S5)的基板10上形成公共电极薄膜,通过一次构图工艺在所述钝化层51上方形成包括公共电极61和测试电极62的图形,所述测试电极62从所述漏电极43上表面穿过所述过孔52并突出于所述钝化层51的表面。此时,所述测试电极62通过过孔52与钝化层51下方的漏电极43电连接,即将像素电极31的信号引到钝化层51的上方。
其中,形成公共电极薄膜采用沉积法、溅射法或热蒸发法。在所述构图工艺中,先在公共电极薄膜上涂敷一层光刻胶,采用掩模板对所述光刻胶进行曝光、显影、刻蚀、剥离,以形成包括公共电极61和测试电极62的图形。其中,公共电极61为呈梳状分布的狭缝电极,测试电极62为位于漏电极上方的孤岛电极。
在上述阵列基板的制备方法中,在形成各层结构时,还可以通过使用半色调或灰色调掩模板等方式来减少构图工艺的次数,本实施例并不做限定。
在本实施例的阵列基板中,当需要对某个子像素单元中的TFT进行电学性能测试时,直接将测试探针接触到相应的子像素单元中的测试电极上即可,测量非常方便,而且测量过程是非损坏的,不会对子像素单元或阵列基板造成任何影响。
当测试过程中发现子像素单元中的TFT发生短路时,即源电极与漏电极之间的沟道因刻蚀不完全,导致出现桥连并引起短路故障时,这个子像素单元对应的显示区域将会成为亮点。由于本实施例中的子像素单元具有与公共电极同层形成的测试电极,作为一种补救措施,此时只需用激光将源电极与漏电极切断,并将与漏电极电连接的测试电极与旁边的公共电极电连接在一起,即可将公共电极的电压加载在对应的子像素单元的像素电极上,即像素电极与公共电极具有相同的电压(压差为0),从而将亮点设置成暗点,提高了显示面板的品质。
在本实施例中,该阵列基板中每一个子像素单元中均包括有测试电极;或者,每N个相邻的子像素单元中的其中一个子像素单元中包括有测试电极,其中,N为大于等于2的正整数。即,基于上述阵列基板中测试电极对因TFT出现短路故障而出现亮点的补救功措施,可以将阵列基板中的每个子像素单元都设计成带有测试电极的结构,也可以根据采用该阵列基板的液晶显示装置的应用环境或条件,将一组子像素单元,例如,当N为3或9时,将3个或9个子像素单元中的其中一个子像素单元采用上述的具有测试电极的设计,以便能获得更好的显示品质。
一种包括上述的阵列基板的液晶显示装置。在该液晶显示装置中,处于下层的电极为板状的像素电极,像素电极与TFT的漏电极相连,而上层的为狭缝状呈梳状分布的公共电极。通过狭缝电极边缘与板状电极层间产生的电场、以及狭缝电极之间产生的电场共同形成多维电场,使液晶盒内的所有液晶分子都能够发生偏转,从而实现图像显示。
需要说明的是,本发明实施例中均以所述像素电极为板状电极进行说明,本领域技术人员可以理解的是,为了形成多维电场,还可以将像素电极也设置为狭缝状电极,只需将像素电极和公共电极的狭缝电极错位设置即可。
本实施例的阵列基板中,在子像素单元的钝化层中对应着漏电极的区域形成一个过孔,并在形成公共电极的同时形成一个与漏电极相连的测试电极,由于像素电极与漏电极电连接,因此像素电极与测试电极电连接,这样就相当于将处于内层的像素电极或漏电极的信号直接引到了子像素单元的最上层,可以很方便地测试TFT的电学性能,解决了原有设计TFT电学性能无法测量的问题。同时,由于像素电极设置有与公共电极同在一层的测试电极,当出现某个TFT因短路故障而发生亮点不良时,可很方便地将测试电极与其旁边的公共电极进行电连接,从而使得该短路故障的TFT的像素电极具有与公共电压相同的加载电压,以便能将亮点转化为暗点,提升液晶显示面板的品质等级。
实施例2:
本实施例与实施例1的区别在于,本实施例阵列基板的子像素单元中的有源层采用金属氧化物半导体材料形成。
在本实施例中,所述有源层采用氧化铟镓锌、氧化铟锌、氧化铟镓锡形成,由于有源层采用金属氧化物半导体形成,使得源电极与漏电极之间的电子迁移率增加,因此能更好地改善源电极与漏电极之间的电子迁移率。
事实上,本发明对阵列基板中有源层的材料没有限制,除了实施例1中的非晶硅材料、实施例2中的金属氧化物半导体材料之外,多晶硅等材料也适用于该薄膜晶体管以及相应的阵列基板中,这里不再列举。
本实施例中阵列基板的其他结构以及制备方法具体可参考实施例1,这里不再详述。
本发明实施例的阵列基板中,通过测试电极将处于内层的像素电极或漏电极的信号直接引到了子像素单元的表面,可以很方便地测试TFT的电学性能,解决了原有设计TFT电学性能无法测量的问题。同时,当出现某个TFT因短路故障而发生亮点不良时,可很方便地将测试电极与其旁边的公共电极进行电连接,从而使得该短路故障的TFT的像素电极具有与公共电压相同的加载电压,以便能将亮点转化为暗点,提升液晶显示面板的品质等级。
本发明还提供一种包括上述的阵列基板的液晶显示装置。由于使用了上述方便TFT性能测试的阵列基板,从而简化了液晶显示装置的测试过程,同时,由于阵列基板能方便的解决由于TFT短路故障而发生的亮点不良,从而能提高液晶显示装置的显示品质。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (17)
1.一种阵列基板,包括基板以及设置于所述基板上的多个子像素单元,所述子像素单元包括薄膜晶体管、像素电极、公共电极和钝化层,所述薄膜晶体管包括有源层、栅电极、源电极及漏电极,所述漏电极与所述像素电极电连接,所述钝化层覆盖所述源电极、漏电极和像素电极,其特征在于,所述子像素单元还包括与所述像素电极电连接,且在所述子像素单元的表面裸露的测试电极,用以测试TFT的电学性能。
2.根据权利要求1所述的阵列基板,其特征在于,在所述子像素单元中,所述钝化层覆盖所述漏电极的区域开设有过孔,所述测试电极从所述漏电极上表面穿过所述过孔并突出于所述钝化层的表面,所述测试电极与所述漏电极电连接。
3.根据权利要求2所述的阵列基板,其特征在于,所述测试电极突出于所述钝化层的表面部分的横截面的面积大于所述过孔的横截面的面积。
4.根据权利要求3所述的阵列基板,其特征在于,所述公共电极设置于所述钝化层的上方,呈梳状分布,且与所述测试电极绝缘。
5.根据权利要求4所述的阵列基板,其特征在于,还包括栅绝缘层,所述栅绝缘层位于所述栅电极的上方,所述有源层位于所述栅绝缘层上方对应栅电极的位置,所述源电极、漏电极位于有源层上方的两侧,所述漏电极延伸至栅绝缘层上方与所述像素电极搭接,或者所述漏电极延伸至像素电极上方与所述像素电极搭接。
6.根据权利要求5所述的阵列基板,其特征在于,所述测试电极与所述公共电极的材料相同,均采用氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡中的至少一种形成。
7.根据权利要求1-6任一项所述的阵列基板,其特征在于,所述阵列基板中每一个子像素单元中均包括有所述测试电极;或者,每N个相邻的子像素单元中的其中一个子像素单元中包括有所述测试电极,其中,N为大于等于2的正整数。
8.一种液晶显示装置,其特征在于,包括权利要求1-7任一项所述的阵列基板。
9.一种阵列基板的制备方法,包括在基板上形成薄膜晶体管、像素电极、公共电极和钝化层的步骤,所述形成薄膜晶体管的步骤包括形成有源层、栅电极、源电极和漏电极的步骤,所述钝化层形成于所述源电极、漏电极和像素电极之上,其特征在于,还包括在漏电极上方的钝化层中形成过孔,以及形成从所述漏电极上表面穿过所述过孔并突出于所述钝化层表面的测试电极的步骤,其中,所述测试电极用以测试TFT的电学性能。
10.根据权利要求9所述的制备方法,其特征在于,具体包括如下步骤:
步骤S1:在基板上形成包括栅电极的图形;
步骤S2:在完成步骤S1的基板上形成栅绝缘层图形;
步骤S3:在完成步骤S2的基板上形成包括有源层的图形;
步骤S4:在完成步骤S3的基板上形成包括像素电极的图形以及形成包括源电极和漏电极的图形,所述像素电极与所述漏电极电连接;
步骤S5:在完成步骤S4的基板上形成钝化层图形,所述钝化层图形覆盖所述源电极、漏电极和像素电极,且在漏电极上方的钝化层中开设有过孔;
步骤S6:在完成步骤S5的基板上形成包括公共电极和测试电极的图形,所述测试电极从所述漏电极上表面穿过所述过孔并突出于所述钝化层的表面。
11.根据权利要求10所述的制备方法,其特征在于,所述步骤S1具体为:在基板上形成金属薄膜,通过一次构图工艺形成包括栅电极和栅线的图形,所述栅电极和所述栅线相连。
12.根据权利要求10所述的制备方法,其特征在于,所述步骤S2具体为:在完成步骤S1的基板上形成栅绝缘层薄膜,通过一次构图工艺形成栅绝缘层图形。
13.根据权利要求10所述的制备方法,其特征在于,所述步骤S3具体为:在完成步骤S2的基板上形成有源层薄膜,通过一次构图工艺形成包括有源层的图形,所述有源层位于栅绝缘层上对应栅电极的位置。
14.根据权利要求10所述的制备方法,其特征在于,所述步骤S4具体为:
步骤S41:在完成步骤S3的基板上形成像素电极薄膜,通过一次构图工艺形成包括像素电极的图形,所述像素电极位于所述栅绝缘层上未形成有所述有源层的区域;
步骤S42:在完成步骤S41的基板上形成金属薄膜,通过一次构图工艺形成包括源电极、漏电极和数据线的图形,所述源电极和漏电极位于所述有源层上方两侧,所述源电极和数据线相连,所述漏电极延伸至所述像素电极上方与像素电极搭接。
15.根据权利要求10所述的制备方法,其特征在于,所述步骤S4具体为:
步骤S41:在完成步骤S3的基板上形成金属薄膜,通过一次构图工艺形成包括源电极、漏电极和数据线的图形,所述源电极和漏电极位于所述有源层上方两侧,所述源电极和所述数据线相连,所述漏电极延伸至所述栅绝缘层上;
步骤S42:在完成步骤S41的基板上形成像素电极薄膜,通过一次构图工艺形成包括像素电极的图形,所述像素电极位于所述栅绝缘层上未形成有所述有源层的区域,所述像素电极与延伸到栅绝缘层上方的漏电极搭接。
16.根据权利要求10所述的制备方法,其特征在于,所述步骤S5具体为:在完成步骤S4的基板上形成钝化层薄膜,通过一次构图工艺形成钝化层图形,所述钝化层图形覆盖所述源电极、所述漏电极和所述像素电极,且所述漏电极上方的所述钝化层中开设有过孔。
17.根据权利要求16所述的制备方法,其特征在于,所述步骤S6具体为:在完成步骤S5的基板上形成公共电极薄膜,通过一次构图工艺在所述钝化层上方形成包括公共电极和测试电极的图形,所述测试电极从所述漏电极上表面穿过所述过孔并突出于所述钝化层的表面,所述测试电极和所述公共电极绝缘。
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