CN104076537A - 阵列基板及其制作方法、显示装置及测量方法 - Google Patents
阵列基板及其制作方法、显示装置及测量方法 Download PDFInfo
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Abstract
本发明涉及液晶显示技术领域,公开了一种阵列基板及其制作方法、显示装置及测量方法。所述阵列基板包括暴露在表面的电性连接块,通过在钝化层中制作钝化层过孔,露出薄膜晶体管的漏电极或像素电极,使得所述电性连接块填充所述钝化层过孔,与漏电极或像素电极接触设置,从而在测量TFT电学特性值时,测量设备的Pixel探针可以通过与所述电性连接块的直接接触,而与漏电极或像素电极电性连接,实现对TFT电学特性的测量。
Description
技术领域
本发明涉及液晶显示技术领域,特别是涉及一种阵列基板及其制作方法、显示装置及测量方法。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display,简称TFT-LCD)具有体积小、功耗低、无辐射、制造成本相对较低等特点,在当前的平板显示器市场占据了主导地位。TFT-LCD阵列基板是TFT-LCD的重要部件之一。在阵列基板上形成有横纵交叉的栅线和数据线,限定多个像素单元,每个像素单元包括薄膜晶体管(Thin Film Transistor,简称TFT)、像素电极和公共电极,TFT的漏电极和像素电极电性连接,源电极和数据线电性连接,栅电极和栅线电性连接。数据线上传输的像素电压通过薄膜晶体管输出至像素电极,像素电极与公共电极配合,形成驱动液晶分子偏转的驱动电场,实现特定灰阶的显示。
可见,TFT的电学特性直接影响TFT-LCD的显示品质,因此,在实际生产过程中,都需要对TFT的电学特性进行测量。其中,TFT的电学特性主要包括Ion(TFT工作电流),Ioff(反向截止电流),Vth(开启电压),Mobility(迁移率),每一个参数都非常重要。目前测量TFT电学特性的设备在测量时需要将对应的探针与配线接触,才能测量出电学特性值,如栅线(Gate)探针与栅线接触,数据(Data)探针与数据线接触,像素(Pixel)探针与漏电极或像素电极接触。通过Gate探针加载0~20V,Data探针加载15V电信号,进而通过Pixel探针输出的信号获取TFT的电学特性值。
当公共电极不形成在阵列基板上时,像素电极位于阵列基板的最上层,测量TFT电学特性的Pixel探针可以直接与像素电极接触,来测量TFT的电学特性值。但是,当公共电极形成在阵列基板上时,公共电极通常位于阵列基板的最上层,像素电极位于公共电极的下方,导致测量设备的Pixel探针无法直接与像素电极接触,从而无法测量实际TFT的电学特性。
发明内容
本发明提供一种阵列基板及其制作方法、显示装置及测量方法,用以解决当公共电极形成在阵列基板上时,测量TFT电学特性的设备的Pixel探针无法直接与像素电极接触,从而无法测量TFT的电学特性值的问题。
为解决上述技术问题,本发明提供一种阵列基板,包括多个像素单元,每个像素单元包括薄膜晶体管、像素电极和公共电极,所述像素电极和薄膜晶体管的上方覆盖有钝化层,所述公共电极位于所述钝化层的上方,并与所述像素电极的位置对应,所述薄膜晶体管的漏电极与所述像素电极电性连接,其中,所述钝化层中形成有钝化层过孔;
每个像素单元还包括填充所述钝化层过孔的电性连接块;
所述电性连接块的一端通过所述钝化层过孔与所述像素电极或漏电极接触设置,另一端暴露在所述阵列基板的表面。
如上所述的阵列基板,优选的是,所述电性连接块与公共电极由同一透明导电层通过一次构图工艺同时形成,所述公共电极设置于所述阵列基板的最上层。
如上所述的阵列基板,优选的是,所述电性连接块贯穿所述钝化层过孔,且所述电性连接块的一端与所述像素电极或所述漏电极之间的接触面积小于暴露在所述阵列基板的表面的另一端的截面面积,暴露在所述阵列基板的表面的另一端覆盖在所述钝化层的表面。
如上所述的阵列基板,优选的是,所述薄膜晶体管的漏电极设置于所述像素电极的上方,且与所述像素电极直接搭接;所述电性连接块的一端通过所述钝化层过孔与薄膜晶体管的漏电极接触设置。
如上所述的阵列基板,优选的是,所述像素电极设置于所述薄膜晶体管的漏电极的上方,且与所述薄膜晶体管的漏电极直接搭接;所述电性连接块的一端通过所述钝化层过孔与所述像素电极接触设置。
本发明还提供一种显示装置,其包括如上所述的阵列基板。
本发明还提供一种阵列基板的制作方法,包括:
形成多个像素单元;
形成每个像素单元的步骤包括:
形成薄膜晶体管和像素电极的图案;
在所述像素电极和薄膜晶体管的上方形成钝化层;
在所述钝化层的上方形成公共电极的图案,所述公共电极与像素电极的位置对应,所述薄膜晶体管的漏电极与所述像素电极电性连接,其中,形成每个像素单元的步骤还包括:
对所述钝化层进行构图工艺形成钝化层过孔;
形成一填充所述钝化层过孔的电性连接块,所述电性连接块的一端与所述像素电极或漏电极接触设置,另一端暴露在所述阵列基板的表面。
如上所述的制作方法,优选的是,形成所述公共电极和电性连接块的步骤具体为:
在所述钝化层上形成透明导电层;
对所述透明导电层进行构图工艺,形成所述公共电极和电性连接块的图案。
如上所述的制作方法,优选的是,所述电性连接块贯穿所述钝化层过孔,且所述电性连接块的一端与所述像素电极或所述漏电极之间的接触面积小于暴露在所述阵列基板的表面的另一端的截面面积,暴露在所述阵列基板的表面的另一端覆盖在所述钝化层的表面。
本发明还提供一种对如上所述的阵列基板的电学特性进行测量的方法,包括:
将栅线探针与阵列基板的栅线接触;
将数据探针与阵列基板的数据线接触,其中,
所述阵列基板的钝化层中形成有钝化层过孔,所述阵列基板还包括一填充所述钝化层过孔的电性连接块,所述电性连接块的一端通过所述钝化层过孔与所述像素电极或漏电极接触设置,另一端暴露在所述阵列基板的表面;
所述测试方法还包括:
将像素探针与所述电性连接块接触,对栅线探针和数据线探针加载预设的电压,通过像素探针输出的信号获取薄膜晶体管的电学特性值。
本发明的上述技术方案的有益效果如下:
上述技术方案中,TFT阵列基板包括暴露在表面的电性连接块,通过在钝化层上制作钝化层过孔,露出薄膜晶体管的漏电极或像素电极,使得所述电性连接块填充所述钝化层过孔,与漏电极或像素电极接触设置,从而在测量TFT电学特性值时,测量设备的Pixel探针可以通过与所述电性连接块的直接接触,而与漏电极或像素电极电性连接,实现对TFT电学特性的测量。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。
图1表示本发明实施例中阵列基板的结构示意图;
图2表示图1沿A-A方向的剖视图;
图3表示图1沿B-B方向的剖视图;
图4表示本发明实施例中阵列基板的制作流程示意图;
图5-图9表示本发明实施例中阵列基板的制作过程示意图。
具体实施方式
结合图1所示,TFT-LCD的阵列基板包括横纵交叉的栅线10和数据线20,栅线10和数据线20限定多个像素单元。每个像素单元包括薄膜晶体管和像素电极4,薄膜晶体管的栅电极1与栅线10电性连接,源电极2与数据线20电性连接,漏电极3与像素电极4电性连接。TFT-LCD还包括公共电极5,用于与像素电极4配合,用于产生驱动液晶分子旋转的电场。其中,公共电极5可以形成在阵列基板上,也可以形成在TFT-LCD的彩膜基板上。
对于TFT-LCD,TFT的电学特性直接影响产品的显示品质。因此,在实际生产过程中,对TFT的电学特性进行测量是最重要的生产环节之一。TFT的电学特性主要包括Ion(TFT工作电流),Ioff(反向截止电流),Vth(开启电压),Mobility(迁移率)。目前测量TFT电学特性的设备在测量时需要将对应的探针与配线接触,才能测量出电学特性值,如栅线(Gate)探针与栅线接触,数据(Data)探针与数据线接触,像素(Pixel)探针与漏电极或像素电极接触。
当公共电极5形成在彩膜基板上时,像素电极4位于阵列基板的最上层,测量TFT电学特性的Pixel探针可以直接与像素电极接触,来测量TFT的电学特性值。但是,当公共电极5形成在阵列基板上,且公共电极5位于阵列基板的最上层,像素电极4位于公共电极5的下方时,导致测量设备的Pixel探针无法直接与像素电极4接触,从而无法测量实际TFT的电学特性。
本发明就是针对上述技术问题,提供一种薄膜晶体管阵列基板及其制作方法,以实现公共电极位于阵列基板上,且位于像素电极上方,即位于阵列基板的最上层时,对TFT电学特性的测量。
下面将结合附图和实施例,对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明,但不用来限制本发明的范围。
本发明实施例中提供一种阵列基板,其包括多个像素单元,每个像素单元包括薄膜晶体管、像素电极和公共电极。所述像素电极和薄膜晶体管的上方覆盖有钝化层。所述公共电极位于所述钝化层的上方,并与所述像素电极的位置对应。所述薄膜晶体管的漏电极与所述像素电极电性连接。
在所述钝化层中还形成有钝化层过孔,以露出薄膜晶体管的漏电极或像素电极。并设置每个像素单元还包括填充所述钝化层过孔的电性连接块,使得所述电性连接块的一端通过所述钝化层过孔与所述像素电极或漏电极接触设置,另一端暴露在所述阵列基板的表面。
上述技术方案,由于电性连接块其中一端暴露在阵列基板的表面,在进行TFT电学特性的测量时,测量设备的Pixel探针可以直接与电性连接块的该端接触,且该电性连接块与像素电极或漏电极电性接触,进而实现Pixel探针与像素电极或漏电极的电性连接,进而可通过探针输出的信号获取TFT的电学特性值。
相应地,上述薄膜晶体管阵列基板的制作方法包括:
形成多个像素单元;
如图4所示,形成每个像素单元的步骤包括:
步骤S1、形成薄膜晶体管和像素电极的图案;
步骤S2、在所述像素电极和薄膜晶体管的上方形成钝化层;
步骤S3、对所述钝化层进行构图工艺形成钝化层过孔;
步骤S4、在所述钝化层的上方形成公共电极和电性连接块的图案,所述公共电极与像素电极的位置对应,所述薄膜晶体管的漏电极与所述像素电极电性连接。所述电性连接块填充所述钝化层过孔,其一端通过所述钝化层过孔与所述像素电极或漏电极接触设置,另一端暴露在所述阵列基板的表面。
优选地,所述电性连接块与公共电极由同一透明导电层通过一次构图工艺同时形成,且所述公共电极设置于所述阵列基板的最上层。具体的,可以在钝化层上形成透明导电膜层,然后对透明导电膜层进行构图工艺,同时形成所述电性连接块与公共电极,也就是说,该透明导电膜层在钝化层过孔位置填充于该钝化层过孔中,以形成上述的电性连接块,而不必另外设置填充材料作为电性连接块,由于公共电极和电性连接块所在层位于阵列基板的最上层,使电性连接块暴露在阵列基板表面,因此,可直接将用于测量的像素探针与连接块接触,以对阵列基板的电学特性进行测试。该步骤具体包括:
在所述透明导电层上涂覆光刻胶;
对光刻胶进行曝光和显影,形成光刻胶保留区域和光刻胶不保留区域,其中,光刻胶保留区域至少对应于公共电极和电性连接块所在的区域,光刻胶不保留区域对应于其他区域;
通过湿法刻蚀工艺去除光刻胶不保留区域的透明导电层,形成包括公共电极和电性连接块的图案;
剥离剩余的光刻胶,形成公共电极和电性连接块。
进一步地,所述电性连接块贯穿所述钝化层过孔,且所述电性连接块的一端与所述像素电极或所述漏电极之间的接触面积小于暴露在所述阵列基板的表面的另一端的截面面积,暴露在所述阵列基板的表面的另一端覆盖在所述钝化层的表面,此种设置方式可方便用于测试的像素探针与所述电性连接块的接触,保证二者电性接触良好,以更加方便的对阵列基板的电学特性进行测试。
本发明的技术方案中,TFT阵列基板包括暴露在表面的电性连接块,通过在钝化层中制作钝化层过孔,露出薄膜晶体管的漏电极或像素电极,使得所述电性连接块填充所述钝化层过孔,与漏电极或像素电极接触设置,从而在测量TFT电学特性值时,测量设备的Pixel探针可以通过与所述电性连接块的直接接触,实现与漏电极或像素电极电性连接,进而实现对TFT电学特性值的测量。
当公共电极形成在阵列基板上时,薄膜晶体管的漏电极与像素电极一般通过直接搭接的方式电性连接。需要说明的是,本发明中涉及的搭接是指:第一图案位于第二图案的上方,且两个图案接触设置,具有交叠的区域。
当薄膜晶体管的漏电极设置于像素电极的上方,且与像素电极直接搭接时,所述电性连接块的一端通过所述钝化层过孔与薄膜晶体管的漏电极接触设置。
当像素电极设置于薄膜晶体管的漏电极的上方,且与薄膜晶体管的漏电极直接搭接时,所述电性连接块的一端通过所述钝化层过孔与所述像素电极接触设置。
结合图1-图3所示,本发明实施例中,阵列基板具体包括:
衬底基板100,为透明基板,通常为玻璃基板、石英基板或有机树脂基板;
形成在衬底基板100上的栅电极1和栅线10,栅电极1与栅线10电性连接;
形成在栅电极1和栅线10上的栅绝缘层102;
形成在栅绝缘层102上的有源层图案7;
形成在有源层图案7上的像素电极4;
形成在像素电极4上的数据线20、源电极2和漏电极3,其中,漏电极3直接搭接在像素电极4上方,源电极2与数据线20电性连接;
形成在数据线20、源电极2和漏电极3上的钝化层101,在钝化层101上中形成有钝化层过孔(图中未示出),露出漏电极3;
形成在钝化层101上的公共电极5和电性连接块6,公共电极5为狭缝电极,与像素电极4的位置对应。电性连接块6填充所述钝化层过孔,其一端通过所述钝化层过孔与漏电极3接触,另一端覆盖在钝化层101的表面。
结合图3和图5-图9所示,本发明实施例中,阵列基板的制作方法具体包括:
步骤a、结合图5所示,提供一衬底基板100,通过一次构图工艺在衬底基板100上形成栅电极1和栅线(图中未示出);
提供一衬底基板100,在衬底基板100上形成由栅金属层组成的包括栅电极1和与栅电极1连接的栅线的图案。其中,衬底基板100可为玻璃基板、石英基板或有机树脂基板。
具体地,可以采用溅射或热蒸发的方法在衬底基板100上沉积一层厚度为的栅金属层,栅金属层可以是Cu,Al,Ag,Mo,Cr,Nd,Ni,Mn,Ti,Ta,W等金属以及这些金属的合金,栅金属层可以为单层结构或者多层结构,多层结构比如Cu\Mo,Ti\Cu\Ti,Mo\Al\Mo等。在栅金属层上涂覆一层光刻胶,采用掩膜板对光刻胶进行曝光,显影,使光刻胶形成光刻胶不保留区域和光刻胶保留区域,其中,光刻胶保留区域对应于栅线和栅电极1的所在区域,光刻胶不保留区域对应于其他区域;通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的栅金属薄膜,剥离剩余的光刻胶,形成栅线和栅电极1。
步骤b、如图5所示,在经过步骤a的衬底基板100上形成栅绝缘层102;
具体地,可以采用等离子体增强化学气相沉积(PECVD)方法,在经过步骤a的衬底基板100上沉积厚度约为的栅绝缘层102,其中,栅绝缘层材料可以选用氧化物、氮化物或者氮氧化物,栅绝缘层102可以为单层、双层或多层结构。具体地,栅绝缘层102可以是SiNx,SiOx或Si(ON)x。
步骤c、如图6所示,在经过步骤b的衬底基板100上形成有源层图案7;
具体地,可以在经过步骤b的衬底基板100上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为的有源层,其中,有源层的材料为硅半导体或金属氧化物半导体。然后对有源层进行构图工艺,形成有源层图案7。
步骤d、如图7所示,在经过步骤c的衬底基板100上形成像素电极4;
具体地,在经过步骤c的衬底基板100上采用磁控溅射、热蒸发或其它成膜方法沉积厚度为的透明导电层,透明导电层可以是ITO或IZO。在透明导电层上涂敷一层光刻胶;采用掩膜板对光刻胶进行曝光,显影,使光刻胶形成光刻胶不保留区域和光刻胶保留区域,其中,光刻胶保留区域对应于像素电极4所在区域,光刻胶不保留区域对应于其他区域;通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的透明导电层,剥离剩余的光刻胶,形成像素电极4。
步骤e、如图8所示,通过一次构图工艺在经过步骤d的衬底基板100上形成数据线、源电极2和漏电极3的图案;
具体地,可以在经过步骤d的衬底基板100上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为的源漏金属层,源漏金属层可以是Cu,Al,Ag,Mo,Cr,Nd,Ni,Mn,Ti,Ta,W等金属以及这些金属的合金。源漏金属层可以是单层结构或者多层结构,多层结构比如Cu\Mo,Ti\Cu\Ti,Mo\Al\Mo等。
在源漏金属层上涂覆一层光刻胶,采用掩膜板对光刻胶进行曝光,显影,使光刻胶形成光刻胶不保留区域和光刻胶保留区域,其中,光刻胶保留区域对应于数据线、源电极2和漏电极3的所在区域,光刻胶不保留区域对应于其他区域;通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的源漏金属薄膜,剥离剩余的光刻胶,形成数据线、源电极2和漏电极3,如图8所示。
其中,源电极2和数据线电性连接,漏电极3设置于像素电极4上方,并与像素电极4直接搭接,电性连接。
步骤f、如图9所示,通过一次构图工艺在经过步骤e的衬底基板100上形成包括有钝化层过孔8的钝化层101,露出漏电极3;
具体地,在经过步骤e的衬底基板100上采用磁控溅射、热蒸发、PECVD或其它成膜方法沉积厚度为的钝化层101,其中,钝化层101的材料可以选用氧化物、氮化物或氮氧化物,具体地,钝化层101可以是SiNx,SiOx或Si(ON)x。钝化层101可以是单层结构,也可以是采用氮化硅和氧化硅构成的两层结构。
在钝化层101上涂敷一层光刻胶;采用掩膜板对光刻胶进行曝光,显影,使光刻胶形成光刻胶不保留区域和光刻胶保留区域,其中,光刻胶不保留区域对应于钝化层过孔8所在区域,光刻胶保留区域对应于其他区域;通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的钝化层,形成钝化层过孔8,露出漏电极3。剥离剩余的光刻胶。
步骤g、如图3所示,通过一次构图工艺在经过步骤f的衬底基板100上形成公共电极5和电性连接块6的图案,其中,公共电极5为狭缝电极,电性连接块6填充钝化层过孔8,其一端通过钝化层过孔8与漏电极3接触,另一端覆盖在钝化层101的表面,暴露在阵列基板的表面,结合图9所示。
具体地,在经过步骤f的衬底基板100上采用磁控溅射、热蒸发或其它成膜方法沉积厚度为的透明导电层,透明导电层可以是ITO或IZO。在透明导电层上涂敷一层光刻胶;采用掩膜板对光刻胶进行曝光,显影,使光刻胶形成光刻胶不保留区域和光刻胶保留区域,其中,光刻胶保留区域对应于公共电极5和电性连接块6的所在区域,光刻胶不保留区域对应于其他区域;通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的透明导电层,剥离剩余的光刻胶,形成公共电极5和电性连接块6,电性连接块6填充钝化层过孔8,其一端与漏电极3接触,另一端覆盖在钝化层101的表面,暴露在阵列基板的表面,结合图3和图9所示。
至此完成阵列基板的制作。
本发明实施例中还提供一种显示装置,其包括上述的阵列基板。所述阵列基板包括公共电极和一电性连接块,其中,公共电极位于像素电极上方,即公共电极位于阵列基板的最上层。所述电性连接块的一端通过钝化层过孔与像素电极或薄膜晶体管的漏电极接触,另一端暴露在阵列基板的表面。从而测量设备的Pixel探针与电性连接块的接触,能够实现与像素电极或薄膜晶体管的漏电极电性连接,实现对薄膜晶体管电学特性的测量,保证了产品的显示品质。
相应地,结合图1所示,本发明实施例中对阵列基板的电学特性进行测量的方法,包括:
将栅线探针与阵列基板的栅线10接触;
将数据探针与阵列基板的数据线20接触,
将像素探针与电性连接块6接触,对栅线探针和数据线探针加载预设的电压,通过像素探针输出的信号获取薄膜晶体管的电学特性值。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明技术原理的前提下,还可以做出若干改进和替换,这些改进和替换也应视为本发明的保护范围。
Claims (10)
1.一种阵列基板,包括多个像素单元,每个像素单元包括薄膜晶体管、像素电极和公共电极,所述像素电极和薄膜晶体管的上方覆盖有钝化层,所述公共电极位于所述钝化层的上方,并与所述像素电极的位置对应,所述薄膜晶体管的漏电极与所述像素电极电性连接,其特征在于,所述钝化层中形成有钝化层过孔;
每个像素单元还包括填充所述钝化层过孔的电性连接块;
所述电性连接块的一端通过所述钝化层过孔与所述像素电极或漏电极接触设置,另一端暴露在所述阵列基板的表面。
2.根据权利要求1所述的阵列基板,其特征在于,所述电性连接块与公共电极由同一透明导电层通过一次构图工艺同时形成,所述公共电极设置于所述阵列基板的最上层。
3.根据权利要求2所述的阵列基板,其特征在于,所述电性连接块贯穿所述钝化层过孔,且所述电性连接块的一端与所述像素电极或所述漏电极之间的接触面积小于暴露在所述阵列基板的表面的另一端的截面面积,暴露在所述阵列基板的表面的另一端覆盖在所述钝化层的表面。
4.根据权利要求1-3任一项所述的阵列基板,其特征在于,所述薄膜晶体管的漏电极设置于所述像素电极的上方,且与所述像素电极直接搭接;所述电性连接块的一端通过所述钝化层过孔与薄膜晶体管的漏电极接触设置。
5.根据权利要求1-3任一项所述的阵列基板,其特征在于,所述像素电极设置于所述薄膜晶体管的漏电极的上方,且与所述薄膜晶体管的漏电极直接搭接;所述电性连接块的一端通过所述钝化层过孔与所述像素电极接触设置。
6.一种显示装置,其特征在于,包括权利要求1-5任一项所述的阵列基板。
7.一种阵列基板的制作方法,包括:
形成多个像素单元;
形成每个像素单元的步骤包括:
形成薄膜晶体管和像素电极的图案;
在所述像素电极和薄膜晶体管的上方形成钝化层;
在所述钝化层的上方形成公共电极的图案,所述公共电极与像素电极的位置对应,所述薄膜晶体管的漏电极与所述像素电极电性连接,其特征在于,形成每个像素单元的步骤还包括:
对所述钝化层进行构图工艺形成钝化层过孔;
形成一填充所述钝化层过孔的电性连接块,所述电性连接块的一端与所述像素电极或漏电极接触设置,另一端暴露在所述阵列基板的表面。
8.根据权利要求7所述的制作方法,其特征在于,形成所述公共电极和电性连接块的步骤具体为:
在所述钝化层上形成透明导电层;
对所述透明导电层进行构图工艺,形成所述公共电极和电性连接块的图案。
9.根据权利要求8所述的制作方法,其特征在于,所述电性连接块贯穿所述钝化层过孔,且所述电性连接块的一端与所述像素电极或所述漏电极之间的接触面积小于暴露在所述阵列基板的表面的另一端的截面面积,暴露在所述阵列基板的表面的另一端覆盖在所述钝化层的表面。
10.一种对权利要求1-5任一项所述的阵列基板的电学特性进行测量的方法,包括:
将栅线探针与阵列基板的栅线接触;
将数据探针与阵列基板的数据线接触,其特征在于,
所述阵列基板的钝化层中形成有钝化层过孔,所述阵列基板还包括一填充所述钝化层过孔的电性连接块,所述电性连接块的一端通过所述钝化层过孔与所述像素电极或漏电极接触设置,另一端暴露在所述阵列基板的表面;
所述测试方法还包括:
将像素探针与所述电性连接块接触,对栅线探针和数据线探针加载预设的电压,通过像素探针输出的信号获取薄膜晶体管的电学特性值。
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