WO2015027615A1 - 阵列基板及其检测方法和制备方法 - Google Patents

阵列基板及其检测方法和制备方法 Download PDF

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Publication number
WO2015027615A1
WO2015027615A1 PCT/CN2013/089301 CN2013089301W WO2015027615A1 WO 2015027615 A1 WO2015027615 A1 WO 2015027615A1 CN 2013089301 W CN2013089301 W CN 2013089301W WO 2015027615 A1 WO2015027615 A1 WO 2015027615A1
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Prior art keywords
line
thin film
film transistor
detection line
array substrate
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PCT/CN2013/089301
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English (en)
French (fr)
Inventor
李梁梁
郭总杰
丁向前
刘耀
白金超
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/404,180 priority Critical patent/US10490109B2/en
Publication of WO2015027615A1 publication Critical patent/WO2015027615A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136272—Auxiliary lines

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of detecting the same and a method of fabricating the same. Background technique
  • the flat panel display device Compared with the conventional cathode ray tube display device, the flat panel display device has the advantages of light weight, low driving voltage, no flickering jitter, and long service life.
  • the flat panel display device can be classified into an active light emitting display device and a passive light emitting display device.
  • a thin film transistor liquid crystal display device (TFT-LCD) is a passive light emitting display device.
  • TFT-LCD has been widely used in electronic products such as TVs, mobile phones, and display devices because of its stable image, vivid image, low radiation, space saving, and energy saving. It has occupied a dominant position in the field of flat display.
  • the liquid crystal display device mainly includes a liquid crystal display panel and a driving device for driving the liquid crystal display panel.
  • the liquid crystal display panel mainly includes a first substrate and a second substrate disposed opposite to each other; generally, the first substrate and the second substrate are an array substrate and a color film substrate, respectively.
  • the array substrate includes a plurality of data lines arranged in a crisscross pattern and a plurality of gate lines, the data lines and the gate lines defining a plurality of pixel units.
  • the manufacturing process of the liquid crystal display panel is mainly divided into a front-end array (Array) process, a middle-stage cell (Cell) process, and a rear-end module assembly process.
  • Array front-end array
  • Cell middle-stage cell
  • rear-end module assembly process In order to reduce the difficulty of detecting the picture of the liquid crystal display panel in the array process and the box process, and reducing the cost of the detection device, one of the most commonly used methods in the industry is to provide a shorting bar area on the array substrate, that is, on the array substrate.
  • the lines around the data lines and the gate lines form some lines for testing.
  • a first detecting line 3 and a second detecting line 4 are formed on the periphery of the array substrate.
  • the first detection line 3 is used for signal testing of all odd-numbered column data lines
  • the second detection line 4 is used for signal testing of all even-numbered column data lines.
  • To measure the resistance between two adjacent data lines for example, two probes of the multimeter are respectively contacted with the adjacent two data lines, and according to the obtained resistance value, it can be judged whether a short circuit occurs between the two data lines. For example, if the detected resistance value is large, it means that no short circuit occurs, and if the detected resistance value is small, it is basically judged that a short circuit has occurred.
  • the shorting bar area is disposed on the periphery of the liquid crystal display panel, and is needed for the convenience of testing, It is connected to a large number of data lines or gate lines in the liquid crystal display panel, so that the electrostatic charge is easily accumulated.
  • static electricity causes electrostatic breakdown in a region where metal lines overlap, causing defects such as short circuits or open circuits.
  • some of the shorting bar regions are located at the edge of the array substrate, many processes are unstable at the edge positions. For example, when an aluminum component is used as the material of the detection line, there is a problem such as a hillock at the edge position, so that electrostatic breakdown is more likely to occur, and the short-circuit strip region is defective.
  • a defect in the shorting bar area causes the entire liquid crystal display panel to be judged as a defective product at the time of testing.
  • the short-circuit strip area is cut off at the final product, which does not affect the display effect of the final display device, thus causing a false positive. That is, this may misidentify a part of the liquid crystal display panel but the defective product in the short-circuit strip area as a defective product, which affects the yield of the display device on the one hand and serious waste on the other hand.
  • Embodiments of the present invention provide an array substrate for reducing or avoiding the problem that a qualified product is misjudged as a defective product due to a defect in the shorting bar area. Embodiments of the present invention also provide a method and a method for detecting the array substrate.
  • An aspect of the present invention provides an array substrate including a first detection line, a second detection line, and first and second data lines disposed therebetween; the first data line is directly connected to the first detection line The second data line is connected to the second detection line through the switching element; or the second data line is directly connected to the second detection line, and the first data line is connected to the first detection line through the switching element.
  • the array substrate may further include a control line of the switching element, the switching element being a first thin film transistor; and a gate of the first thin film transistor is connected to the control line.
  • the switching element may be a first thin film transistor
  • the first detecting line is also used as a control line of the switching element
  • a gate of the first thin film transistor is connected to the first detecting line.
  • the array substrate may further include a gate metal layer and a source/drain metal layer; the control line is disposed in the same layer as the gate metal layer; and the second detection line and a source of the first thin film transistor Connected, the second data line is connected to a drain of the first thin film transistor.
  • the second detecting line may be disposed in the same layer as the source/drain metal layer, and the first data line and the second data line may be disposed in the same layer as the source/drain metal layer;
  • the detecting line is directly connected to the first data line through a via, and the second detecting line is extremely integrated with a source of the first thin film transistor.
  • the second detecting line may be disposed in the same layer as the gate metal layer, and the first data line and the second data line may be disposed in the same layer as the source/drain metal layer, the first The detection line is directly connected to the first data line through a via, and the second detection line is connected to a source of the first thin film transistor through a via.
  • control line may be integrated with the gate of the first thin film transistor.
  • the array substrate may include a second thin film transistor arranged in an array of display regions; the first thin film transistor and the second thin film transistor have the same configuration.
  • Another aspect of the present invention provides a method for detecting any one of the above array substrates, comprising: inputting a data signal at one of a first detection line and a second detection line connected to the switching element, and another detecting The line has no signal input to turn off the switching element; if a data signal can be detected in the display area of the array substrate, it is determined that the first detection line and the second detection line are short-circuited.
  • Another aspect of the present invention provides a method for fabricating an array substrate, including: a second thin film transistor located in a display region; and a first detection line, a second detection line, and first and second data lines disposed between the peripheral regions; The first data line is directly connected to the first detection line, and the second data line is connected to the second detection line through a switching element; or the second data line is directly connected to the line And a second detecting line, wherein the first data line is connected to the first detecting line through a switching element.
  • the switching element may be a first thin film transistor.
  • the first thin film transistor is formed while forming the second thin film transistor.
  • a first detection line, a gate metal layer of the first thin film transistor and the second thin film transistor, and a control line are formed on the substrate of the substrate; a gate insulating layer covering the entire substrate is formed; and the first film is formed An active layer of the transistor and the second thin film transistor; forming a first data line, a second data line, a second detecting line, and a source/drain metal layer of the first thin film transistor and the second thin film transistor; forming a passivation layer and a via.
  • a first detection line, a second detection line, a gate metal layer of the first thin film transistor and the second thin film transistor, and a control line are formed on the substrate of the substrate; and a gate insulating layer covering the entire substrate is formed Forming an active layer of the first thin film transistor and the second thin film transistor; forming the first a data line, a second data line, and a source/drain metal layer of the first thin film transistor and the second thin film transistor; forming a passivation layer and a via.
  • control line and the gate of the first thin film transistor may be arranged in a unitary structure.
  • control line may be the first detection line.
  • 1 is a partial schematic view of a conventional array substrate
  • FIG. 2 is a schematic view showing electrostatic breakdown of a conventional array substrate
  • FIG. 3a is a schematic structural view of an array substrate according to Embodiment 1 of the present invention.
  • 3b is a schematic structural view of an array substrate according to Embodiment 2 of the present invention.
  • 4a-4d are schematic structural views of an array substrate formed at each stage of the method for fabricating an array substrate according to Embodiment 3 of the present invention.
  • an array substrate is first provided, the array substrate having a display area and a peripheral area surrounding the display area.
  • the array substrate comprises a plurality of gate lines and a plurality of data lines arranged in a crisscross pattern, wherein the data lines and the gate lines intersect in the display area to define one pixel area, each pixel
  • the regions are each provided with a second thin film transistor (pixel switching thin film transistor); the above data line includes a first data line and a second data line disposed between the phases.
  • the data lines of all the odd columns in this embodiment are referred to as the first data lines, and the data lines of all the even columns are referred to as the second data lines; of course, the data lines of all the even columns may also be referred to as the first data lines.
  • the data lines of all odd columns are referred to as second data lines and the like.
  • a first detection line, a second detection line, and a switching element are further provided, and the first detection line and the second detection line are insulated from each other.
  • the first data line is directly connected to the first detection line, and the second data line is connected to the second detection line through the switching element; or the second data line is directly connected to the second detection line, and the first data line is connected to the second through the switching element A test line.
  • the above switching elements may be thin film transistors or other controllable analog switches.
  • the array substrate provided in this embodiment is described below by connecting the first data line directly to the first detection line, the second data line being connected to the second detection line through the switching element, and the switching element being the first thin film transistor as an example.
  • each of the first data lines 1 is directly connected to the first detecting line 3 through a via 5 and a connecting line 6; each of the second data lines 2 is connected to the drain of a first thin film transistor 7.
  • the second detecting line 4 is connected to the source of the first thin film transistor 7, and the gate of the first thin film transistor 7 is connected to the control line.
  • the control line is similar to the action of the gate line in the display area of the array substrate (controlling the turn-off of the pixel switching thin film transistor) for controlling the turn-on and turn-off of the first thin film transistor.
  • the control line for the first thin film transistor is the same as the first detecting line 3, that is, the first detecting line 3 is also used as the control line at the same time.
  • a portion of the first detecting line 3 serves as the gate of the first thin film transistor 7.
  • the gate of the first thin film transistor 7 may also be an electrode portion formed by extending from the first detecting line 3.
  • the display region of the array substrate includes a gate metal layer (including a gate and a gate line), a gate insulating layer, an active layer, and a source/drain metal layer (including a source and a drain) which are sequentially disposed from bottom to top on the base substrate. ), the data line, the passivation layer, the transparent electrode layer, and the like; the first detecting line 3 in this embodiment is disposed in the same layer as the gate metal layer and has the same material, the second detecting line 4 and the source/drain metal layer and the data line Same layer settings and the same material. Since the gate insulating layer is disposed between the first detecting line 3 and the second detecting line 4, the first detecting line 3 and the second detecting line 4 are insulated from each other.
  • the gate metal layer and the first detecting line 3 may be simultaneously formed at one time, that is, the first detecting line and the gate of the first thin film transistor are integrated,
  • the control line is the first detection line.
  • the source/drain metal layer, the data line, and the second detecting line 4 are simultaneously formed at one time; at the same time, since the second detecting line 4 and the data line are disposed in the same layer, the second data line 2 and the second detecting line 4 are facilitated. connection.
  • the first thin film transistor 7 in this embodiment may be identical in construction to the second thin film transistor of the array substrate display region.
  • the gate metal layer of the second thin film transistor and the gate metal layer of the first thin film transistor 7 may be simultaneously formed, and the gate insulating layer of the second thin film transistor and the gate insulating layer of the first thin film transistor 7 may be simultaneously formed,
  • the active layer, the source/drain metal layer of the second thin film transistor and the active layer and the source/drain metal layer of the first thin film transistor 7 may be simultaneously formed. Therefore, it is not necessary to separately increase the process step of forming the first thin film transistor 7; further, the source/drain metal layer, the second data line 2, and the second detecting line 4 of the first thin film transistor 7 are disposed in the same layer to facilitate the corresponding connection.
  • the second detecting line 4 is integrally formed with the source of the first thin film transistor 7
  • the second data line 2 is integrally formed with the drain of the first thin film transistor 7, and the like.
  • the first detecting line 3, the second detecting line 4, and the switching element are used only for the array substrate test, are etched away in the post process, or are removed by physical methods such as substrate cutting and laser cutting, so that the molding is not affected. Normal signal transmission of the array substrate.
  • This embodiment is a variant of the first embodiment, except that the control line is formed separately from the first detection line.
  • each of the first data lines 1 is directly connected to the first detecting line 3 through one via 5 and one connecting line 6; each of the second data lines 2 is connected to the drain of one of the first thin film transistors 7.
  • the second detecting line 4 is connected to the source of the first thin film transistor 7, and the gate of the first thin film transistor 7 is connected to the control line 31.
  • the control line 31 of the first thin film transistor and the first detecting line 3 are formed in parallel with each other.
  • a part of the control line 31 serves as the gate of the first thin film transistor 7.
  • the gate of the first thin film transistor 7 may also be an electrode portion formed by extending from the control line 31.
  • the first detecting line 3 and the control line 31 are formed to be parallel to each other as shown in Fig. 3b, for example, the first detecting line 3 and the control line 31 are disposed in the same layer as the gate metal layer and have the same material.
  • a method for preparing any one of the above array substrates is further provided; the difference between the method for fabricating the array substrate and the method for preparing a conventional array substrate is mainly:
  • the switching element is the first thin film transistor 7 and is formed simultaneously with the second thin film transistor of the display region.
  • Step 1 A first detecting line 3, a gate metal layer of the first thin film transistor 7 and the second thin film transistor, and a control line are formed on the substrate of the substrate by a patterning process such as deposition, exposure, etching, development, and the like. If the first detecting line 3 is the control line of the first thin film transistor 7, the first detecting line 3 is integrally formed with the gate metal layer (gate) of the first thin film transistor 7, or the gate of the first thin film transistor 7 is An electrode portion extending from the first detection line 3.
  • a patterning process such as deposition, exposure, etching, development, and the like.
  • the first detecting line 3 is formed separately from the control line of the first thin film transistor 7, the two are formed in parallel with each other, the control line is formed integrally with the gate metal layer of the first thin film transistor, or the gate of the first thin film transistor is controlled from The electrode portion from which the wire extends.
  • a metal thin film is deposited on the substrate of the village by magnetron sputtering or thermal evaporation; a layer of photoresist is coated on the metal film; and exposure is performed by using a common mask (monotone mask) to form Corresponding to the first detecting line 3, the gate metal layer of the first thin film transistor 7, the gate metal layer of the second thin film transistor, and the photoresist remaining region of the control line and the photoresist removing region corresponding to the region outside the above region.
  • a common mask monotone mask
  • the photoresist is developed; after the development process, the thickness of the photoresist in the photoresist retention region is not changed, the photoresist in the photoresist removal region is removed; after the development process, the photoresist is removed by an etching process Removing the metal film of the region; finally stripping the remaining photoresist, leaving the metal film including the first detecting line 3 as shown in FIG. 4a, the gate metal layer of the first thin film transistor 7, and the second thin film transistor The gate metal layer and the control line.
  • Step 2 A gate insulating layer covering the entire substrate of the substrate is formed.
  • the gate insulating layer may be an inorganic insulating layer such as silicon oxide or silicon nitride, or may be an organic insulating layer.
  • Step 3 forming an active layer of the first thin film transistor and an active layer of the second thin film transistor and forming source and drain metals of the first data line 1, the second data line 2, the second detecting line 4, and the first thin film transistor The source and drain metal layers of the layer and the second thin film transistor.
  • a semiconductor layer and a doped semiconductor layer are sequentially deposited on the gate insulating layer by a method such as chemical vapor deposition; then a metal thin film is deposited by magnetron sputtering or thermal evaporation; Coating a layer of photoresist on the film; exposing through the two-tone mask to form a source/drain metal layer corresponding to the first thin film transistor and the second thin film transistor, the first data line L, the second data line 2, and the second detecting line 4
  • the photoresist completely retains the region, corresponding to the channel domains of the first thin film transistor and the second thin film transistor.
  • the thickness of the photoresist in the completely remaining region of the photoresist is not changed, the photoresist in the completely removed region of the photoresist is completely removed, and the thickness of the photoresist in the semi-reserved region of the photoresist is thinned;
  • the sub-etching process removes the metal thin film, the doped semiconductor layer, and the semiconductor layer in the completely removed region of the photoresist to form an active layer pattern of the active layer of the first thin film transistor and the second thin film transistor.
  • Step 4 A passivation layer is formed and a via 5 as shown in Fig. 4c.
  • a via 5 exposing the first data line 1 and the first detecting line 3 is then formed on the passivation layer by a two-color mask process.
  • Step 5 A transparent electrode and a connecting wire are formed.
  • a transparent metal thin film is deposited on the passivation layer by chemical vapor deposition or other methods; then a common wiring mask process is used to form a connecting line 6 and a transparent electrode as shown in FIG. 4d on the transparent metal film; 6 connects the first data line 1 and the first detection line 3 through the via 5 .
  • the second detecting line is disposed in the same layer as the source/drain metal layer.
  • the second detecting line may also be disposed in the same layer as the gate metal layer, and the first detecting line is directly connected to the first data line through the via hole.
  • the second detecting line is connected to the source of the first thin film transistor through the via.
  • the preparation method of the array substrate also needs to be adjusted.
  • the preparation method of the exemplary array substrate can be performed as follows.
  • first detection line, a second detection line, a first thin film transistor, and a second thin film on the substrate of the substrate a gate metal layer of the film transistor and a control line; forming a gate insulating layer covering the entire substrate substrate; forming an active layer of the first thin film transistor and the second thin film transistor; forming a first data line, a second data line, and the first a source/drain metal layer of the thin film transistor and the second thin film transistor; forming a passivation layer and a via hole, the first detecting line is directly connected to the first data line through the via hole, and the second detecting line passes through the via hole and the source of the first thin film transistor Extremely connected.
  • the method for preparing an array substrate in this embodiment is only one implementation method for preparing the array substrate provided by the present invention. In actual use, the number of patterning processes can be increased or decreased, and different embodiments are selected.
  • the embodiment further provides a method for detecting any one of the above array substrates; the array substrate detecting method can be performed as follows.
  • the first detection line 3 and the control line when the first detection line 3 and the control line are formed separately, a data signal is input to the first detection line 3 and the second detection line 4, and a high level signal is turned on at the control line.
  • the first thin film transistor 7 can load data signals to all of the data lines on the array substrate to detect defects in the respective pixel regions. At this time, the resistance between the adjacent two data lines is tested. For example, the two probes of the multimeter respectively contact the two adjacent data lines, and when the resistance between the adjacent two data lines is detected, It can be preliminarily judged that there is a short circuit between the two data lines.
  • the array substrate detecting method in this embodiment, the input of the data signal at the first detection line 3 is stopped and the control signal is stopped at the control line, and the first thin film transistor 7 is turned off; if the data signal can be detected in the display area of the array substrate at this time, the second detection line 4 is illustrated.
  • the input data signal is shunted to the first detection line 3, that is, the first detection line 3 and the second detection line 4 can be short-circuited; if the data signal cannot be detected in the display area of the array substrate at this time, the description is indeed the above phase.
  • a short circuit failure occurs between the adjacent data lines, and the product can be judged as a defective product; it can be clearly seen that the detection method of the embodiment can greatly reduce the false detection rate.
  • the control line is the first detection line 3
  • the first detection line 3 inputs a low level signal, that is, stops inputting the data signal to the first detecting line 3, and the first thin film transistor 7 can be turned off. Therefore, the first detecting line 3 is used as the control line, on the one hand, the additional control line is avoided, the structure of the array substrate is compressed, the production cost is reduced, and the manufacturing process difficulty of the array substrate is reduced; on the other hand, since no additional is needed Applying a control signal to the first thin film transistor 7 greatly reduces the difficulty of control and the cost of driving.
  • the array substrate and the array substrate detecting method provided by the present invention can determine whether the short circuit of the first detecting line 3 and the second detecting line 4 is short, thereby avoiding the first detecting line 3 and the second detecting.
  • the short circuit of line 4 causes the qualified product to be misjudged as a defective product; and, outside the test process, since the switching element is in the off state, that is, the connection between the test line and the corresponding data line of the switching element is disconnected. This avoids the transfer of charge from the display area to the test line, reduces the accumulation of static electricity, and improves the reliability of the short-circuit strip area.

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Abstract

提供了一种阵列基板及其检测方法和制备方法。阵列基板包括第一检测线（3）、第二检测线（4）以及相间设置的第一数据线（1）和第二数据线（2）；第一数据线（1）直接连接至第一检测线（3），第二数据线（2）通过开关元件（7）连接至第二检测线（4）；或者，第二数据线（2）直接连接至第二检测线（4），第一数据线（1）通过开关元件（7）连接至第一检测线（3）。因此，这样的阵列基板可以避免显示区域电荷传递到测试线上，减少了静电积累，提升了短路条区域的可靠性。

Description

阵列基板及其检测方法和制备方法 技术领域
本发明的实施例涉及一种阵列基板以及该阵列基板的检测方法和制备方 法。 背景技术
平板显示装置相比与传统的阴极射线管显示装置具有轻薄、驱动电压低、 没有闪烁抖动以及使用寿命长等优点。 平板显示装置可以分为主动发光显示 装置与被动发光显示装置。 例如， 薄膜晶体管液晶显示装置 (TFT-LCD)就是 一种被动发光显示装置。 由于其具有画面稳定、 图像逼真、 辐射小、 节省空 间以及节省能耗等优点， TFT-LCD被广泛应用于电视、 手机、 显示装置等电 子产品中， 已占据了平面显示领域的主导地位。
液晶显示装置主要包括液晶显示面板以及驱动该液晶显示面板的驱动装 置。 液晶显示面板主要包括相对设置的第一基板和第二基板； 通常， 第一基 板和第二基板分别为阵列基板和彩膜基板。 阵列基板包括纵横交错设置的多 条数据线以及多条栅线， 这些数据线和栅线限定出多个像素单元。
液晶显示面板的制作工艺主要分为前段阵列 (Array)制程、中段成盒 (Cell) 制程及后段模组组装制程等。 为了减少阵列制程和成盒制程中液晶显示面板 画面检测的难度以及减少检测设备费用， 目前业界最常采用的方法之一是在 阵列基板上设置短路条 (shorting bar)区域，即在阵列基板上的数据线和栅线等 线路的外围形成出一些用来测试的线路。
如图 1所示，在阵列基板的外围形成有第一检测线 3以及第二检测线 4。 第一检测线 3用于对所有奇数列数据线进行信号测试， 第二检测线 4用于对 所有偶数列数据线进行信号测试。 为测量相邻两条数据线间的电阻， 例如万 用表的两根探针分别接触上述相邻的两条数据线， 根据得到的电阻值就可以 判断这两条数据线之间是否有短路发生。 例如， 检测到的电阻值 ^艮大， 则说 明无短路发生， 而检测到的电阻值很小， 则基本可以判断发生了短路。
由于短路条区域设置在液晶显示面板的外围， 而且为了方便测试， 需要 与液晶显示面板中的大量的数据线或者栅线相连， 这样 ^艮容易造成静电电荷 积累。 例如， 如图 2所示， 这种静电会致使在金属线交叠的区域发生静电击 穿， 造成短路或断路等不良。 而且， 由于一些短路条区域位于在阵列基板的 边缘位置， 很多工艺处理在边缘位置都很不稳定。 例如， 采用铝成分作为检 测线的材质时， 由于边缘位置存在突出部 (hillock)等问题，这样更加容易发生 静电击穿， 使短路条区域发生不良。 短路条区域的不良会致使整个液晶显示 面板在测试的时候被判成不良品。 但是， 短路条区域在最后成品时是被切割 掉的， 不会影响最终显示装置的显示效果， 这样就造成了误判。 也即， 这可 能将一部分液晶显示面板合格但是短路条区域存在不良的产品误判为不合格 产品， 一方面影响了显示装置的良品率， 另一方面造成了严重的浪费。 发明内容
本发明的实施例提供了一种阵列基板， 用于减少或者避免由于短路条区 域的不良造成合格产品被误判为不合格产品的问题。 本发明的实施例还提供 了一种该阵列基板的检测方法和制备方法。
本发明的一个方面提供了一种阵列基板， 其包括第一检测线、 第二检测 线以及相间设置的第一数据线和第二数据线； 所述第一数据线直接连接至第 一检测线， 第二数据线通过开关元件连接至第二检测线； 或者， 所述第二数 据线直接连接至第二检测线， 第一数据线通过开关元件连接至第一检测线。
例如， 该阵列基板还可以包括所述开关元件的控制线， 所述开关元件为 第一薄膜晶体管； 所述第一薄膜晶体管的栅极连接至所述控制线。
例如， 该阵列基板中， 所述开关元件可以为第一薄膜晶体管， 所述第一 检测线还作为所述开关元件的控制线， 所述第一薄膜晶体管的栅极连接至所 述第一检测线。例如，所述阵列基板还可以包括栅极金属层以及源漏金属层； 所述控制线与所述栅极金属层同层设置； 所述第二检测线与所述第一薄膜晶 体管的源极连接， 所述第二数据线与所述第一薄膜晶体管的漏极连接。
例如，该阵列基板中，所述第二检测线可以与所述源漏金属层同层设置， 所述第一数据线以及第二数据线可以与源漏金属层同层设置； 所述第一检测 线通过过孔与所述第一数据线直接连接， 所述第二检测线与所述第一薄膜晶 体管的源极为一体结构。 例如，该阵列基板中，所述第二检测线可以与所述栅极金属层同层设置， 所述第一数据线以及第二数据线可以与源漏金属层同层设置， 所述第一检测 线通过过孔与所述第一数据线直接连接， 所述第二检测线通过过孔与所述第 一薄膜晶体管的源极连接。
例如， 该阵列基板中， 所述控制线可以与所述第一薄膜晶体管的栅极为 一体结构。
例如， 所述阵列基板可以包括在显示区域阵列排布的第二薄膜晶体管； 所述第一薄膜晶体管与第二薄膜晶体管构造相同。
本发明的另一个方面还提供了对上述任意一种阵列基板的进行检测的方 法， 包括： 在与所述开关元件连接的第一检测线和第二检测线之一输入数据 信号， 另一检测线无信号输入， 以关断所述开关元件； 若在所述阵列基板的 显示区域可以检测到数据信号， 则判断所述第一检测线与第二检测线发生短 路。
本发明的另一个方面提供了一种阵列基板制备方法； 包括位于显示区域 的第二薄膜晶体管以及位于外围区域的第一检测线、 第二检测线以及相间设 置的第一数据线和第二数据线； 其中， 所述第一数据线直接连接至所述第一 检测线， 所述第二数据线通过开关元件连接至第二检测线； 或者， 所述第二 数据线直接连接至所述第二检测线， 所述第一数据线通过开关元件连接至所 述第一检测线。
例如， 该方法中， 所述开关元件可以为第一薄膜晶体管。
例如， 该方法中， 在形成所述第二薄膜晶体管的同时形成所述第一薄膜 晶体管。
例如， 该方法中， 在村底基板上形成第一检测线、 第一薄膜晶体管和第 二薄膜晶体管的栅极金属层以及控制线；形成覆盖整个村底基板的栅绝缘层； 形成第一薄膜晶体管和第二薄膜晶体管的有源层； 形成第一数据线、 第二数 据线、 第二检测线以及第一薄膜晶体管和第二薄膜晶体管的源漏金属层； 形 成钝化层以及过孔。
例如， 该方法中， 在村底基板上形成第一检测线、 第二检测线、 第一薄 膜晶体管和第二薄膜晶体管的栅极金属层以及控制线； 形成覆盖整个村底基 板的栅绝缘层； 形成第一薄膜晶体管和第二薄膜晶体管的有源层； 形成第一 数据线、 第二数据线以及第一薄膜晶体管和第二薄膜晶体管的源漏金属层； 形成钝化层以及过孔。
例如， 该方法中， 设置所述控制线与所述第一薄膜晶体管的栅极可以为 一体结构。
例如， 该方法中， 所述控制线可以为所述第一检测线。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1是一种传统的阵列基板的局部示意图；
图 2是传统的阵列基板发生静电击穿的示意图；
图 3a是本发明实施例一的阵列基板的结构示意图；
图 3b是本发明实施例二的阵列基板的结构示意图；
图 4a-4d是本发明实施例三的阵列基板制备方法各阶段形成的阵列基板 结构示意图。
附图标记：
1: 第一数据线； 2: 第二数据线； 3: 第一检测线； 4: 第二检测线； 5: 过孔； 6: 连接线； 7: 第一薄膜晶体管。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
实施例一
本实施例中首先提供了一种阵列基板， 该阵列基板具有显示区域和围绕 在显示区域之外的外围区域。 该阵列基板包括纵横交错设置的多条栅线和多 条数据线， 在显示区域数据线和栅线交叉限定出一个个像素区域， 每个像素 区域均设置有第二薄膜晶体管 (像素开关薄膜晶体管)； 上述数据线包括相间 设置的第一数据线和第二数据线。 例如， 本实施例中所有奇数列的数据线称 为第一数据线， 所有偶数列的数据线称为第二数据线； 当然， 也可以是所有 偶数列的数据线称为第一数据线，所有奇数列的数据线称为第二数据线等等。 在阵列基板的外围区域中，还设置有第一检测线、第二检测线以及开关元件， 第一检测线和第二检测线相互绝缘。 第一数据线直接连接至第一检测线， 第 二数据线通过开关元件连接至第二检测线； 或者， 第二数据线直接连接至第 二检测线， 第一数据线通过开关元件连接至第一检测线。 为了方便控制， 上 述开关元件可以是薄膜晶体管或者其他可控模拟开关。
下面以第一数据线直接连接至第一检测线， 第二数据线通过开关元件连 接至第二检测线， 开关元件为第一薄膜晶体管为例对本实施例所提供的阵列 基板进行说明。
如图 3a所示，第一数据线 1每条通过一个过孔 5以及一条连接线 6直接 连接至第一检测线 3; 第二数据线 2每条连接至一个第一薄膜晶体管 7的漏 极， 第二检测线 4连接至该第一薄膜晶体管 7的源极， 第一薄膜晶体管 7的 栅极连接至控制线。控制线与阵列基板的显示区域中的栅线的作用 (控制像素 开关薄膜晶体管的关断)类似， 用于控制第一薄膜晶体管的导通与关断。例如 在控制线中输入高电平信号时第一薄膜晶体管 7导通， 在控制线中输入低电 平信号， 即无信号输入时， 第一薄膜晶体管 7关断。 在本实施例中， 用于第 一薄膜晶体管的控制线与第一检测线 3为同一条， 也即， 第一检测线 3还同 时用作控制线。 如图 3a所示， 第一检测线 3的一部分作为第一薄膜晶体管 7 的栅极。 第一薄膜晶体管 7的栅极也可以是从第一检测线 3延伸出来而形成 的电极部分。
例如， 阵列基板的显示区域包括在基底基板上从下至上依次设置的栅极 金属层 (包括栅极和栅线）、栅绝缘层、有源层、源漏金属层（包括源极和漏极)、 数据线、 钝化层以及透明电极层等等； 本实施例中的第一检测线 3与栅极金 属层同层设置且材质相同， 第二检测线 4与源漏金属层以及数据线同层设置 且材质相同。 由于第一检测线 3和第二检测线 4之间设置有栅绝缘层， 因此， 第一检测线 3和第二检测线 4彼此绝缘。 例如， 可以一次性同时形成栅极金 属层和第一检测线 3 , 即第一检测线与第一薄膜晶体管的栅极为一体结构， 例如， 所述控制线就为所述第一检测线。 例如，一次性同时形成源漏金属层、 数据线和第二检测线 4; 同时， 由于第二检测线 4和数据线属同层设置， 方 便了第二数据线 2与第二检测线 4的连接。 这样， 不必单独增加形成第一检 测线 3以及第二检测线 4的工艺步骤。 为了方便形成以及减少工艺步骤， 本 实施例中的第一薄膜晶体管 7可以与阵列基板显示区域的第二薄膜晶体管构 造相同。 也即， 第二薄膜晶体管的栅极金属层与第一薄膜晶体管 7的栅极金 属层可以同时形成， 第二薄膜晶体管的栅绝缘层与第一薄膜晶体管 7的栅绝 缘层可以同时形成， 第二薄膜晶体管的有源层、 源漏金属层与第一薄膜晶体 管 7的有源层、 源漏金属层可以同时形成。 这样就不必单独增加形成第一薄 膜晶体管 7的工艺步骤； 而且， 第一薄膜晶体管 7的源漏金属层、 第二数据 线 2以及第二检测线 4均同层设置， 方便实现相应的连接， 例如， 第二检测 线 4与第一薄膜晶体管 7的源极一体形成， 第二数据线 2与第一薄膜晶体管 7的漏极一体形成等等。
上述第一检测线 3、第二检测线 4以及开关元件等仅用于阵列基板测试， 在后工艺中被刻蚀掉， 或者通过基板切割以及激光切割等物理方法去除， 因 此不会影响成型的阵列基板的正常信号传输。
实施例二
本实施例为实施例一的变体， 区别在于控制线与第一检测线分开形成。 如图 3b所示，第一数据线 1每条通过一个过孔 5以及一条连接线 6直接连接 至第一检测线 3; 第二数据线 2每条连接至一个第一薄膜晶体管 7的漏极， 第二检测线 4连接至该第一薄膜晶体管 7的源极， 第一薄膜晶体管 7的栅极 连接至控制线 31。 在本实施例中， 第一薄膜晶体管的控制线 31与第一检测 线 3彼此平行形成。 如图 3b所示， 控制线 31的一部分作为第一薄膜晶体管 7的栅极。第一薄膜晶体管 7的栅极也可以是从控制线 31延伸出来而形成的 电极部分。
在形成如图 3b所示的第一检测线 3与控制线 31彼此平行的情形时， 例 如第一检测线 3、 控制线 31与栅极金属层同层设置且材质相同。
实施例三
本实施例中还提供了一种制备上述任意一种阵列基板的方法； 该阵列基 板制备方法与常规的阵列基板制备方法的不同之处主要在于， 除了形成位于 显示区域的第二薄膜晶体管之外， 还需要形成上述开关元件。 为了筒化工艺 流程， 本实施例的一个示例中， 开关元件为第一薄膜晶体管 7且和显示区域 的第二薄膜晶体管同时形成。 本实施例的示例性的阵列基板的制备方式， 如 图 4a-图 4b中所示， 可如下进行。
(步骤 1)通过沉积、 曝光、 刻蚀、 显影等构图工艺， 在村底基板上形成第 一检测线 3、第一薄膜晶体管 7和第二薄膜晶体管的栅极金属层以及控制线。 如果第一检测线 3即作为第一薄膜晶体管 7的控制线， 则第一检测线 3与第 一薄膜晶体管 7的栅极金属层 (栅极)一体形成， 或者第一薄膜晶体管 7的栅 极为从第一检测线 3延伸出来的电极部分。 如果第一检测线 3与第一薄膜晶 体管 7的控制线分开形成， 则二者彼此平行形成， 控制线与第一薄膜晶体管 的栅极金属层一体形成， 或者第一薄膜晶体管的栅极为从控制线延伸出来的 电极部分。
例如， 采用磁控溅射或热蒸发等方法在村底基板上沉积一层金属薄膜； 在金属薄膜上涂布一层光刻胶； 采用普通掩膜板 (单色调掩模板)进行曝光， 形成对应第一检测线 3、 第一薄膜晶体管 7的栅极金属层和第二薄膜晶体管 的栅极金属层以及控制线的光刻胶保留区域以及对应上述区域之外区域的光 刻胶去除区域。
对光刻胶进行显影处理； 显影处理后， 光刻胶保留区域的光刻胶厚度没 有变化， 光刻胶去除区域的光刻胶被去除； 在显影处理后， 通过刻蚀工艺去 除光刻胶去除区域的金属薄膜； 最后剥离剩余的光刻胶， 留下的金属薄膜即 包括如图 4a中所示的第一检测线 3、第一薄膜晶体管 7的栅极金属层和第二 薄膜晶体管的栅极金属层以及控制线。
(步骤 2)形成覆盖整个村底基板的栅绝缘层。
例如， 该栅绝缘层可以为例如氧化硅、 氮化硅等无机绝缘层， 或者可以 为有机绝缘层。
(步骤 3)形成第一薄膜晶体管的有源层和第二薄膜晶体管的有源层以及 形成第一数据线 1、第二数据线 2、第二检测线 4以及第一薄膜晶体管的源漏 金属层和第二薄膜晶体管的源漏金属层。
例如， 采用化学气相沉积法等方法在栅绝缘层上依次沉积半导体层以及 掺杂半导体层； 然后采用磁控溅射或热蒸发等方法沉积金属薄膜； 在金属薄 膜上涂覆一层光刻胶； 通过双色调掩模板曝光， 形成对应第一薄膜晶体管和 第二薄膜晶体管的源漏金属层、 第一数据线 L 第二数据线 2以及第二检测 线 4的光刻胶完全保留区域、 对应第一薄膜晶体管和第二薄膜晶体管的沟道 域。
显影处理后， 光刻胶完全保留区域的光刻胶厚度没有变化， 光刻胶完全 去除区域的光刻胶被完全去除， 光刻胶半保留区域的光刻胶厚度变薄； 然后 通过第一次刻蚀工艺去除光刻胶完全去除区域的金属薄膜、 掺杂半导体层以 及半导体层,形成第一薄膜晶体管的有源层和第二薄膜晶体管的有源层图形。
通过灰化工艺去除光刻胶半保留区域的光刻胶， 暴露出该区域的金属薄 膜； 通过第二次刻蚀工艺去除光刻胶半保留区域的金属薄膜以及掺杂半导体 层，并去除部分厚度的半导体层，形成如图 4b中所示的第一薄膜晶体管和第 二薄膜晶体管的源漏金属层以及沟道区域、 第一数据线 L 第二数据线 2、 第 二检测线 4的图形。
在形成上述结构之后。 剥离剩余的光刻胶。
(步骤 4)形成钝化层以及如图 4c中所示过孔 5。 例如， 在第一薄膜晶体 管和第二薄膜晶体管的源漏金属层以及沟道区域、 第一数据线 i、 第二数据
然后采用双色掩膜板工艺在钝化层上形成暴露出第一数据线 1以及第一检测 线 3的过孔 5。
(步骤 5)形成透明电极以及连接线。例如，在钝化层上采用化学气相沉积 法或者其他方式沉积形成透明金属薄膜； 然后采用普通掩膜板工艺在透明金 属薄膜上形成如图 4d中所示的连接线 6以及透明电极；连接线 6通过过孔 5 将第一数据线 1以及第一检测线 3连接。
在上述阵列基板中， 第二检测线与源漏金属层同层设置， 当然， 第二检 测线也可以与栅极金属层同层设置， 第一检测线通过过孔与第一数据线直接 连接， 第二检测线通过过孔与第一薄膜晶体管的源极连接。 相应的， 该阵列 基板的制备方法也需要做适应性的调整， 例如， 该示范性的阵列基板的制备 方法可以如下进行。
在村底基板上形成第一检测线、 第二检测线、 第一薄膜晶体管和第二薄 膜晶体管的栅极金属层以及控制线； 形成覆盖整个村底基板的栅绝缘层； 形 成第一薄膜晶体管和第二薄膜晶体管的有源层； 形成第一数据线、 第二数据 线以及第一薄膜晶体管和第二薄膜晶体管的源漏金属层； 形成钝化层以及过 孔， 第一检测线通过过孔与第一数据线直接连接， 第二检测线通过过孔与第 一薄膜晶体管的源极连接。
本实施例中的阵列基板制备方法仅仅是制备本发明所提供的阵列基板的 一种实现方法， 实际使用中还可以通过增加或减少构图工艺次数、 选择不同 实施例四
本实施例还提供了对上述任意一种阵列基板的进行检测的方法； 该阵列 基板检测方法， 可如下进行。
在与开关元件连接的第一检测线和第二检测线之一输入数据信号， 另一 检测线无信号输入， 以关断开关元件； 若在阵列基板的显示区域可以检测到 数据信号， 则判断第一检测线与第二检测线发生短路。
例如， 如图 3b所示的示例中， 当第一检测线 3和控制线分开形成时， 在 第一检测线 3和第二检测线 4输入数据信号， 在控制线加载高电平信号导通 第一薄膜晶体管 7, 这样可以向阵列基板上的所有的数据线加载数据信号， 以便检测各个像素区域的不良。 此时， 测试相邻两条数据线间的电阻， 例如 万用表的两根探针分别接触上述相邻的两条数据线， 当检测到相邻两条数据 线间的电阻过 d、时， 就可以初步判断这两条数据线之间是有短路不良发生。 但是， 如果第一检测线 3和第二检测线 4之间存在短路不良， 也可能造成相 邻两条数据线间的电阻过小， 从而导致合格的产品为误判为不合格产品。 因 此， 可以通过本实施例中的阵列基板检测方法进行进一步测试。 例如， 停止 在第一检测线 3输入数据信号并且停止在控制线加载信号， 第一薄膜晶体管 7 关断； 如果此时能够在阵列基板的显示区域检测到数据信号， 则说明第二 检测线 4上输入的数据信号分流到了第一检测线 3 ,即可以判断第一检测线 3 与第二检测线 4发生短路； 如果此时不能在阵列基板的显示区域检测到数据 信号， 说明确实是上述相邻的数据线之间发生了短路不良， 可以将此产品判 为不良品； 可以明显看出， 本实施例的检测方法能够大幅度降低了误检率。
进一步的， 如图 3a所示， 当上述控制线为第一检测线 3时， 在第一检测 线 3输入低电平信号， 即停止向第一检测线 3输入数据信号， 即可关断第一 薄膜晶体管 7。 因此， 将第一检测线 3作为控制线， 一方面避免了额外设置 控制线， 筒化了阵列基板的结构， 降低了生产成本， 同时减少了阵列基板制 备工艺难度； 另一方面， 由于无需额外施加针对第一薄膜晶体管 7的控制信 号， 大幅度降低了控制的难度以及驱动成本。
综上所述， 本发明所提供的阵列基板以及阵列基板检测方法， 可以判断 出是否出现第一检测线 3与第二检测线 4短路不良， 从而避免了由于第一检 测线 3与第二检测线 4短路不良造成合格产品被误判为不合格产品的问题； 并且， 在测试过程之外， 由于开关元件处于关断状态， 即和开关元件的连接 测试线与对应数据线之间是断开的， 这样避免了显示区域电荷传递到测试线 上， 减少了静电积累， 提升了短路条区域的可靠性。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板， 包括第一检测线、第二检测线以及相间设置的第一数 据线和第二数据线；
其中， 所述第一数据线直接连接至所述第一检测线， 所述第二数据线通 过开关元件连接至第二检测线； 或者， 所述第二数据线直接连接至所述第二 检测线， 所述第一数据线通过开关元件连接至所述第一检测线。
2、根据权利要求 1所述的阵列基板，还包括所述开关元件的控制线， 其 中， 所述开关元件为第一薄膜晶体管； 所述第一薄膜晶体管的栅极连接至所 述控制线。
3、根据权利要求 1所述的阵列基板，其中所述开关元件为第一薄膜晶体 管， 所述第一检测线还作为所述开关元件的控制线， 所述第一薄膜晶体管的 栅极连接至所述第一检测线。
4、根据权利要求 2或 3所述的阵列基板，还包括栅极金属层以及源漏金 属层；
其中， 所述控制线与所述栅极金属层同层设置， 所述第二检测线与所述 第一薄膜晶体管的源极连接， 所述第二数据线与所述第一薄膜晶体管的漏极 连接。
5、根据权利要求 4所述的阵列基板， 其中， 所述第二检测线与所述源漏 金属层同层设置， 所述第一数据线以及第二数据线与源漏金属层同层设置； 所述第一检测线通过过孔与所述第一数据线直接连接， 所述第二检测线与所 述第一薄膜晶体管的源极为一体结构。
6、根据权利要求 4所述的阵列基板， 其中， 所述第二检测线与所述栅极 金属层同层设置， 所述第一数据线以及第二数据线与源漏金属层同层设置， 所述第一检测线通过过孔与所述第一数据线直接连接， 所述第二检测线通过 过孔与所述第一薄膜晶体管的源极连接。
7、根据权利要求 5或 6所述的阵列基板， 其中， 所述控制线与所述第一 薄膜晶体管的栅极为一体结构。
8、根据权利要求 1-7任一所述的阵列基板，还包括在显示区域阵列排布 的第二薄膜晶体管； 其中， 所述第一薄膜晶体管与所述第二薄膜晶体管构造相同。
9、 一种对根据权利要求 1-8任意一项所述的阵列基板进行检测的方法， 包括步骤：
在与所述开关元件连接的第一检测线和第二检测线之一输入数据信号， 另一检测线无信号输入， 以关断所述开关元件；
若在所述阵列基板的显示区域可以检测到数据信号， 则判断所述第一检 测线与所述第二检测线发生短路。
10、 一种阵列基板制备方法； 包括形成位于显示区域的第二薄膜晶体管 以及形成位于外围区域的第一检测线、 第二检测线以及相间设置的第一数据 线和第二数据线；
其中， 所述第一数据线直接连接至所述第一检测线， 所述第二数据线通 过开关元件连接至第二检测线； 或者， 所述第二数据线直接连接至所述第二 检测线， 所述第一数据线通过开关元件连接至所述第一检测线。
11、根据权利要求 10所述的阵列基板制备方法， 其中， 所述开关元件为 第一薄膜晶体管。
12、 根据权利要求 11所述的阵列基板制备方法， 包括：
在形成所述第二薄膜晶体管的同时形成所述第一薄膜晶体管。
13、 根据权利要求 12所述的阵列基板制备方法， 进一步包括： 在村底基板上形成所述第一检测线、 所述第一薄膜晶体管的栅极金属层 和所述第二薄膜晶体管的栅极金属层以及所述第一薄膜晶体管的控制线； 形成覆盖整个村底基板的栅绝缘层；
形成所述第一薄膜晶体管的有源层和第二薄膜晶体管的有源层； 形成所述第一数据线、 所述第二数据线、 所述第二检测线以及所述第一 薄膜晶体管的源漏金属层和第二薄膜晶体管的源漏金属层；
形成钝化层以及过孔。
14、 根据权利要求 12所述的阵列基板制备方法， 进一步包括： 在村底基板上形成所述第一检测线、 所述第二检测线、 所述第一薄膜晶 体管的栅极金属层和所述第二薄膜晶体管的栅极金属层以及所述第一薄膜晶 体管的控制线；
形成覆盖整个村底基板的栅绝缘层； 形成第一薄膜晶体管的有源层和第二薄膜晶体管的有源层； 形成所述第一数据线、 所述第二数据线以及所述第一薄膜晶体管的源漏 金属层和所述第二薄膜晶体管的源漏金属层；
形成钝化层以及过孔。
15、 根据权利要求 13或 14所述的阵列基板制备方法， 其中， 设置所述 控制线与所述第一薄膜晶体管的栅极为一体结构。
16、 根据权利要求 13或 14所述的阵列基板制备方法， 其中， 所述控制 线为所述第一检测线。
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