TW202137570A - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TW202137570A
TW202137570A TW109133157A TW109133157A TW202137570A TW 202137570 A TW202137570 A TW 202137570A TW 109133157 A TW109133157 A TW 109133157A TW 109133157 A TW109133157 A TW 109133157A TW 202137570 A TW202137570 A TW 202137570A
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Taiwan
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epitaxial layer
layer
trench
oxide layer
gate structure
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TW109133157A
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TWI759878B (zh
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陳正龍
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台灣積體電路製造股份有限公司
大陸商台積電（中國）有限公司
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Abstract

一種方法包括：在基板的磊晶層上方形成硬遮罩，其中磊晶層具有N型雜質；在硬遮罩上方形成經圖案化的遮罩；使用經圖案化遮罩作為蝕刻遮罩來蝕刻硬遮罩和磊晶層以在磊晶層中形成溝槽，其中硬遮罩的剩餘部分覆蓋磊晶層的最上表面，且溝槽暴露磊晶層的側壁；藉由沿著與磊晶層的最上表面的法線不平行的傾斜方向將p型離子束引導到溝槽來中形成P阱區域，其中在將p型離子束引導到溝槽期間，硬遮罩的剩餘部分保護磊晶層的最上表面；以及在將p型離子束引導到溝槽中之後，在溝槽中形成閘極結構。

Description

半導體元件及其製造方法
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半導體積體電路(IC)行業經歷了快速的增長。IC材料和設計方面的技術進步已經產生了幾代IC，其中每一代都比上一代具有更小和更複雜的電路。這樣的進步增加了IC加工和製造的複雜性和挑戰。
垂直導電溝槽金屬氧化物半導體場效應電晶體(Vertically-conducting trench metal oxide semiconductor field effect transistors)可以用作功率電子元件。當溝槽金屬氧化物半導體場效應電晶體處於導通狀態時，電流在源極區和基板之間垂直流動。減小金屬氧化物半導體場效應電晶體的單元間距對於減小元件尺寸和增加半導體晶片上有源元件的數量至關重要。此外，單元間距也會影響元件性能，例如在元件導通時源極與汲極之間的電阻率(Rdson)。減小單元間距受到製造製程技術的限制，例如光微影工具解決最小臨界尺寸和對準不同圖案化層的能力。在這種情況下，提出以下公開內容。
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以下揭露提供眾多不同的實施例或範例，用於實施本案提供的主要內容之不同特徵。下文描述一特定範例之組件及配置以簡化本揭露。當然，此範例僅為示意性，且並不擬定限制。舉例而言，以下描述「第一特徵形成在第二特徵之上方或之上」，於實施例中可包括第一特徵與第二特徵直接接觸，且亦可包括在第一特徵與第二特徵之間形成額外特徵使得第一特徵及第二特徵無直接接觸。此外，本揭露可在各範例中重複使用元件符號及/或字母。此重複之目的在於簡化及釐清，且其自身並不規定所討論的各實施例及/或配置之間的關係。
此外，空間相對術語，諸如「下方(beneath)」、「以下(below)」、「下部(lower)」、「上方(above)」、「上部(upper)」等等在本文中用於簡化描述，以描述如附圖中所圖示的一個元件或特徵結構與另一元件或特徵結構的關係。除了描繪圖示之方位外，空間相對術語也包含元件在使用中或操作下之不同方位。此設備可以其他方式定向(旋轉90度或處於其他方位上)，而本案中使用之空間相對描述詞可相應地進行解釋。
上文概述了若干實施例的特徵，以便本領域熟習此項技藝者可更好地理解本揭示案的態樣。本領域熟習此項技藝者應當瞭解到他們可容易地使用本揭示案作為基礎來設計或者修改其他製程及結構，以實行相同目的及/或實現相同優勢的。本領域熟習此項技藝者亦應當瞭解到，此類等效構造不脫離本揭示案的精神及範疇，以及在不脫離本揭示案的精神及範疇的情況下，其可對本文進行各種改變、取代及變更。
第1圖至第14圖是根據本公開的一些實施例的各個製造階段的半導體元件的橫截面視圖。
參考第1圖。圖示提供了作為半導體基板100的一部分的半導體區域102。半導體區域102可以具有晶體矽結構。替代地，半導體區域102可以由諸如矽鍺之類的其他半導體材料形成。在一些實施例中，半導體區域102是重摻雜層，其摻雜有諸如磷或砷之類的n型雜質，例如雜質濃度在約1019 /cm3 和約1021 /cm3 之間。在所描述的實施例中，術語“重摻雜(heavily doped)”是指高於約1019 /cm3 的雜質濃度。然而，本領域技術人員將認識到，“重摻雜”是取決於特定元件類型、技術世代、最小特徵尺寸等的技術術語。因此，旨在根據正在評估的技術來解釋該術語，並且該術語不限於所描述的實施例。
在重摻雜半導體區域102上方，半導體基板100還包括磊晶層104。磊晶層104是通過磊晶形成的，並且被輕摻雜有n型雜質。磊晶層104的雜質濃度可以在約1015 /cm3 和約1018 /cm3 之間。因此，磊晶層104的雜質濃度低於半導體區域102的雜質濃度。在一些實施例中，磊晶層104可以是結晶矽層，亦可以使用其他半導體材料。
然後，在磊晶層104上方形成襯墊氧化物層110和硬遮罩112。在一些實施例中，通過對磊晶層104的頂部區域進行熱氧化來形成襯墊氧化物層110，因此襯墊氧化物層110可以包括氧化矽(SiO2 )。硬遮罩112可以由諸如Si3 N4 之類的氮化矽形成，並且可以通過諸如CVD、PVD、ALD或其他適當製程之類的適當製程形成。
然後，在硬遮罩112上形成經圖案化的遮罩M1。在一些實施例中，經圖案化的遮罩M1具有多個開口O1，其定義了在後續步驟中形成的閘極結構的位置(例如，第10圖至第14圖中的閘極結構170)。在一些實施例中，經圖案化的遮罩M1是光阻，並且可以通過光微影製程形成。
參考第2圖。經由經圖案化的遮罩M1的開口O1來蝕刻襯墊氧化物層110、硬遮罩112和磊晶層104，從而在磊晶層104中形成多個溝槽T1。更詳細地，使用經圖案化的遮罩M1作為蝕刻遮罩來對硬遮罩112進行圖案化。然後，使用硬遮罩112作為蝕刻遮罩來對襯墊氧化物層110和磊晶層104進行圖案化。在一些實施例中，可以使用乾蝕刻、濕蝕刻或其組合來蝕刻襯墊氧化物層110、硬遮罩112和磊晶層104。在一些實施例中，每個溝槽T1具有圓弧形底表面。或者，每個溝槽T1具有U形橫截面輪廓。在一些實施例中，溝槽T1的最底端與半導體區域102分離。
參考第3圖。通過適當製程(例如，剝離)來移除經圖案化的遮罩M1。然後，在硬遮罩112上方沉積氧化物層120並且填充溝槽T1。在一些實施例中，氧化物層120完全填充溝槽T1。即，溝槽T1沒有未被氧化物層120填充的部分。在一些實施例中，氧化物層120由SiO2 製成。在一些實施例中，可以通過CVD、PVD、ALD、可流動CVD或其他合適的沉積製程來形成氧化物層120。
參考第4圖。回蝕氧化物層120，以降低氧化物層120的頂表面。剩餘氧化物層120保留在溝槽T1的下部。例如，降低氧化物層120，使得剩餘氧化物層120的最上表面低於磊晶層104的最上表面。換句話說，氧化物層120的剩餘部分設置在溝槽T1的底部。可以使用乾蝕刻、濕蝕刻或其組合來蝕刻氧化物層120。在一些其他實施例中，在回蝕氧化物層120之前，對氧化物層120進行化學機械研磨(CMP)製程以使氧化物層120的頂表面與硬遮罩112的頂表面齊平。在一些實施例中，在回蝕製程之後，氧化物層120的最大高度H1在約0.5μm至約3.5μm的範圍內。
參考第5A圖。在硬遮罩112上方以及溝槽T1的側壁上沉積氧化物層130。在一些實施例中，氧化物層130與硬遮罩112、襯墊氧化物層110和磊晶層104是共形的。可通過共形沉積製程(例如，CVD或ALD)來形成氧化物層130，持續時間短得足以形成共形層而不填充溝槽T1。在其中通過CVD形成氧化物層120和氧化物層130兩者的一些實施例中，氧化物層120的沉積時間可以長於氧化物層130的沉積時間，因為氧化物層120被沉積以完全填充溝槽T1(參見第3圖)，而氧化物層130是與下面的結構共形的薄層。因此，第3圖中的氧化物層120的厚度比第5A圖中的氧化物層130更厚。在一些實施例中，氧化物層130由SiO2 製成。在第5A圖的一些實施例中，氧化物層120和130由相同的材料製成，並且因此在氧化物層120和130之間沒有可區別的介面。而在其中氧化物層120和130由不同的材料製成的一些情況下，氧化物層120和130可以在它們之間包括可區別的介面。
參考第5B圖。第5B圖示出了與第5A圖的實施例不同的其他實施例，其中，在由溝槽T1暴露的磊晶層104的表面上選擇性地形成氧化物層131。在一些實施例中，可以經由熱氧化製程來形成氧化物層131。以此方式，氧化層131在磊晶層104的暴露表面上可以比在硬遮罩112上具有更快的生長速率。在一些實施例中，硬遮罩112的表面沒有被氧化層131覆蓋。即，在形成氧化物層131之後，硬遮罩112的表面保持暴露。
參考第6A圖和第6B圖，其中，第6A圖延續第5A圖的實施例，第6B圖延續第5B圖的實施例。執行方向性植入製程以在磊晶層104中形成多個P阱區域140，其中，相對於磊晶層104的最上表面的垂直方向以傾斜角度將方向性離子引導到磊晶層104。第6A圖和第6B圖中帶有虛線的箭頭表示入射到磊晶層104的離子束。更詳細地，離子束從磊晶層104的側壁經由溝槽T1被引導到磊晶層104，而硬遮罩112阻擋入射離子束，使得離子束不能到達磊晶層104的頂表面。
在一些實施例中，方向性植入製程可以例如通過下方式來執行：經由溝槽T1的第一側(例如，第6A圖和第6B圖中的溝槽T1的左側)以在約30°至約60°的範圍內的第一角度A1將第一方向性離子I1引導至磊晶層104，從而經由溝槽T1的第一側在磊晶層104中形成P阱區域140的部分。這裡，角度A1表示第一方向性離子I1的入射方向與磊晶層104的最上表面的法線之間的角度。在引導第一方向性離子I1之後，經由溝槽T1的(與溝槽T1的第一側相對的)第二側(例如，第6A圖和第6B圖中的溝槽T1的右側)以在約30°至約60°範圍內的第二角度A2將第二方向性離子I2引導至磊晶層104，從而經由溝槽T1的第二側在磊晶層104中形成P阱區域140的其他部分。這裡，角度A2表示第二方向性離子I2的入射方向與磊晶層104的最上表面的法線之間的角度。在一些實施例中，第一角度A1和第二角度A2基本上具有相同的值，但是方向相反。在一些實施例中，如果第一角度A1和第二角度A2過小(例如，遠小於30°)，則離子的軌跡可能過於陡峭，並且因此無法在磊晶層104中達到期望的橫向深度。另一方面，如果第一角度A1和第二角度A2過大(例如，遠大於60°)，則離子的軌跡可能過於水平，並且因此被硬遮罩112阻擋，而無法到達磊晶層104。
在一些實施例中，在方向性植入製程之後，磊晶層104具有在橫向上鄰近P阱區域140的未摻雜區域1042。這是因為方向性離子I1和I2無法從磊晶層104的側壁到達非摻雜區域1042。例如，如第6A圖和第6B圖中的區域S1所示(以虛線繪製)，其中區域S1是磊晶層104的位於兩個相鄰溝槽T1之間的區域(和/或第10圖至第14圖中位於兩個相鄰閘極結構之間的區域)。如圖所示，未摻雜區域1042橫向位於兩個P阱區域140之間。在一些實施例中，未摻雜區域1042的最上端與磊晶層104的最上表面基本上齊平。換句話說，在方向性植入製程之後，磊晶層104的區域S1的最上表面至少部分未被摻雜。在一些實施例中，區域S1在其相對側上具有比其中部更高的摻雜劑濃度。例如，區域S1的中部(例如，未摻雜區域1042)沒有P阱區域140的摻雜劑。
在一些實施例中，第6A圖和第6B圖的氧化物層130和131在方向性植入製程期間用作磊晶層104的保護層(例如，遮罩層)，用於在方向性植入製程期間作為植入製程的屏蔽遮罩並且減小溝道效應。在第6A圖和第6B圖的氧化物層130和131省略的一些實施例中，磊晶層104的側壁可以被溝槽T1暴露，故離子I1和I2可以直接轟擊磊晶層104的暴露側壁並且可以在磊晶層104中引起缺陷。因此，第6A圖和第6B圖的氧化物層130和131可以藉由降低本文所述的方向性植入製程在磊晶層104中引起的缺陷來保護磊晶層104。
在一些實施例中，氧化物層120也可以充當遮罩以阻擋離子I1和I2，從而防止離子I1和I2到達磊晶層104的不需要的區域，因此氧化物層120的高度H1影響P阱區域140的垂直深度。如上所述，氧化物層120的高度H1在約0.5μm至約3.5μm的範圍內。在一些實施例中，如果氧化物層120的高度H1過低，則P阱區域140沿垂直方向可能過長；如果氧化物層120的高度H1過大，則P阱區域140沿垂直方向可能過短。
在本公開的一些實施例中，硬遮罩112用於對磊晶層104進行圖案化以在磊晶層104中形成溝槽T1。然後，可以使用相同的硬遮罩112通過執行方向性植入製程在磊晶層104中形成P阱區域140。在一些實施例中，所有P阱區域140都形成在硬遮罩112下方的區域中，因此P阱區域140基本上可以視為與硬遮罩112自對準。然而，若P阱區域是在後續步驟中(例如，在移除硬遮罩112之後)形成的一些實施例中，則必須使用額外的遮罩來限定P阱區域在磊晶層104中的位置。因此，本公開的實施例提供一種形成自對準P阱區域的方法，亦可以節省成本。
參考第7圖。移除第6A圖中的硬遮罩112、襯墊氧化物層110、氧化物層120和氧化物層130(以及第6B圖中的氧化物層131)。在一些實施例中，硬遮罩112、襯墊氧化物層110、氧化物層120和氧化物層130(或氧化物層131)可以經由諸如乾蝕刻、濕蝕刻或其組合之類的適當蝕刻製程來移除。在蝕刻製程之後，磊晶層104的最上表面被暴露。在一些實施例中，在蝕刻製程之後，暴露未摻雜區域1042。
參考第8A圖。執行退火製程以對第7圖的P阱區域140進行重新分佈以形成P阱區域142。更詳細地，執行退火製程以橫向擴散第7圖的P阱區域140的摻雜劑。例如，如位於兩個相鄰溝槽T1之間的區域S1中所示，第7圖的P阱區域140的摻雜劑通過熱力學擴散到第7圖的未摻雜區域1042，使得未摻雜區域1042變為摻雜區域1044，如第8A圖所示。換句話說，在退火製程之後，區域S1中的磊晶層104的最上表面是完全摻雜區域。在一些實施例中，退火製程可以在約800℃至約1200℃之間的溫度下執行約30分鐘至約240分鐘。
參考第8B圖，其中，第8B圖是示出第8A圖的區域S1中的摻雜劑濃度分佈的曲線圖。第8B圖的垂直軸是摻雜劑濃度，並且第8B圖的水平軸是第8A圖中的區域S1的橫向位置(例如，從左溝槽T1到右溝槽T1)。如第8B圖所示，摻雜劑濃度在區域S1中橫向變化。更詳細地，區域S1在其相對側(其靠近第8A圖中的溝槽T1)具有較高的摻雜劑濃度。這是因為摻雜劑最初是從區域S1的相對側兩側被驅動到區域S1中間部分的，如第6A圖和第6B圖所示。另一方面，因為退火製程將摻雜劑從區域S1的相對側擴散到區域S1的中間部分，所以區域S1的中間部分處的摻雜劑濃度低於在區域S1的相對兩側處的摻雜劑濃度。可以在區域S1的最上表面處發現該特性。即，摻雜劑濃度沿著磊晶層104的區域S1的最上表面變化。
參考第9圖。沉積與磊晶層104共形的閘極介電質層150。閘極介電質層150對溝槽T1形成襯裡。閘極介電質層150可以是氧化物層，例如，氧化矽、二氧化矽(SiO2 )。在一些實施例中，可以通過諸如CVD、ALD或熱氧化製程之類的適當製程來形成閘極介電質層150。在其中通過熱氧化製程形成閘極介電質層150的一些實施例中，熱氧化製程期間的溫度可以足夠高以引起第6A圖和第6B圖所示的P阱區域140的擴散，並且可以引起摻雜劑在P阱區域140中的重新分佈以形成P阱區域142，如第8A圖和第8B圖所示。以此方式，在一些實施例中，第8A圖和第8B圖中描述的退火製程可以被省略，只要第9圖的熱氧化製程的溫度足夠高以引起摻雜劑的重新分佈。在這種情況下(例如，省略第8A圖和第8B圖中討論的退火製程)，由於第9圖的熱氧化製程的溫度足夠高以引起摻雜劑的重新分佈，第9圖中的區域S1可以仍具有與第8B圖中討論的相似的摻雜劑濃度分佈。
參考第10圖。閘極電極層160被沉積在閘極介電質層150上方並且填充溝槽T1。在一些實施例中，閘極電極層160可以是多晶矽。在一些實施例中，閘極電極層160可以是摻雜的多晶矽。在一些實施例中，通過在低壓製程腔內熱分解矽烷(SiH4 )來形成閘極電極層160。閘極電極層160被形成為具有填充溝槽T1的厚度。
參考第11圖。執行化學機械研磨(CMP)製程以移除過多的閘極電極層160(參見第10圖)和閘極介電質層150，直到暴露磊晶層104。在CMP製程之後，溝槽T1中的閘極電極層160的剩餘部分可以被稱為閘極電極162，並且溝槽T1中的閘極介電質層150的剩餘部分可以被稱為閘極介電質152。在一些實施例中，在每個溝槽T1內，閘極電極162和閘極介電質152可以被統稱為閘極結構170。
參考第12圖。在磊晶層104上方形成經圖案化的遮罩M2。在一些實施例中，經圖案化的遮罩M2具有開口O2，其暴露閘極結構170以及磊晶層104的鄰近閘極結構170的部分的頂表面。另一方面，磊晶層104的部分被經圖案化的遮罩M2覆蓋。然後，執行植入製程以經由開口O2在磊晶層104的暴露部分中形成多個N+源極區域180。N+源極區域180可以被稱為重摻雜N+區域180。
在一些實施例中，第12圖的植入製程包括將離子I3引導至磊晶層104。在一些實施例中，離子I3的入射方向基本垂直於磊晶層104的頂表面。即，離子I3的入射方向與磊晶層104的頂表面的法線基本對準。在一些其他實施例中，離子I3的入射方向與磊晶層104的頂表面的法線之間的角度在約0°至約7°的範圍內。在所描繪的實施例中，因為閘極結構170沒有被經圖案化的遮罩M2覆蓋，所以閘極結構170的至少最上部分可能被離子I3非刻意地摻雜。在一些其他實施例中，閘極結構170被經圖案化的遮罩M2覆蓋，使得閘極結構170將不會被離子I3摻雜。
如先前於第6A圖和第6B圖所討論的，方向性離子I1和I2以傾斜角度入射到磊晶層104。在一些實施例中，第12圖的離子I3的入射方向與第6A圖和第6B圖中描述的離子I1和I2的入射方向相比更垂直於磊晶層104的頂表面。換句話說，第12圖的離子I3的入射方向與磊晶層104的頂表面的法線之間的角度小於第6A圖和第6B圖的離子I1和I2的入射方向與磊晶層104的頂表面的法線之間的角度。
參考第13圖。移除經圖案化的遮罩M2，並且在磊晶層104上方形成經圖案化的遮罩M3。在一些實施例中，經圖案化的遮罩M3具有暴露磊晶層104的部分的開口O3。另一方面，N+源極區域180和閘極結構170被經圖案化的遮罩M3覆蓋。然後，執行植入製程以經由開口O3在磊晶層104的暴露部分中形成多個P+本體區域。在一些實施例中，P+本體區域190中的摻雜劑濃度高於P阱區域142中的摻雜劑濃度。
在一些實施例中，第13圖的植入製程包括將離子I4引導至磊晶層104。在一些實施例中，離子I4的入射方向基本垂直於磊晶層104的頂表面。即，離子I4的入射方向與磊晶層104的頂表面的法線基本對準。在一些其他實施例中，離子I4的入射方向與磊晶層104的頂表面的法線之間的角度在約0°至約7°的範圍內。
如先前於第6A圖和第6B圖所討論的，方向性離子I1和I2以傾斜角度入射到磊晶層104。在一些實施例中，第13圖的離子I4的入射方向比第6A圖和第6B圖中描述的離子I1和I2的入射方向相比更垂直於磊晶層104的頂表面。換句話說，第13圖的離子I4的入射方向與磊晶層104的頂表面的法線之間的角度小於第6A圖和第6B圖的離子I1和I2的入射方向與磊晶層104的頂表面的法線之間的角度。
參考第14圖。移除經圖案化的遮罩M3。因此形成半導體元件10。在一些實施例中，半導體元件10是金屬氧化物場效應電晶體(MOSFET)元件。因為閘極結構170被形成在磊晶層104的溝槽T1中，所以半導體元件10也可以被稱為溝槽金屬氧化物場效應電晶體(trench MOSFET)。在一些其他實施例中，半導體元件10也可以被稱為UMOS(U形溝槽MOSFET)。
注意，P阱區域142具有部分142T，其中，P阱區域142的部分142T在第12圖和第13圖的製程期間被經圖案化的遮罩M2和M3保護。在一些實施例中，P阱區域142的部分142T位於半導體元件10的邊緣區域10T(terminal region)內。邊緣區域10T可以被視為位於半導體元件10的邊界處的區域。典型地，半導體元件10的該區域不具有電路功能，並且因此位於該區域內的P阱區域142的部分142T不經歷第12圖和第13圖的植入製程。另一方面，半導體元件10的單元區域10C(cell region)內的其他部分可以經歷第12圖和第13圖的植入製程。單元區域10C可以被視為半導體元件10的執行某些特定功能操作的區域。
第15A圖和第15B圖示出了根據本公開的一些實施例的製造方法1000。雖然方法1000被圖示和/或描述為一系列動作或事件，但是應當理解，該方法不限於圖示的順序或動作。因此，在一些實施例中，可以以與圖示的順序不同的循序執行動作，和/或可以同時執行動作。此外，在一些實施例中，圖示的動作或事件可以被細分為多個動作或事件，其可以在分開的時間執行，或者與其他動作或子動作同時地執行。在一些實施例中，可以省略一些圖示的動作或事件，並且可以包括其他未圖示的動作或事件。
在方塊S101處，在基板的磊晶層上方形成襯墊氧化物層、硬遮罩層和第一經圖案化的遮罩。第1圖示出了與方塊S101中的動作相對應的一些實施例的示意圖。
在方塊S102處，蝕刻襯墊氧化物層、硬遮罩和磊晶層以在磊晶層中形成溝槽。第2圖示出了與方塊S102中的動作相對應的一些實施例的示意圖。
在方塊S103處，移除第一經圖案化的遮罩，並且在硬遮罩層上方沉積第一氧化物層並填充磊晶層的溝槽。第3圖示出了與方塊S103中的動作相對應的一些實施例的示意圖。
在方塊S104處，回蝕第一氧化物層。第4圖示出了與方塊S104中的動作相對應的一些實施例的示意圖。
在方塊S105處，在磊晶層的溝槽的側壁上沉積第二氧化物層。第5A圖和第5B圖示出了與方塊S105中的動作相對應的一些實施例的示意圖。
在方塊S106處，執行方向性植入製程以在磊晶層中形成多個P阱區域。第6A圖和第6B圖示出了與方塊S106中的動作相對應的一些實施例的示意圖。
在方塊S107處，移除硬遮罩層、襯墊氧化物、第一氧化物層和第二氧化物層。第7圖示出了與方塊S107中的動作相對應的一些實施例的示意圖。
在方塊S108處，執行退火製程以對P阱區域進行重新分佈。第8圖示出了與方塊S108中的動作相對應的一些實施例的示意圖。
在方塊S109處，在磊晶層的溝槽中沉積閘極介電質層。第9圖示出了與方塊S109中的動作相對應的一些實施例的示意圖。
在方塊S110處，在閘極介電質層上方沉積閘極電極層，並且填充磊晶層的溝槽。第10圖示出了與方塊S110中的動作相對應的一些實施例的示意圖。
在方塊S111處，執行化學機械研磨(CMP)製程以移除多餘的閘極電極層和閘極介電質層以形成閘極結構。第11圖示出了與方塊S111中的動作相對應的一些實施例的示意圖。
在方塊S112處，在磊晶層上方形成第二經圖案化的遮罩，並且執行第一植入製程以在磊晶層中形成N+源極區域。第12圖示出了與方塊S112中的動作相對應的一些實施例的示意圖。
在方塊S113處，移除第二經圖案化的遮罩，在磊晶層上方形成第三經圖案化的遮罩，並且執行第二植入製程以在磊晶層中形成P+本體區域。第13圖示出了與方塊S113中的動作相對應的一些實施例的示意圖。
在方塊S114處，移除第三經圖案化的遮罩。第14圖示出了與方塊S114中的動作相對應的一些實施例的示意圖。
參考第16圖。第16圖是根據本公開的一些實施例的半導體元件。第16圖中的半導體元件20與第14圖中的半導體元件的不同之處在於，第16圖中的半導體區域202是P型區域。在一些實施例中，半導體區域202是重摻雜層，其摻雜有諸如硼(B)、鎵(Ga)、銦(In)、鋁(Al)之類的p型雜質，例如雜質濃度在約1019 /cm3 和約1021 /cm3 之間。在所描述的實施例中，術語“重摻雜”是指高於約1019 /cm3 的雜質濃度。第16圖中的半導體元件可以被視為絕緣閘極雙極型電晶體(IGBT)。在一些實施例中，第16圖的一些元件與第1圖至第14圖中描述的那些元件相似或相同，並且因此這類元件被標記為相同的，並且為簡潔起見將不再重複。
第17圖至第23圖是根據本公開的一些實施例的各個製造階段的半導體元件的橫截面視圖。
參考第17圖。第17圖的結構類似於在第8A圖和第8B圖中描述的結構。第17圖的一些元件與第8A圖的元件相同或相似，並且因此這類元件被標記為相同的，並且為簡潔起見將不再重複結構細節。第17圖與第8A圖的不同之處在於，磊晶層104的溝槽T2比第8A圖中的溝槽T1深。在一些實施例中，第17圖的P阱區域142通過與關於第3圖至第8B圖中描述的相同或相似的方法形成，並且因此不再重複相關細節。
參考第18圖。在磊晶層104上方和溝槽T2中形成閘極介電質層300。閘極介電質層300對溝槽T2形成襯裡。閘極介電質層300可以是氧化物層，例如，氧化矽、二氧化矽(SiO2 )。在一些實施例中，可以通過諸如CVD、ALD或熱氧化製程之類的適當製程來形成閘極介電質層300。在一些實施例中，基於針對低Rds和高擊穿電壓的元件優化，閘極介電質層300被生長為具有期望的厚度。厚的閘極介電質層300在此減小了矽表面電場，從而針對相同的擊穿額定值(breakdown rating)允許使用更高的摻雜並且產生更低的Rds。
參考第19圖。在溝槽T2中並且在閘極介電質層300上方形成多個閘極電極310。在一些實施例中，閘極電極310可以是多晶矽。在一些實施例中，可以例如通過以下方式來形成閘極電極310：在磊晶層104上方沉積毯式閘極電極層並且填充溝槽T2，然後通過回蝕刻製程使用蝕刻劑來降低閘極電極層的頂表面，該蝕刻劑以比蝕刻閘極介電質材料(例如，氧化矽)更快的蝕刻速率蝕刻閘極電極材料(例如，多晶矽)。在一些實施例中，對閘極電極層執行回蝕製程，使得閘極電極310的頂表面低於磊晶層104的最頂表面。在一些其他實施例中，對閘極電極層執行回蝕製程，使得閘極電極310的頂表面低於P阱區域142的最底端。
參考第20圖。使用例如濕蝕刻來移除閘極介電質層300的部分，直到位於未被閘極電極310密封的區域中的磊晶層104的頂表面和側壁是乾淨的。在一些實施例中，執行蝕刻製程，使得閘極介電質層300的位於溝槽T2的下部內的部分不被蝕刻。即，在蝕刻製程之後，閘極介電質層300的至少部分保留在閘極電極310和磊晶層104之間。蝕刻製程可以是例如使用以下蝕刻劑(例如，稀釋的HF)的選擇性蝕刻製程，該蝕刻劑蝕刻閘極介電質材料(例如，氧化矽)，而不蝕刻層104中的磊晶材料(例如，單晶矽)和閘極電極材料(例如多晶矽)。
參考第21圖。在閘極電極310上方並且沿著磊晶層104的暴露表面形成閘極介電質層320。在一些實施例中，閘極介電質層320被形成為覆蓋和密封閘極電極310。在一些實施例中，閘極電極310可以互換地稱為底部遮罩電極310。在一些實施例中，閘極介電質層320比在第18圖中形成的閘極介電質層300更薄。閘極溝槽側壁上的薄閘極介電質層320提供降低閘極閾值電壓的優點。
參考第22圖。在磊晶層104的溝槽T2中形成多個閘極電極330。在一些實施例中，閘極電極330可以是多晶矽。在一些實施例中，可以例如通過以下方式來形成閘極電極330：在磊晶層104上方沉積毯式閘極電極層並且填充溝槽T2，然後通過CMP製程移除多餘的閘極電極層，直到磊晶層104的頂表面被暴露。在一些實施例中，在每個溝槽T2中，剩餘的閘極介電質層300、閘極電極310、剩餘的閘極介電質層320和閘極電極330可以被統稱為閘極結構340。
參考第23圖。在磊晶層104中形成N+源極區域180和P+本體區域(body region)190，並且形成半導體元件20。在一些實施例中，第23圖的半導體元件30可以被稱為遮罩閘極溝槽場效電晶體(shielded-gate trench FET；SGT FET)。通常，遮罩閘極溝槽場效電晶體包括位在一閘極電極(例如，閘極電極330)下方的一遮罩電極(例如，閘極電極320)。遮罩閘極(例如，閘極電極320)和閘極電極(例如，閘極電極330)通過用作電極間介電質的介電質層(例如，閘極介電質層320)彼此絕緣。
在一些實施例中，半導體元件30包括單元區域20C和邊緣區域20T，其與第14圖中描述的半導體元件10的單元區域10C和邊緣區域10T相似。N+源極區域180和P+本體區域190通過與第12圖至第14圖中討論的相似或相同的方法形成，並且因此為了簡潔起見將不再重複相關細節。
第24圖是根據本公開的一些實施例的用於形成半導體元件的方法。雖然方法2000被圖示和/或描述為一系列動作或事件，但是應當理解，該方法不限於圖示的順序或動作。因此，在一些實施例中，可以以與圖示的順序不同的循序執行動作，和/或可以同時執行動作。此外，在一些實施例中，圖示的動作或事件可以被細分為多個動作或事件，其可以在分開的時間執行，或者與其他動作或子動作同時地執行。在一些實施例中，可以省略一些圖示的動作或事件，並且可以包括其他未圖示的動作或事件。
在一些實施例中，可以在方法2000的方塊S201之前執行一些操作，例如在關於第1圖至第8B圖的方塊S101至108中描述的操作。相應地，第17圖示出了方法2000的方塊S201的初始結構。
在方塊S201處，在磊晶層上方和磊晶層的溝槽中形成第一閘極介電質層。第18圖示出了與方塊S201中的動作相對應的一些實施例的示意圖。
在方塊S202處，在溝槽中並且在第一閘極介電質層上方形成多個第一閘極電極。第19圖示出了與方塊S202中的動作相對應的一些實施例的示意圖。
在方塊S203處，移除第一閘極介電質層300的部分以暴露磊晶層的表面。第20圖示出了與方塊S203中的動作相對應的一些實施例的示意圖。
在方塊S204處，在第一閘極電極上方並且沿著磊晶層的暴露表面形成第二閘極介電質層。第21圖示出了與方塊S204中的動作相對應的一些實施例的示意圖。
在方塊S205處，在磊晶層的溝槽中形成多個第二閘極電極。第22圖示出了與方塊S205中的動作相對應的一些實施例的示意圖。
在方塊S206處，在磊晶層中形成N+源極區域和P+本體區域。第23圖示出了與方塊S206中的動作相對應的一些實施例的示意圖。
基於以上討論，可以看出本公開提供了優點。然而，應當理解，其他實施例可以提供附加優點，並且在本文中不必公開所有優點，並且對於所有實施例不需要特定的優點。一個優點是硬遮罩層用於對磊晶層進行圖案化以在磊晶層中形成溝槽。然後，可以通過方向性植入製程使用相同的硬遮罩層在磊晶層中形成P阱區域。P阱區域被形成在硬遮罩層下方的磊晶層的區域中，並且因此P阱區域可以被認為與硬遮罩層基本自對準，並且因此用於限定P阱區域的位置的附加遮罩可以被省略，這將減少製程成本和製程時間。
在本公開的一些實施例中，一種方法包括：在基板的磊晶層上方形成硬遮罩，其中磊晶層具有N型雜質；在硬遮罩上方形成經圖案化的遮罩；使用經圖案化遮罩作為蝕刻遮罩來蝕刻硬遮罩和磊晶層以在磊晶層中形成溝槽，其中硬遮罩的剩餘部分覆蓋磊晶層的最上表面，且溝槽暴露磊晶層的側壁；藉由沿著與磊晶層的最上表面的法線不平行的傾斜方向將p型離子束引導到溝槽來中形成P阱區域，其中在將p型離子束引導到溝槽期間，硬遮罩的剩餘部分保護磊晶層的最上表面；以及在將p型離子束引導到溝槽中之後，在溝槽中形成閘極結構。
在部分實施例中，方法還包含在溝槽中形成閘極結構之前，移除硬遮罩的剩餘部分以暴露磊晶層的最上表面。
在部分實施例中，其中P阱區域位於硬遮罩的剩餘部分的正下方。
在部分實施例中，還包含在引導p型離子束之前，在溝槽的底部形成第一氧化物層，其中磊晶層的側壁的上部在形成第一氧化物層之後保持暴露。
在部分實施例中，還包含在形成第一氧化物層之後且在引導p型離子束之前，形成第二氧化物層，第二氧化物層覆蓋磊晶層的側壁的上部。
在部分實施例中，還包含在引導p型離子束之後，移除第一氧化物層和第二氧化物層。
在部分實施例中，還包含在形成閘極結構之後，將一n型離子束從磊晶層的最上表面引導到磊晶層以在磊晶層中形成n型源極區域。
在部分實施例中，其中p型離子束的一傾斜方向與磊晶層的最上表面的法線之間的第一角度大於n型離子束的入射方向與磊晶層的最上表面的法線之間的第二角度。
在部分實施例中，還包含在形成閘極結構之前，對P阱區域執行退火製程。
在本公開的一些實施例中，一種方法，包括：在基板的磊晶層上方形成硬遮罩，其中磊晶層具有N型雜質；蝕刻硬遮罩和磊晶層以在磊晶層中形成溝槽，其中硬遮罩的剩餘部分覆蓋磊晶層的最上表面，且溝槽暴露磊晶層的側壁；在磊晶層上方沉積第一氧化物層並且填滿溝槽；回蝕第一氧化物層直到磊晶層的側壁被溝槽暴露；形成第二氧化物層，其覆蓋由溝槽暴露的磊晶層的側壁；在形成第二氧化物層之後，在磊晶層中形成P阱區域；移除硬遮罩的剩餘部分、第一氧化物層和第二氧化物層；以及在溝槽中形成閘極結構。
在部分實施例中，其中沉積第一氧化物層被執行以使得第一氧化物層具有第一厚度，形成第二氧化物層被執行以使得第二氧化物層具有第二厚度，且第一厚度大於第二厚度。
在部分實施例中，其中形成第二氧化物層被執行以使得第二氧化物層從該硬遮罩的該剩餘部分的頂表面延伸至磊晶層的側壁。
在部分實施例中，其中第二氧化物層是通過氧化磊晶層的側壁來形成的。
在部分實施例中，其中在磊晶層中形成該P阱區域包含：相對於磊晶層的最上表面的法線以傾斜角度將p型離子束引導到該磊晶層，其中該P阱區域被形成在該硬遮罩的剩餘部分下方。
在部分實施例中，其中硬遮罩的該剩餘部分防止離子束到達磊晶層的最上表面。
在部分實施例中，其中傾斜角度在約30°至約60°的範圍內。
在部分實施例中，其中形成閘極結構包含：在溝槽中形成閘極電介質，其中閘極電介質是通過熱氧化製程形成的，且P阱區域在熱氧化製程之後的輪廓與P阱區域在熱氧化製程之前的輪廓不同；以及在閘極電介質上方形成閘極電極。
在本公開的一些實施例中，一種半導體元件包括基板、第一閘極結構和第二閘極結構。基板具有半導體區域和位於半導體區域上方的磊晶層。第一閘極結構和第二閘極結構設置在磊晶層中，第一閘極結構和第二閘極結構具有圓弧形底表面，其中磊晶層具有橫向位於第一閘極結構和第二閘極結構之間的P阱區域，且P阱區域中的摻雜劑濃度沿著從第一閘極結構到第二閘極結構的方向變化。
在部分實施例中，其中沿著從第一閘極結構到第二閘極結構的方向，P阱區域具有以下特徵：P阱區域靠近第一閘極結構的第一側處具有第一摻雜劑濃度；P阱區域靠近第二閘極結構的一第二側處具有第二摻雜劑濃度；並且P阱區域的中間部分處具有第三摻雜劑濃度，其中第一摻雜劑濃度和第二摻雜劑濃度高於第三摻雜劑濃度。
在部分實施例中，半導體元件還包含:複數個重摻雜N型區域，位於P阱區域該第一側和第二側上方。以及重摻雜P型區域，位於P阱區域的中部上方。
以上概述了若干實施例的特徵，使得本領域技術人員可以更好地理解本公開的各方面。本領域技術人員應當理解，他們可以容易地使用本公開作為設計或修改其他製程和結構以實現本文介紹的實施例或示例的相同目的和/或實現本文介紹的實施例或示例的相同優點的基礎。本領域技術人員還應該認識到，這樣的等同配置不脫離本公開的精神和範圍，並且他們可以在不脫離本公開的精神和範圍的情況下在本文中進行各種改變、替換和變更。
10、20、30:半導體元件 10C、20C:單元區域 10T、20T:邊緣區域 100:基板 102:半導體區域 104:磊晶層 110:襯墊氧化物層 112:硬遮罩 120、130、131:氧化物層 140、142:P阱區域 142T:部分 150:閘極介電質層 152:閘極介電質 160:閘極電極層 162:閘極電極 170:閘極結構 180:N+源極區域 190:P+本體區域 202:半導體區域 300:閘極介電質層 310:閘極電極 320:閘極介電質層 330:閘極電極 340:閘極結構 1042:未摻雜區域 1044:摻雜區域 H1:高度 I1、I2、I3、I4:離子 A1、A2:角度 M1、M2、M3:經圖案化的遮罩 O1、O2、O3:開口 S1:區域 S101-S114、S201-S206:方塊 T1、T2:溝槽
閱讀以下詳細敘述並搭配對應之圖式，可了解本揭露之多個態樣。應注意，根據業界中的標準做法，多個特徵並非按比例繪製。事實上，多個特徵之尺寸可任意增加或減少以利於討論的清晰性。 第1圖至第14圖是根據本公開的一些實施例的各個製造階段的半導體元件的橫截面視圖。 第15A圖和第15B圖是根據本公開的一些實施例的用於形成半導體元件的方法。 第16圖是根據本公開的一些實施例的半導體元件的橫截面視圖。 第17圖至第23圖是根據本公開的一些實施例的各個製造階段的半導體元件的橫截面視圖。 第24圖是根據本公開的一些實施例的用於形成半導體元件的方法。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
10:半導體元件
10C:單元區域
10T:邊緣區域
100:基板
102:半導體區域
104:磊晶層
142:P阱區域
142T:部分
152:閘極介電質
162:閘極電極
170:閘極結構
180:N+源極區域
190:P+本體區域
T1:溝槽

Claims (20)

  1. 一種半導體元件的製造方法，包含： 在一基板的一磊晶層上方形成一硬遮罩，其中，該磊晶層具有一N型雜質； 在該硬遮罩上方形成一經圖案化的遮罩； 使用該經圖案化的遮罩作為一蝕刻遮罩來蝕刻該硬遮罩和該磊晶層，以在該磊晶層中形成一溝槽，其中該硬遮罩的一剩餘部分覆蓋該磊晶層的一最上表面，且該溝槽暴露該磊晶層的一側壁； 藉由沿著與該磊晶層的該最上表面的一法線不平行的傾斜方向將一p型離子束引導到該溝槽中來形成一P阱區域，其中在將該p型離子束引導到該溝槽期間，該硬遮罩的該剩餘部分保護該磊晶層的該最上表面；以及 在將該p型離子束引導到該溝槽之後，在該溝槽中形成一閘極結構。
  2. 如請求項1的方法，還包含在該溝槽中形成該閘極結構之前，移除該硬遮罩的該剩餘部分以暴露該磊晶層的該最上表面。
  3. 如請求項1的方法，其中該P阱區域位於該硬遮罩的該剩餘部分的正下方。
  4. 如請求項1的方法，還包含在引導該p型離子束之前，在該溝槽的一底部形成一第一氧化物層，其中該磊晶層的該側壁的一上部在形成該第一氧化物層之後保持暴露。
  5. 如請求項4的方法，還包含在形成該第一氧化物層之後且在引導該p型離子束之前，形成一第二氧化物層，該第二氧化物層覆蓋該磊晶層的該側壁的該上部。
  6. 如請求項5的方法，還包含在引導該p型離子束之後，移除該第一氧化物層和該第二氧化物層。
  7. 如請求項1的方法，還包含在形成該閘極結構之後，將一n型離子束從該磊晶層的該最上表面引導到該磊晶層以在該磊晶層中形成一n型源極區域。
  8. 如請求項7的方法，其中該p型離子束的一傾斜方向與該磊晶層的該最上表面的一法線之間的一第一角度大於該n型離子束的一入射方向與該磊晶層的該最上表面的該法線之間的一第二角度。
  9. 如請求項1的方法，還包含在形成該閘極結構之前，對該P阱區域執行一退火製程。
  10. 一種半導體元件的製造方法，包含： 在一基板的一磊晶層上方形成一硬遮罩，其中該磊晶層具有一N型雜質； 蝕刻該硬遮罩和該磊晶層以在該磊晶層中形成一溝槽，其中該硬遮罩的剩餘部分覆蓋該磊晶層的一最上表面，且該溝槽暴露該磊晶層的一側壁； 在該磊晶層上方沉積一第一氧化物層並且填滿該溝槽； 回蝕該第一氧化物層直到該磊晶層的該側壁被該溝槽暴露為止； 形成一第二氧化物層，該第二氧化物層覆蓋被該溝槽暴露的該磊晶層的該側壁； 在形成該第二氧化物層之後，在該磊晶層中形成P阱區域； 移除該硬遮罩的該剩餘部分、該第一氧化物層和該第二氧化物層；以及 在該溝槽中形成一閘極結構。
  11. 如請求項10的方法，其中沉積該第一氧化物層被執行以使得該第一氧化物層具有一第一厚度，形成該第二氧化物層被執行以使得該第二氧化物層具有一第二厚度，且該第一厚度大於該第二厚度。
  12. 如請求項10的方法，其中形成該第二氧化物層被執行以使得該第二氧化物層從該硬遮罩的該剩餘部分的一頂表面延伸至該磊晶層的該側壁。
  13. 如請求項10的方法，其中該第二氧化物層是通過氧化該磊晶層的該側壁來形成的。
  14. 如請求項10的方法，其中在該磊晶層中形成該P阱區域包含：相對於該磊晶層的該最上表面的法線以一傾斜角度將p型離子束引導到該磊晶層，其中該P阱區域被形成在該硬遮罩的剩餘部分下方。
  15. 如請求項10的方法，其中該硬遮罩的該剩餘部分防止該離子束到達該磊晶層的該最上表面。
  16. 如請求項10的方法，其中該傾斜角度在約30°至約60°的範圍內。
  17. 如請求項10的方法，其中形成該閘極結構包含： 在該溝槽中形成一閘極電介質，其中該閘極電介質是通過熱氧化製程形成的，且該P阱區域在該熱氧化製程之後的輪廓與該P阱區域在該熱氧化製程之前的輪廓不同；以及 在該閘極電介質上方形成一閘極電極。
  18. 一種半導體元件，包含： 一基板，具有一半導體區域和位於該半導體區域上方的一磊晶層；以及 一第一閘極結構和一第二閘極結構，設置在該磊晶層中，該第一閘極結構和該第二閘極結構具有圓弧形底表面，其中， 該磊晶層具有橫向位於該第一閘極結構與該第二閘極結構之間的P阱區域，並且該P阱區域中的摻雜劑濃度沿著從該第一閘極結構到該第二閘極結構的方向變化。
  19. 如請求項18的半導體元件，其中沿著從該第一閘極結構到該第二閘極結構的該方向，該P阱區域具有以下特徵： 該P阱區域靠近該第一閘極結構的一第一側處具有一第一摻雜劑濃度； 該P阱區域靠近該第二閘極結構的一第二側處具有一第二摻雜劑濃度；並且 該P阱區域的一中間部分處具有一第三摻雜劑濃度，其中該第一摻雜劑濃度和該第二摻雜劑濃度高於該第三摻雜劑濃度。
  20. 如請求項18的半導體元件，還包含: 複數個重摻雜N型區域，位於該P阱區域的該第一側和該第二側上方；以及 一重摻雜P型區域，位於該P阱區域的該中部上方。
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