WO2023073765A1 - 半導体メモリ装置の製造方法 - Google Patents

半導体メモリ装置の製造方法 Download PDF

Info

Publication number
WO2023073765A1
WO2023073765A1 PCT/JP2021/039319 JP2021039319W WO2023073765A1 WO 2023073765 A1 WO2023073765 A1 WO 2023073765A1 JP 2021039319 W JP2021039319 W JP 2021039319W WO 2023073765 A1 WO2023073765 A1 WO 2023073765A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
gate
impurity
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/039319
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
理一郎 白田
望 原田
康司 作井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisantis Electronics Singapore Pte Ltd
Original Assignee
Unisantis Electronics Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisantis Electronics Singapore Pte Ltd filed Critical Unisantis Electronics Singapore Pte Ltd
Priority to PCT/JP2021/039319 priority Critical patent/WO2023073765A1/ja
Priority to JP2023555893A priority patent/JPWO2023073765A1/ja
Priority to TW111140269A priority patent/TWI838924B/zh
Priority to US17/971,789 priority patent/US20230127781A1/en
Publication of WO2023073765A1 publication Critical patent/WO2023073765A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies

Definitions

  • the present invention relates to a method of manufacturing a semiconductor memory device.
  • the channel In a normal planar MOS transistor, the channel extends horizontally along the upper surface of the semiconductor substrate. In contrast, the SGT channel extends in a direction perpendicular to the upper surface of the semiconductor substrate (see Patent Document 1 and Non-Patent Document 1, for example). For this reason, the SGT enables a higher density semiconductor device compared to a planar MOS transistor.
  • a DRAM Dynamic Random Access Memory
  • a PCM Phase Change Memory
  • Non-Patent Document 4 RRAM (Resistive Random Access Memory, see, for example, Non-Patent Document 4), MRAM (Magneto-resistive Random Access Memory, see, for example, Non-Patent Document 5) that changes the resistance by changing the direction of the magnetic spin by current ) can be highly integrated.
  • DRAM memory cell see Non-Patent Document 6
  • the present application relates to a dynamic flash memory that does not have resistance change elements or capacitors and can be configured only with MOS transistors.
  • FIG. 8 shows the write operation of a DRAM memory cell composed of a single MOS transistor without the capacitor described above, FIG. 8 shows the operational problem, and FIG. 8 shows the read operation.
  • FIG. 8 shows the write operation of the DRAM memory cell.
  • FIG. 8(a) shows a "1" write state.
  • the memory cell is formed on the SOI substrate 100 and includes a source N + layer 103 (hereinafter, a semiconductor region containing a high concentration of donor impurities is referred to as an “N + layer”) to which a source line SL is connected.
  • the drain N + layer 104 connected to the line BL, the gate conductive layer 105 connected to the word line WL, and the floating body 102 of the MOS transistor 110a.
  • a memory cell of the DRAM is composed of these pieces.
  • the SiO 2 layer 101 of the SOI substrate is in contact directly below the floating body 102 .
  • the MOS transistor 110a When "1" is written to the memory cell constituted by one MOS transistor 110a, the MOS transistor 110a is operated in the saturation region. That is, the electron channel 107 extending from the source N + layer 103 has a pinch-off point P and does not reach the drain N + layer 104 connected to the bit line. In this way, both the bit line BL connected to the drain N + layer 104 and the word line WL connected to the gate conductive layer 105 are set at a high voltage, and the gate voltage is set to about 1/2 of the drain voltage. is operated, the electric field intensity becomes maximum at the pinch-off point P near the drain N + layer 104 .
  • the holes 106 generated at the same time charge the floating body 102 . In this case, the generated holes contribute as increments of majority carriers because the floating body 102 is P-type Si.
  • the floating body 102 is filled with the generated holes 106, and when the voltage of the floating body 102 becomes higher than that of the source N + layer 103 by Vb or more, the generated holes are discharged to the source N + layer 103.
  • Vb is the built-in voltage of the PN junction between the source N + layer 103 and the floating body 102 of the P layer, which is about 0.7V.
  • FIG. 8B shows how the floating body 102 is saturated charged with the generated holes 106 .
  • FIG. 8(c) shows how the "1" write state is rewritten to the "0" write state.
  • the voltage of the bit line BL is negatively biased, and the PN junction between the drain N + layer 104 and the floating body 102 of the P layer is forward biased.
  • the holes 106 previously generated in the floating body 102 in the previous cycle flow to the drain N + layer 104 connected to the bit line BL.
  • the capacitance CFB of the floating body 102 is composed of the capacitance CWL between the gate connected to the word line and the floating body 102, and the source N + layer 103 connected to the source line.
  • FIG. 10(a) shows a "1" write state
  • FIG. 10(b) shows a "0" write state.
  • Vb is written to the floating body 102 by writing "1”
  • the floating body 102 is pulled down to a negative bias when the word line returns to 0 V at the end of writing.
  • the negative bias becomes even deeper. Therefore, as shown in FIG. do not have.
  • This small operating margin is a major problem of the present DRAM memory cell.
  • a method for manufacturing a memory device using a semiconductor element includes: By controlling the voltage applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer, an impact ionization phenomenon or a gate a data holding operation of holding hole groups or electron groups that are majority carriers of the semiconductor pillars formed by an induced drain leak current; the first gate conductor layer; the second gate conductor layer; and a data erasing operation of removing the group of holes or the group of electrons, which are the majority carriers of the semiconductor pillar, from the inside of the semiconductor pillar by controlling the voltage applied to the second impurity layer.
  • a semiconductor memory device manufacturing method comprising: a first impurity layer, a first insulating layer, a first material layer, a second insulating layer, a second material layer, and a third material layer from below in a vertical direction on the substrate; a step of laminating the The bottom part is on the surface of or inside the first impurity layer, and the first insulating layer, the first material layer, the second insulating layer, the second material layer, and the third material layer.
  • the first impurity layer is connected to a source line
  • the first gate conductor layer is connected to a plate line
  • the second gate conductor layer is connected to a word line
  • the second impurity layer is connected to a word line.
  • the layer is connected to the bit line, and the wiring conductor layer of the bit line is formed to extend in a direction perpendicular to the first direction in plan view (second invention).
  • the step of removing a portion of the third material layer to expose the top of the semiconductor pillar; forming a third impurity layer covering the exposed top of the semiconductor pillar; has The third impurity layer serves as the second impurity layer (third invention).
  • the step of forming a fourth impurity layer on the top of the semiconductor pillar is formed by the third impurity layer and the fourth impurity layer (fourth invention).
  • the inner walls of the second hole and the third hole are covered with the second hole.
  • a third gate insulating layer is formed to cover the first gate insulating layer and the second gate insulating layer (a fifth invention).
  • the third material layer has at least one insulating layer (sixth invention).
  • the first insulating layer, the first material layer, the second insulating layer, the second material layer, and the third insulating layer protruded outside the block region. and etching away the third material layer; (7th invention).
  • FIG. 1 is a structural diagram of a semiconductor memory device according to a first embodiment
  • FIG. FIG. 4 is a diagram for explaining an erase operation mechanism of the semiconductor memory device according to the first embodiment
  • FIG. 2 is a diagram for explaining a write operation mechanism of the semiconductor memory device according to the first embodiment
  • FIG. FIG. 2 is a diagram for explaining a read operation mechanism of the semiconductor memory device according to the first embodiment
  • FIG. FIG. 2 is a diagram for explaining a read operation mechanism of the semiconductor memory device according to the first embodiment
  • FIG. FIG. 4 is a structural diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 4 is
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the semiconductor memory device according to the first embodiment;
  • FIG. 10 is a diagram for explaining a method of manufacturing a semiconductor memory device according to a second embodiment;
  • FIG. 10 is a diagram for explaining a method of manufacturing a semiconductor memory device according to a third embodiment;
  • FIG. 10 is a diagram for explaining a method of manufacturing a semiconductor memory device according to a third embodiment;
  • FIG. 10 is a diagram for explaining a write operation of a conventional DRAM memory cell that does not have a capacitor;
  • FIG. 4 is a diagram for explaining operational problems of a conventional DRAM memory cell that does not have a capacitor;
  • FIG. 2 illustrates a read operation of a DRAM memory cell without a conventional capacitor;
  • dynamic flash memory a semiconductor memory device
  • FIG. 1 The structure, operation mechanism, and manufacturing method of the dynamic flash memory cell according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 5.
  • FIG. 1 The structure of a dynamic flash memory cell will be described with reference to FIG. Then, a data erasing mechanism will be described with reference to FIG. 2, a data writing mechanism will be described with reference to FIG. 3, and a data writing mechanism will be described with reference to FIG. Then, a method of manufacturing a dynamic flash memory will be described with reference to FIG.
  • FIG. 1 shows the structure of a dynamic flash memory cell according to a first embodiment of the invention.
  • a silicon semiconductor pillar 2 (an example of a ⁇ semiconductor pillar'' in the claims) (hereinafter referred to as a ⁇ Si pillar'') is placed on a substrate 1 (an example of a ⁇ substrate'' in the scope of claims). ).
  • the Si pillar 2 includes, from the bottom, an N + layer 3a (which is an example of a "first impurity layer” in the claims), a semiconductor region 7 containing acceptor impurities (hereinafter, a semiconductor region containing acceptor impurities is referred to as “ (referred to as a "P layer”), and an N + layer 3b (which is an example of a "second impurity layer” in the scope of claims).
  • the P layer 7 between the N + layers 3a and 3b becomes a channel region 7a.
  • a first gate insulating layer 4a (which is an example of the "first gate insulating layer” in the scope of claims) surrounds the lower portion of the Si pillar 2, and a second gate insulating layer surrounds the upper portion of the Si pillar 2.
  • first gate conductor layer 5a Surrounding the first gate insulating layer 4a is a first gate conductor layer 5a (which is an example of the "first gate conductor layer” in the claims), and surrounding the second gate insulating layer 4b. Then, there is a second gate conductor layer 5b (which is an example of the "second gate conductor layer” in the claims). The first gate conductor layer 5 a and the second gate conductor layer 5 b are separated by an insulating layer 6 .
  • a dynamic flash memory cell comprising N + layers 3a and 3b, P layer 7, first gate insulating layer 4a, second gate insulating layer 4b, first gate conductor layer 5a and second gate conductor layer 5b is formed. is formed.
  • the N + layer 3a serves as a source line SL (an example of a "source line” in the claims), and the N + layer 3b serves as a bit line BL (a "bit line” in the claims).
  • the first gate conductor layer 5a corresponds to the plate line PL (which is an example of the "plate line” in the claims)
  • the second gate conductor layer 5b corresponds to the word line WL (which is an example of the "plate line” in the claims). (which is an example of the "word line” in the claims).
  • the gate capacitance of the first gate conductor layer 5a connected to the plate line PL is larger than the gate capacitance of the second gate conductor layer 5b connected to the word line WL. It is desirable to have
  • first gate conductor layer 5a may be divided into two or more, and each of them may be operated synchronously or asynchronously as a conductor electrode of the first plate line.
  • second gate conductor layer 5b may be divided into two or more, each of which may be operated synchronously or asynchronously as a conductor electrode of the word line WL. This also provides dynamic flash memory operation.
  • FIG. 2(a) shows a state in which the hole groups 10 generated by impact ionization in the previous cycle are stored in the channel region 7a before the erasing operation. and.
  • V ERA is, for example, -3V.
  • V FB V ERA +Vb.
  • the threshold voltage of the second gate conductor layer 5b connected to this word line WL is increased.
  • the erased state of this channel region 7a is logical storage data "0". Note that the voltage conditions applied to the bit line BL, the source line SL, the word line WL, and the plate line PL and the potential of the floating body described above are only examples for performing the erase operation, and other operating conditions under which the erase operation can be performed. may be
  • FIG. 3 shows the write operation of a dynamic flash memory cell.
  • 0 V for example, is input to the N + layer 3a connected to the source line SL
  • 3 V for example, is input to the N + layer 3b connected to the bit line BL
  • the plate line PL 2 V for example, is input to the connected first gate conductor layer 5a
  • 5 V for example, is input to the second gate conductor layer 5b connected to the word line WL.
  • an annular inversion layer Ra is formed in the channel region 7a inside the first gate conductor layer 5a to which the plate line PL is connected.
  • the first N-channel MOS transistor region having conductor layer 5a is operated in the saturation region.
  • a pinch-off point P exists in the inversion layer Ra inside the first gate conductor layer 5a to which the plate line PL is connected.
  • the second N-channel MOS transistor region having the second gate conductor layer 5b connected to the word line WL is operated in the linear region.
  • an inversion layer Rb is formed all over the channel region 7a inside the second gate conductor layer 5b connected to the word line WL without any pinch-off point.
  • the inversion layer Rb formed entirely inside the second gate conductor layer 5b connected to the word line WL is a substantial drain of the first N-channel MOS transistor region having the first gate conductor layer 5a.
  • the electric field is maximum at the first boundary region of , and the impact ionization phenomenon occurs in this region. Since this region is the region on the source side viewed from the second N-channel MOS transistor region having the second gate conductor layer 5b connected to the word line WL, this phenomenon is called the source-side impact ionization phenomenon.
  • the generated hole group 10 is majority carriers in the channel region 7a, and charges the channel region 7a to a positive bias. Since the N + layer 3a connected to the source line SL is at 0 V, the channel region 7a is at the built-in voltage Vb (approximately 0 V) of the PN junction between the N + layer 3a connected to the source line SL and the channel region 7a. .7V).
  • Vb approximately 0 V
  • the threshold voltages of the first N-channel MOS transistor region and the second N-channel MOS transistor region are lowered due to the substrate bias effect. Thereby, as shown in FIG. 3(c), the threshold voltage of the second N-channel MOS transistor region connected to word line WL is lowered.
  • the write state of this channel region 7a is assigned to logical storage data "1".
  • a second boundary region between the N + layer 3a and the channel region 7a, or a second boundary region between the N + layer 3b and the channel region 7a may be generated by the impact ionization phenomenon or the GIDL current in the boundary region 3, and the channel region 7a may be charged with the generated hole group 10.
  • FIG. The voltage conditions applied to the bit line BL, the source line SL, the word line WL, and the plate line PL are only examples for performing the write operation, and other voltage conditions that allow the write operation may be used.
  • FIGS. 4A and 4B A read operation of the dynamic flash memory cell will be described with reference to FIGS. 4A and 4B.
  • the read operation of the dynamic flash memory cell will be described with reference to FIGS. 4A(a) to 4A(c).
  • FIG. 4A(a) when the channel region 7a is charged to the built-in voltage Vb (approximately 0.7 V), the threshold voltage drops due to the substrate bias effect. This state is assigned to logical storage data "1".
  • FIG. 4A(b) when the memory block selected before writing is in the erased state "0" in advance, the channel region 7a has the floating voltage V FB of V ERA +Vb.
  • a write operation randomly stores a write state of "1".
  • logical storage data of logical "0" and "1" are created for the word line WL.
  • reading is performed by the sense amplifier using the level difference between the two threshold voltages for the word line WL.
  • FIG. 4B(a) to FIG. 4B(d) are used to compare the magnitude relationship between the gate capacitances of the two first gate conductor layers 5a and the second gate conductor layers 5b during the read operation of the dynamic flash memory cell. , the related operations are explained.
  • the gate capacitance of the second gate conductor layer 5b connected to the word line WL is preferably designed to be smaller than the gate capacitance of the first gate conductor layer 5a connected to the plate line PL.
  • the vertical length of the first gate conductor layer 5a connected to the plate line PL is greater than the vertical length of the second gate conductor layer 5b connected to the word line WL.
  • FIG. 4B(b) shows an equivalent circuit of one cell of the dynamic flash memory of FIG. 4B(a).
  • FIG. 4B(c) shows the coupling capacity relationship of the dynamic flash memory.
  • CWL is the capacitance of the second gate conductor layer 5b
  • CPL is the capacitance of the first gate conductor layer 5a
  • CBL is the capacitance between the N + layer 3b serving as the drain and the channel region 7a
  • C SL is the capacitance of the PN junction between the N + layer 3a serving as the source and the channel region 7a.
  • the operation affects the channel region 7a as noise.
  • V ReadWL is the amplitude potential at the time of reading the word line WL.
  • ⁇ V FB can be reduced by reducing the contribution of C WL compared to the total capacitance C PL +C WL +C BL +C SL of the channel region 7a.
  • the memory cell in plan view .DELTA.V.sub.FB may be made even smaller without reducing the integration density.
  • the voltage conditions applied to the bit line BL, the source line SL, the word line WL, and the plate line PL, and the potential of the floating body described above are examples for performing the read operation, and other operating conditions under which the read operation can be performed. may be
  • FIGS. 5A to 5M A method for manufacturing the semiconductor memory device according to the first embodiment will be described with reference to FIGS. 5A to 5M.
  • (a) is a plan view of one memory cell of the semiconductor memory device
  • (b) is a cross-sectional view along line XX' in (a)
  • (c) is a ) along the line YY'.
  • a memory device a large number of memory cells are arranged two-dimensionally.
  • an N + layer 12 (an example of a "first impurity layer” in the claims) is placed on a P-layer substrate 11 (an example of a "substrate” in the claims) from below. ), a first insulating layer 13 (which is an example of the "first insulating layer” in the claims), a silicon nitride (SiN) layer 14a (an example of the "first material layer” in the claims) ), the second insulating layer 15 (which is an example of the “second insulating layer” in the claims), and the SiN layer 14b (which is an example of the “second material layer” in the claims) , a third insulating layer 17 (an example of a "third insulating layer” in the scope of claims), and a third material layer 18 (an example of a "third material layer” in the scope of claims) to form
  • an epitaxial crystal growth method is used to form Si pillars 22 (which are an example of "semiconductor pillars" in the scope of claims) in the holes 20 .
  • the top surface is grown to be above the top surface of the third material layer 18, and then the top surface is moved to the top by CMP (Chemical Mechanical Polishing).
  • CMP Chemical Mechanical Polishing
  • a Si pillar 22 is formed by polishing so as to be positioned on the upper surface of the material layer 18 of No. 3 .
  • heat treatment is performed to diffuse the donor impurities of the N + layer 12 into the Si pillars 22 to form the N + layer 12a.
  • holes 23a which are examples of "second holes” in the claims
  • 23b second holes in the claims
  • second holes which is an example of "third vacancies”
  • a large number of Si pillars are arranged two-dimensionally. It becomes a support connected to the layer 18 . This support prevents the second insulating layer 15, the third insulating layer 17 and the third material layer 18 from bending or breaking during the formation of the holes 23a, 23b.
  • a dummy Si pillar is formed outside the block region in which the Si pillars are two-dimensionally arranged, and in a plan view, the second insulating layer 15 and the third insulating layer, one side of which floats, are formed outside the dummy Si pillar. 17.
  • the second insulating layer 15, the third insulating layer 17 and the third material layer 18 are cleaned and the SiN layers 14a and 14b are etched. Damage can be prevented.
  • the exposed Si pillars 22 are oxidized to form SiO 2 layers 25a (which are examples of the “first gate insulating layer” in the claims), 25b (the ), 25c is formed.
  • doped poly-Si layers 26a and 26b containing a large amount of donor or acceptor impurities are formed in the holes 23a and 23b.
  • a doped poly-Si layer is formed on the third material layer 18 and the SiO2 layer 25c. This doped poly-Si layer is polished and removed by the CMP method. At the same time, the SiO2 layer 25c is also removed. Then, a fifth insulating layer 28 is formed over the entire surface.
  • photolithography and RIE are used to form a third material layer 18a surrounding the Si pillar 22 and extending in the XX′ line direction in plan view, and a fifth insulating layer. 28a.
  • the third insulating layer 17, the doped poly-Si layer 26b, the second insulating layer 15, and the doped poly-Si are etched.
  • Layer 26a is etched to form third insulating layer 17a, doped poly-Si layer 26aa (which is an example of the "first gate conductor layer” in the claims), second insulating layer 15a, and doped poly-Si layer 26ba ( (which is an example of the "second gate conductor layer” in the claims) is formed.
  • a SiO 2 layer (not shown) is deposited on the entire surface by CVD (Chemical Vapor Deposition). Then, a SiO 2 layer 30 whose upper surface is located at the upper surface of the fifth insulating layer 28a is formed by polishing by the CMP method.
  • the third material layer 18a above the third insulating layer 17a and the fifth insulating layer 28a are removed.
  • the upper layer of the SiO 2 layer 30 is removed to form a SiO 2 layer 30a.
  • the tops of the Si pillars 22 are exposed.
  • an N + layer 32 (an example of the "second impurity layer” and “third impurity layer” in the claims) is formed by selective epitaxial crystal growth.
  • a SiO 2 layer 34 is formed on the N + layer 32 and the third insulating layer 17a.
  • a contact hole 35 is formed in the SiO 2 layer 34 on the N + layer 32 .
  • a metal wiring layer 36 connected to the N + layer 32 through the contact hole 35 and extending in the YY' line direction is formed.
  • N + layer 12a is connected to source line SL
  • doped poly-Si layer 26aa is connected to plate line PL
  • doped poly-Si layer 26ba is connected to word line WL
  • metal wiring layer 36 is connected to bit line BL.
  • a dynamic flash memory is thus formed on the P-layer substrate 11 .
  • the Si pillar 22 may be formed of another semiconductor layer.
  • the doped poly-Si layers 26a and 26b may be conductor layers made of other metals or alloys.
  • the first insulating layer 13, the second insulating layer 15, and the third insulating layer 17 are insulating layers made of a single layer such as a SiO2 layer, a SiN layer, an alumina ( Al2O3 ) layer, or a plurality of layers. Layers may be used.
  • the fourth insulating layer 28 has a role of protecting the top of the Si pillar 22 from RIE etching, so it may be a layer of other material regardless of the insulating layer.
  • the third insulating layer 17 and the third material layer 18 may be formed of one insulating layer. In this case, in FIG. 5K, it is necessary to leave an insulating layer having a thickness corresponding to that of the third insulating layer 17 in the step of exposing the top of the Si pillar 22 .
  • the formation of the N + layer 12a was performed by heat treatment in the process of FIG. 5D.
  • the N + layer 12a may be formed in any step after the Si pillar 22 is formed.
  • the N + layer is not formed on the top of the Si pillar 22, but the N + layer ( (which is an example of the "fourth impurity layer" in the claims) may be formed. It is also possible to form the N + layer on the top of the Si pillar 22 and not form the N + layer 32 by the selective epitaxial crystal growth method.
  • the Si pillars 22 are formed by epitaxial crystal growth, but may be formed by other methods such as molecular beam crystal growth and ALD (Atomic Layer Deposition).
  • the doped poly-Si layers 26a and 26b are formed so as to surround the Si pillar 22 as a whole in plan view.
  • the doped poly-Si layers 26a and 26b may be divided into two in plan view.
  • the holes 20 are formed close to adjacent holes (not shown) in the XX' direction.
  • the SiO 2 layers 25a and 25b in FIG. 5F the SiO 2 layers 25a and 25b are formed so as to be in contact with the SiO 2 layer (not shown) surrounding the adjacent Si pillars (not shown). .
  • the doped poly-Si layers 26a and 26b can be separated in the YY' line direction and extended in the XX' line direction.
  • the dynamic flash memory operation can be performed by synchronously or asynchronously driving the conductor layers connected to the divided plate lines PL or word lines WL.
  • a buried conductor layer such as a W layer may be provided around the N + layer 12a.
  • a metal wiring layer connected to the N + layer 12a may be provided around the block region of the memory cells arranged two-dimensionally and connected to the source line SL.
  • the dynamic flash memory operation can also be performed in a structure in which the polarities of the conductivity types of N + layers 3a, 3b and P layer 7 are reversed in FIG. In this case, majority carriers in the Si pillar 2 become electrons. Therefore, a group of electrons generated by impact ionization is stored in the channel region 7a, and the "1" state is set. This also applies to FIG.
  • This embodiment provides the following features.
  • Feature 1 When a dynamic flash memory cell performs write and read operations, the voltage on word line WL swings up and down. At this time, the plate line PL serves to reduce the capacitive coupling ratio between the word line WL and the channel region 7 . As a result, the influence of the voltage change in the channel region 7 when the voltage of the word line WL swings up and down can be significantly suppressed. As a result, the threshold voltage difference between the MOS transistor regions of the word line WL indicating logic "0" and “1” can be increased. This leads to increased operating margins for dynamic flash memory cells.
  • the doped poly-Si layer 26a connected to the plate line PL and the doped poly-Si layer 26b connected to the word line WL are determined by the thicknesses of the SiN layers 14a and 14b as shown in FIG. 5A.
  • the thickness of the SiN layers 14a and 14b can be controlled with high precision by the deposition time when formed by, for example, a CVD (Chemical Vapor Deposition) method. As a result, variations in voltage change in the channel region 7 can be reduced, and as a result, the operating margin can be expanded.
  • SiO 2 layers 25a and 25b which are gate insulating layers, can be easily formed by oxidizing the exposed surfaces of the Si pillars 22 in the holes 23a and 23b. . This simplifies the manufacturing of the dynamic flash memory.
  • FIG. 6 (a) is a plan view of one memory cell of a semiconductor memory device, (b) is a cross-sectional view taken along line XX' in FIG. (a), and FIG. FIG. 3 is a cross-sectional view taken along line YY'; In a memory device, many memory cells are arranged two-dimensionally.
  • FIGS. 5A to 5F are performed to form SiO 2 layers 25a and 25b, and then, as shown in FIG . 40a and 40b (which is an example of the "third gate insulating layer" in the claims) are formed. Then, doped poly-Si layers 26a and 26b are formed. Then, steps similar to those shown in FIGS. 5H to 5M are performed. A dynamic flash memory is thus formed on the P-layer substrate 11 .
  • the HfO 2 layers 40a and 40b may be formed of a single layer or multiple layers of other insulating material as long as they serve as gate insulating layers.
  • the doped poly-Si layers 26a and 26b may be conductor layers made of other metals or alloys.
  • This embodiment provides the following features. As shown in FIG. 5, when the gate insulating layer is formed of only the SiO 2 layers 25a and 25b, the SiO 2 layers 25a and 25b become thicker and the effective diameter of the Si pillar 22 serving as the channel becomes smaller. As a result, the volume of the channel for storing holes, which are signals, is reduced, leading to a reduction in operating margin. In contrast, in the present embodiment, the HfO 2 layers 40a and 40b are formed outside the SiO 2 layers 25a and 25b to suppress the reduction in the diameter of the Si pillar 22 and increase the capacitance of the predetermined gate insulating layer. can be formed.
  • FIGS. 7A and 7B A method for manufacturing the semiconductor memory device according to the third embodiment will be described with reference to FIGS. 7A and 7B.
  • 7A and 7B (a) is a plan view of one memory cell of the semiconductor memory device, (b) is a cross-sectional view along line XX' in (a), and (c) is a FIG. 3 is a cross-sectional view taken along line YY';
  • a memory device many memory cells are arranged two-dimensionally in a memory cell region.
  • the third material layer 18a and the fifth insulating layer 28a are used as an etching mask to form the third insulating layer 17 and the doped poly-Si layer, as shown in FIG. 7A.
  • 26b are etched to form a third insulating layer 17a and a doped poly-Si layer 26ba (which is an example of the "second gate conductor layer" in the claims).
  • the doped poly-Si layer 26a remains without being etched, and is formed connecting adjacent Si pillars (not shown).
  • the doped poly-Si layer 26aa connected to the plate line PL has the same shape as the doped poly-Si layer 26ba connected to the word line WL in a plan view.
  • the doped poly-Si layer 26a connected to the plate line PL remains unetched and is formed connecting between adjacent Si pillars (not shown). A dynamic flash memory is thus formed on the P-layer substrate 11 .
  • This embodiment provides the following features.
  • processing by etching of the doped poly-Si layer 26a connected to the plate line PL is not required within the memory cell region. This facilitates the manufacture of dynamic flash memory.
  • the gate capacitance of the first gate conductor layer 5a connected to the plate line PL is made larger than the gate capacitance of the second gate conductor layer 5b connected to the word line WL.
  • the gate length of the first gate conductor layer 5a is made longer than the gate length of the second gate conductor layer 5b.
  • the gate length of the first gate conductor layer 5a is not made longer than the gate length of the second gate conductor layer 5b, and the thickness of the gate insulation film of the first gate insulation layer 4a is increased. , may be thinner than the thickness of the gate insulating film of the second gate insulating layer 4b.
  • the dielectric constant of the first gate insulating layer 4a may be higher than that of the second gate insulating layer 4b. Further, the length of the first gate conductor layer 5a and the second gate conductor layer 5b, the film thickness of the first gate insulating layer 4a and the second gate insulating layer 4b, and the dielectric constant are combined to obtain the The gate capacitance of one gate conductor layer 5a may be larger than the gate capacitance of the second gate conductor layer 5b. This also applies to other embodiments.
  • the vertical length of the first gate conductor layer 5a connected to the plate line PL is made longer than the vertical length of the first gate conductor layer 5b connected to the word line WL.
  • the addition of the plate line PL alone reduces the capacitive coupling ratio (C WL /(C PL +C WL +C BL +C SL )) for the channel region 7a of the word line WL1.
  • the potential variation ⁇ V FB of the channel region 7a of the floating body is reduced. This also applies to other embodiments.
  • the voltage of the plate line PL in the description of this embodiment may be, for example, a fixed voltage regardless of each operation mode. Also, the voltage of the plate line PL may be applied, for example, 0 V only when erasing. Also, the voltage of the plate line PL may be a fixed voltage or a voltage that varies with time as long as it satisfies the conditions for dynamic flash memory operation.
  • the shape of the Si pillar 2 in plan view in FIG. 1 is circular, it may be other than circular, such as an ellipse or a shape elongated in one direction. This also applies to other embodiments.
  • the source line SL is negatively biased during the erasing operation to pull out the group of holes in the channel region 7a, which is the floating body FB, but the erasing operation is performed under other voltage conditions.
  • N + layer 3a and the P layer 7 there may be an N-type impurity layer or a P-type impurity layer having a different acceptor impurity concentration.
  • An N - type or P-type impurity layer may be provided between N + layer 3 b and P layer 7 . This also applies to other embodiments.
  • the N + layers 3a, 3b of FIG. 1 may be formed of Si or other semiconductor material layers containing donor impurities. Also, the N + layer 3a and the N + layer 3b may be formed of different semiconductor material layers. This also applies to other embodiments.
  • the Si pillars 22 in FIG. 5 may be arranged two-dimensionally in a square lattice or an orthorhombic lattice.
  • the Si pillars connected to one word line may be arranged in a zigzag or sawtooth shape with a plurality of Si pillars as one side. This also applies to other embodiments.
  • SOI and multi-layer wells may be used instead of the P-layer substrate 11 in FIG. This also applies to other embodiments.
  • the first gate conductor layer 5a and the second gate conductor layer 5b are each formed of one conductor material layer. good.
  • an insulating layer may be provided between each conductor material layer. For example, having the same thickness for these conductor material layers provides the advantage of uniform embedding of the doped poly-Si layer in FIG. 5G.
  • the plate line conductor layers in each stage extend in the same direction as the first gate conductor layer in plan view.
  • the word line conductor layer in each stage extends in the same direction as the second gate conductor layer, and the word line conductor layer in each stage and the plate line conductor layer extend in the same direction.
  • a high-density and high-performance dynamic flash memory can be obtained.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
PCT/JP2021/039319 2021-10-25 2021-10-25 半導体メモリ装置の製造方法 Ceased WO2023073765A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2021/039319 WO2023073765A1 (ja) 2021-10-25 2021-10-25 半導体メモリ装置の製造方法
JP2023555893A JPWO2023073765A1 (https=) 2021-10-25 2021-10-25
TW111140269A TWI838924B (zh) 2021-10-25 2022-10-24 半導體記憶裝置的製造方法
US17/971,789 US20230127781A1 (en) 2021-10-25 2022-10-24 Production method for semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/039319 WO2023073765A1 (ja) 2021-10-25 2021-10-25 半導体メモリ装置の製造方法

Publications (1)

Publication Number Publication Date
WO2023073765A1 true WO2023073765A1 (ja) 2023-05-04

Family

ID=86056761

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/039319 Ceased WO2023073765A1 (ja) 2021-10-25 2021-10-25 半導体メモリ装置の製造方法

Country Status (4)

Country Link
US (1) US20230127781A1 (https=)
JP (1) JPWO2023073765A1 (https=)
TW (1) TWI838924B (https=)
WO (1) WO2023073765A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022269890A1 (ja) * 2021-06-25 2022-12-29 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置の製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000340679A (ja) * 1999-05-10 2000-12-08 Internatl Business Mach Corp <Ibm> ボディ・コンタクト式ダイナミック・メモリ
JP2003086712A (ja) * 2001-02-19 2003-03-20 Toshiba Corp 半導体メモリ装置及びその製造方法
JP2003188279A (ja) * 2001-12-14 2003-07-04 Toshiba Corp 半導体メモリ装置およびその製造方法
JP2009026448A (ja) * 2007-07-20 2009-02-05 Samsung Electronics Co Ltd メモリセル構造、メモリセルアレイ、メモリ装置、メモリ制御器、メモリシステム及びこれらを動作する方法
JP2012015517A (ja) * 2010-07-02 2012-01-19 Samsung Electronics Co Ltd 垂直的に集積された不揮発性記憶セルサブストリングを含む不揮発性記憶装置の形成方法、及び形成された不揮発性記憶装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100675297B1 (ko) * 2005-12-19 2007-01-29 삼성전자주식회사 캐패시터가 없는 동적 메모리 셀을 구비한 반도체 메모리장치 및 이 장치의 배치 방법
JP5078338B2 (ja) * 2006-12-12 2012-11-21 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7919800B2 (en) * 2007-02-26 2011-04-05 Micron Technology, Inc. Capacitor-less memory cells and cell arrays
KR101603731B1 (ko) * 2009-09-29 2016-03-16 삼성전자주식회사 버티칼 낸드 전하 트랩 플래시 메모리 디바이스 및 제조방법
TWI404956B (zh) * 2010-09-20 2013-08-11 Himax Display Inc 液晶顯示面板的測試方法
KR20150020847A (ko) * 2013-08-19 2015-02-27 에스케이하이닉스 주식회사 3차원 반도체 장치, 이를 구비하는 저항 변화 메모리 장치, 및 그 제조방법
CN107592943B (zh) * 2015-04-29 2022-07-15 芝诺半导体有限公司 提高漏极电流的mosfet和存储单元
US20230363138A1 (en) * 2022-05-06 2023-11-09 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and fabricating methods thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000340679A (ja) * 1999-05-10 2000-12-08 Internatl Business Mach Corp <Ibm> ボディ・コンタクト式ダイナミック・メモリ
JP2003086712A (ja) * 2001-02-19 2003-03-20 Toshiba Corp 半導体メモリ装置及びその製造方法
JP2003188279A (ja) * 2001-12-14 2003-07-04 Toshiba Corp 半導体メモリ装置およびその製造方法
JP2009026448A (ja) * 2007-07-20 2009-02-05 Samsung Electronics Co Ltd メモリセル構造、メモリセルアレイ、メモリ装置、メモリ制御器、メモリシステム及びこれらを動作する方法
JP2012015517A (ja) * 2010-07-02 2012-01-19 Samsung Electronics Co Ltd 垂直的に集積された不揮発性記憶セルサブストリングを含む不揮発性記憶装置の形成方法、及び形成された不揮発性記憶装置

Also Published As

Publication number Publication date
TWI838924B (zh) 2024-04-11
US20230127781A1 (en) 2023-04-27
JPWO2023073765A1 (https=) 2023-05-04
TW202333351A (zh) 2023-08-16

Similar Documents

Publication Publication Date Title
JP7335661B2 (ja) 半導体素子を用いたメモリ装置の製造方法
WO2023084565A1 (ja) 半導体メモリ装置及び半導体メモリ装置の製造方法
US11968822B2 (en) Memory device using semiconductor element
TWI823513B (zh) 具有記憶元件之半導體裝置的製造方法
US12144164B2 (en) Method for manufacturing memory device using semiconductor element
WO2022208658A1 (ja) メモリ素子を有する半導体装置
WO2023032193A1 (ja) 半導体素子を用いたメモリ装置
WO2022239237A1 (ja) 半導体素子を用いたメモリ装置
WO2022219767A1 (ja) メモリ素子を有する半導体装置
TWI810929B (zh) 使用半導體元件的記憶裝置的製造方法
WO2023148799A1 (ja) 半導体素子を用いたメモリ装置
TWI800198B (zh) 使用柱狀半導體元件的記憶體裝置的製造方法
JP7057033B1 (ja) 半導体素子を用いたメモリ装置の製造方法
WO2023166608A1 (ja) 半導体素子を用いたメモリ装置
WO2023162036A1 (ja) 半導体メモリ装置
TWI838924B (zh) 半導體記憶裝置的製造方法
US20230171945A1 (en) Semiconductor memory device and manufacturing method of semiconductor memory device
TWI800228B (zh) 使用半導體元件的記憶裝置
US20220310608A1 (en) Memory device using semiconductor element and method for manufacturing the same
WO2022239102A1 (ja) 半導体素子を用いたメモリ装置
WO2023281730A1 (ja) 半導体素子を用いたメモリ装置
WO2022168219A1 (ja) 柱状半導体素子を用いたメモリ装置
TWI810791B (zh) 使用柱狀半導體元件之記憶裝置的製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21961611

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2023555893

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21961611

Country of ref document: EP

Kind code of ref document: A1