WO2023005443A1 - 显示面板的控制电路和显示装置 - Google Patents

显示面板的控制电路和显示装置 Download PDF

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Publication number
WO2023005443A1
WO2023005443A1 PCT/CN2022/097860 CN2022097860W WO2023005443A1 WO 2023005443 A1 WO2023005443 A1 WO 2023005443A1 CN 2022097860 W CN2022097860 W CN 2022097860W WO 2023005443 A1 WO2023005443 A1 WO 2023005443A1
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WO
WIPO (PCT)
Prior art keywords
electronic switch
level
level signal
signal
clock signal
Prior art date
Application number
PCT/CN2022/097860
Other languages
English (en)
French (fr)
Inventor
沈婷婷
康报虹
Original Assignee
惠科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to JP2022576403A priority Critical patent/JP2023538714A/ja
Priority to EP22813391.4A priority patent/EP4379702A1/en
Priority to KR1020227042045A priority patent/KR102612204B1/ko
Publication of WO2023005443A1 publication Critical patent/WO2023005443A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present application relates to the field of display technology, in particular to a control circuit and a display device of a display panel.
  • GDL Gate Driver Less, Array Substrate Row Drive
  • the gate driver IC Gate driver IC
  • the gate is scanned row by row by outputting row drive signals.
  • GDL technology can simplify the manufacturing process of the display panel, save the chip bonding (Bonding) process in the direction of the horizontal scanning line, and reduce the production cost. At the same time, it can improve the integration of the display panel and make the display panel lighter and thinner.
  • Display panels using GDL technology need to use multiple clock signals to control the gate drive circuit to output row drive signals. As the size and resolution of display panels continue to increase, the number of gate drive circuits for each display panel also continues to increase, resulting in The load of a single clock signal is too high, which degrades the operation stability of the display panel.
  • One of the purposes of the embodiments of the present application is to provide a control circuit and a display device for a display panel, aiming at solving the problem that the existing GDL technology-based display panel gate drive circuits continue to increase in number, resulting in an excessively high load on a single clock signal. , the problem of degrading the operation stability of the display panel.
  • a control circuit of a display panel is provided, the control circuit is used for receiving a first clock signal, a first level signal and a second level signal, and according to the first level signal and the second level signal A two-level signal, shifting the phase of the first clock signal to obtain a second clock signal and outputting it to the gate drive circuit; wherein the second clock signal includes a third level signal and a fourth level signal, so The levels of the third level signal and the fourth level signal are different;
  • the control circuit includes a first switch unit and a second switch unit, the first switch unit is connected to the second switch unit;
  • the first switch unit is configured to receive the first clock signal, the first level signal and the second level signal, and according to the first clock signal, the first level signal and the a second level signal, outputting a third level signal to the gate drive circuit;
  • the second switch unit is configured to receive the first clock signal, the first level signal and the second level signal, and according to the first clock signal, the first level signal and the A second level signal, outputting a fourth level signal to the gate drive circuit.
  • a display device including a display panel
  • control unit includes the control circuit described in the first aspect above.
  • the first aspect of the embodiments of the present application provides a control circuit for a display panel, configured to receive a first clock signal, a first level signal, and a second level signal, and according to the first level signal and the second level signal, phase-shift the first clock signal to obtain a second clock signal and output it to the gate drive circuit, realize the phase-shift of the clock signal, so as to reduce the load of a single clock signal, and can reduce the clock signal in the display panel
  • the number of generators reduces the production cost of the display panel.
  • FIG. 1 is a first structural schematic diagram of a control circuit of a display panel provided by an embodiment of the present application
  • FIG. 2 is a second structural schematic diagram of a control circuit of a display panel provided by an embodiment of the present application
  • FIG. 3 is a third structural schematic diagram of a control circuit of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a fourth structure of a control circuit of a display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a fifth structure of a control circuit of a display panel provided by an embodiment of the present application.
  • Fig. 6 shows the first clock signal, the gate level of the second electronic switch, the drain level of the second electronic switch, the gate level of the fourth electronic switch, the third level signal, A timing diagram of the fourth level signal and the second clock signal;
  • FIG. 7 is a schematic diagram of a sixth structure of a control circuit of a display panel provided by an embodiment of the present application.
  • FIG. 8 is a seventh structural schematic diagram of a control circuit of a display panel provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an eighth structure of a control circuit of a display panel provided by an embodiment of the present application.
  • Figure 10 shows the first clock signal, the gate level of the tenth electronic switch, the drain level of the tenth electronic switch, the gate level of the twelfth electronic switch, and the fifth level signal provided by the embodiment of the present application , a timing diagram of the sixth level signal and the second clock signal;
  • FIG. 11 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • references to "one embodiment” or “some embodiments” or the like in the specification of the present application means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • appearances of the phrases “in one embodiment,” “in some embodiments,” “in other embodiments,” “in other embodiments,” etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless specifically stated otherwise.
  • the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless specifically stated otherwise.
  • the embodiment of the present application provides a control circuit for a display panel, which can be applied to a display panel, and the display panel can be based on a TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display) technology liquid crystal display panel, based on LCD (Liquid Crystal Display, liquid crystal display) technology liquid crystal display panel, based on OLED (Organic Light-Emitting Diode (Organic Light-Emitting Diode) technology organic electro-laser display panel, based on QLED (Quantum Dot Light Emitting Diodes, quantum dot light emitting diode) technology quantum dot light emitting diode display panel or curved display panel, etc.
  • TFT-LCD Thi Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display
  • LCD Liquid Crystal Display, liquid crystal display
  • OLED Organic Light-Emitting Diode
  • organic electro-laser display panel based on QLED (Quantum Dot Light Emitting
  • the control circuit 10 of the display panel provided by the embodiment of the present application is used to receive the first clock signal, the first level signal and the second level signal, and according to the first level signal and a second level signal, phase-shift the first clock signal to obtain a second clock signal and output it to the gate drive circuit 20; wherein, the second clock signal includes a third level signal and a fourth level signal, and the second The levels of the three-level signal and the fourth-level signal are different;
  • the control circuit 10 includes a first switch unit 11 and a second switch unit 12, the first switch unit 11 is connected to the second switch unit 12;
  • the first switch unit 11 is used to receive the first clock signal, the first level signal and the second level signal, and output the third level signal to Gate drive circuit 20;
  • the second switch unit 12 is used to receive the first clock signal, the first level signal and the second level signal, and output the fourth level signal to Gate drive circuit 20.
  • Fig. 1 only exemplarily shows the connection relationship between the control circuit and the gate drive circuit, the input and output signals of the control circuit, and the input signal of the gate drive circuit;
  • Fig. 2 shows on the basis of Fig. 1
  • the control circuit includes a first switch unit and a second switch unit, and input and output signals of the first switch unit and the second switch unit.
  • the control circuit may include electronic components such as multiple transistors, comparators, logic gates, resistors, capacitors or inductors; the first clock signal, the first level signal and the second level signal may be controlled by the timing controller (Timer Control Register, TCON) or on-chip (System on Chip, SOC) input to the control circuit; the control circuit can shift the phase of the first clock signal according to the first level signal and the second level signal, and the second clock obtained by phase shifting The phase difference between the signal and the first clock signal can range from 0 degrees to 180 degrees, and the phase difference between the second clock signal and the first clock signal can be determined according to the timing of the first level signal and the second level signal; the first Both the clock signal and the second clock signal can be used to output to the gate drive circuit to control the gate drive circuit to output row drive signals to scan the gate of the display panel row by row; specifically, a display panel can include at least one control circuits, the number of control circuits is determined according to the number of clock signals used by the above display panel, each control circuit corresponds to each first first clock
  • n first clock signals and n second clock signals can be used to input a total of 2n clock signals into the gate drive circuit, because a single clock signal can be input into multiple gate drive circuits , when the number of clock signals increases, a single clock signal can reduce the number of input gate drive circuits, thereby reducing the load on a single clock signal, and can reduce the number of clock generators used to generate clock signals, reducing the display panel Cost of production.
  • n is an integer greater than 0, and the number of control circuits can be set according to the actual needs of the display panel.
  • FIG. 3 exemplarily shows a structural diagram of the connection between the first control circuit 101 , the second control circuit 102 to the nth control circuit 103 and the gate drive circuit 20 .
  • the control circuit may include a plurality of switch units, and each switch unit may control whether the switch unit outputs a level signal according to the level of the first clock signal.
  • the control circuit may include a first switch unit and a second clock signal. Two switch units, wherein the first switch unit is used to control the output of the third level signal according to the first clock signal, and the second switch unit is used to control the output of the fourth level signal according to the first clock signal.
  • the first switch unit when the first clock signal is at a high level, the first switch unit can control the third level signal to stop outputting, and the second switching unit can control the fourth level signal to start outputting; when the first clock signal is at a low level, The first switch unit may control the third level signal to start outputting, and the second switch unit may control the fourth level signal to stop outputting. It should be noted that after the display panel enters the working state, the levels of the third level signal and the fourth level signal are different.
  • the fourth level signal when the third level signal is at a high level, the fourth level signal is low level, or, when the third level signal is low level, the fourth level signal is high level, therefore, by integrating the third level signal output by the first switch unit and the first level signal output by the second switch unit
  • the four-level signal can obtain a continuous and uninterrupted second clock signal.
  • the first level signal is a high level signal
  • the second level signal is a low level signal
  • the first switch unit 11 is further configured to conduct and switch on according to the first clock signal, the first level signal and the second level signal when the first clock signal is low Outputting a third level signal to the gate drive circuit 20, the third level signal is at a high level; it is also used when the first clock signal is at a high level, according to the first clock signal, The first level signal and the second level signal are turned off and stop outputting the third level signal to the gate drive circuit 20;
  • the second switch unit 12 is further configured to conduct and output the first clock signal according to the first clock signal, the first level signal and the second level signal when the first clock signal is at a high level.
  • the four-level signal is sent to the gate drive circuit 20, and the fourth level signal is low level; it is also used when the first clock signal is low level, according to the first clock signal, the The first level signal and the second level signal are turned off and stop outputting the fourth level signal to the gate driving circuit 20 .
  • the first switch unit is turned on and outputs the third level signal to the gate drive circuit, at this time the third level signal is high level level, the second switch unit is turned off and stops outputting the fourth level signal to the gate drive circuit, at this time the fourth level signal is not output, therefore, the second clock signal is at high level at this time; when the first clock signal When the level is high, the first switch unit is turned off and stops outputting the third level signal to the gate drive circuit. At this time, the third level signal is not output, and the second switch unit is turned on and outputs the fourth level signal.
  • the flat signal is sent to the gate drive circuit.
  • the fourth level signal is low level, so the second clock signal is low level at this time, thereby realizing the phase shift of the first clock signal, and the phase shift obtained
  • the phase difference between the second clock signal and the first clock signal is 90 degrees.
  • the first switch unit 11 includes a first electronic switch 111, a second electronic switch 112, a third electronic switch 113, a fourth electronic switch switch 114, fifth electronic switch 115 and first capacitor 116;
  • the drain of the first electronic switch 111 is connected to the gate of the second electronic switch 112, and the gate and source of the first electronic switch 111 are used to receive the first clock signal;
  • the drain of the second electronic switch 112 is connected to the source of the fourth electronic switch 114, and the source of the second electronic switch 112 is used to receive the first level signal;
  • the drain of the third electronic switch 113 is respectively connected to the source of the fifth electronic switch 115 and the gate of the fourth electronic switch 114, and the source of the third electronic switch 113 is used to receive the first level signal;
  • the first stage of the first capacitor 116 is respectively connected to the drain of the first electronic switch 111 and the gate of the second electronic switch 112, and the drain of the fifth electronic switch 115 is used to receive the second level signal;
  • the gate of the third electronic switch 113, the drain of the fifth electronic switch 115, the drain of the fourth electronic switch 114 and the second pole of the first capacitor 116 are respectively connected with the second switch
  • the unit is electrically connected.
  • the first electronic switch to the fifth electronic switch can be any device or circuit with electronic switching function, for example, a triode or a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor).
  • Metal Oxide Semiconductor Field Effect Transistor MOSFET
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • TFT thin film field effect transistor
  • the first capacitor can be different types of capacitors such as ceramic capacitors, aluminum electrolytic capacitors, mica capacitors, paper capacitors, tantalum-niobium electrolytic capacitors or film capacitors. The type and capacitance value of the first capacitor can be based on actual needs Make a selection.
  • the second switch unit 12 includes a sixth electronic switch 121, a seventh electronic switch 122, and an eighth electronic switch 123;
  • the drain of the sixth electronic switch 121 is respectively connected to the gate of the third electronic switch and the source of the seventh electronic switch 122, and the gate and source of the sixth electronic switch 121 are used to receive the first level signal;
  • the drain of the seventh electronic switch 122 is respectively connected to the drain of the fifth electronic switch and the source of the eighth electronic switch 123, and the gate of the seventh electronic switch 122 is used to receive the first A clock signal, the drain of the seventh electronic switch 122 is used to receive the second level signal;
  • the drain of the eighth electronic switch 123 is respectively connected to the drain of the fifth electronic switch and the second stage of the first capacitor, and the gate of the eighth electronic switch 123 is used to receive the first clock signal.
  • the types of components of the sixth electronic switch to the eighth electronic switch are the same as those of the above-mentioned first electronic switch to the fifth electronic switch, and will not be repeated here.
  • Fig. 6 exemplarily shows the first clock signal, the gate level of the second electronic switch, the drain level of the second electronic switch, the gate level of the fourth electronic switch, the third level signal, the second Timing diagram of the four-level signal and the second clock signal.
  • the first level signal always outputs a high level signal
  • the second level signal always outputs a low level signal
  • the first clock signal is a periodic clock signal
  • the adjacent rising edges of the first clock signal and The phase difference of the falling edge is 90 degrees; before the control circuit enters the working state, it needs to go through the preparation state; in the first time period, the control circuit enters the first preparation state, and the first clock signal receives a low level, so during the first time period
  • the first electronic switch is turned off, the drain level of the first electronic switch is low level, the gate level of the second electronic switch is low level, the second electronic switch is turned off, and the drain level of the second electronic switch is low.
  • pole level is low level, therefore, the source level of the fourth electronic switch is low level; the gate and source of the sixth electronic switch both receive the first level signal, so that the sixth electronic switch is turned on and If the drain level is high level, then the gate level of the third electronic switch is high level, so that the third electronic switch is turned on, and the source of the third electronic switch receives the first level signal, so the third electronic switch The drain level of the electronic switch is high level, so that the gate level of the fourth electronic switch is high level, and the fourth electronic switch is turned on.
  • the drain level of the fourth electronic switch is low level, and the drain level of the fourth electronic switch is the third level signal, so the third level signal is low level; since the first clock signal input low level level, the fifth electronic switch, the seventh electronic switch and the eighth electronic switch are turned off in the first time period, and the eighth electronic switch does not output the fourth level signal; since the third level signal is low level, the fourth level The signal is not output, therefore, the second clock signal is low.
  • the voltages of the third level signal and the fourth level signal are different.
  • the third level signal can be low level, and the low level can be -3V specifically. , -5V, -6V or -8V, etc., the voltage of the fourth level signal may be 0V; the embodiment of the present application does not impose any limitation on the specific voltage values of the low level and the high level.
  • the control circuit enters the second preparation state in the second time period, and the first clock signal changes from the low level in the first time period to the input high level, so in the second time period, the first electronic switch is turned on And the drain level is high level, so that the gate level of the second electronic switch is high level, the second electronic switch is turned on, and the source of the second electronic switch receives the first level signal, so the second The drain level of the electronic switch is high level; since the grid of the seventh electronic switch receives the high level first clock signal to make it conduction, the high level output by the sixth electronic switch drain can pass through the seventh electronic switch.
  • the switch and the second level signal are released, so that the gate level of the third electronic switch is lowered from high level to low level, and the third electronic switch is turned off, and because the gate of the fifth electronic switch receives a high level
  • the first clock signal makes it turn on, and the high level at the source of the fifth electronic switch is released through the fifth electronic switch and the second level signal, combined with the third electronic switch being turned off, so that the source electrode of the fifth electronic switch level is lowered from high level to low level, the gate level of the fourth electronic switch is lowered from high level to low level, the fourth electronic switch is turned off, and the output of the third level signal is stopped; because the eighth electronic switch
  • the gate of the switch receives the high-level first clock signal to turn on the eighth electronic switch, and since the source of the eighth electronic switch receives the second-level signal and is low, the drain electrode of the eighth electronic switch level is low level, so the fourth level signal is low level; because the output of the third level signal stops, the fourth level signal is low level, so the second clock signal is low
  • the third time period is the time period when the second clock signal outputs a high level, the control circuit enters the first working state, the first clock signal changes from the input high level of the second time period to the input low level, Therefore, the first electronic switch is turned off in the third time period, but because the voltage at the gate of the second electronic switch is in a floating state, assuming that the current voltage at the gate of the second electronic switch is the first voltage, the voltage of the second electronic switch The gate level is still high, the second electronic switch is turned on, the drain level of the second electronic switch is consistent with the drain level of the second electronic switch in the second time period, and the third electronic switch The conduction state of the second electronic switch is consistent with the conduction state of the third electronic switch in the first time period, which will not be repeated here.
  • the gate level of the fifth electronic switch is at a low level
  • the fifth electronic switch is turned off, the gate level of the fourth electronic switch is high level, because the source level of the fourth electronic switch is high level, thus the third level signal is high level
  • the first clock signal is input at low level
  • the gate levels of the seventh electronic switch and the eighth electronic switch are at low level
  • the seventh electronic switch is turned off, the eighth electronic switch is turned off and stops outputting the fourth level signal
  • the third level signal is high level
  • the output of the fourth level signal stops, so the second clock signal is high level
  • the third level signal is high level
  • the second electronic switch gate The voltage at the pole is in a floating state, and the coupling effect of the first capacitor makes the first voltage at the gate of the second electronic switch rise to the second voltage, and the voltage value of the first voltage is determined by the first clock signal when the high level is input.
  • the fourth time period is the time period when the second clock signal outputs a low level, the control circuit enters the second working state, the first clock signal changes from the input low level in the third time period to the input high level, Therefore, in the third time period, the first electronic switch is turned on, the floating state of the voltage at the gate of the second electronic switch is released, and the voltage at the gate of the second electronic switch recovers from the second voltage to the first voltage, and the second electronic switch
  • the switch is turned on, and the drain level of the second electronic switch in the fourth time period is consistent with the drain level of the second electronic switch in the third time period and is at a high level; since the gate of the seventh electronic switch receives The high-level first clock signal turns on the seventh electronic switch, and the high level output by the drain of the sixth electronic switch can be released through the seventh electronic switch and the second level signal, making the gate of the third electronic switch Level is reduced from high level to low level, the third electronic switch is turned off, and because the gate of the fifth electronic switch receives the high level first clock signal to make
  • the working state of the control circuit changes with the level of the first clock signal. Specifically, when the first clock signal is at a low level , the working state of the control circuit is consistent with the first working state of the above-mentioned third time period, and when the first clock signal is at a high level, the working state of the control circuit is consistent with the second working state of the above-mentioned fourth time period, so that the control circuit outputs
  • the phase difference between the second clock signal and the first clock signal is 90 degrees, which realizes the phase shift of the clock signal to reduce the load of a single clock signal, and can reduce the number of clock generators in the display panel and reduce the production of the display panel cost.
  • control circuit 10 includes:
  • the third switch unit 13 is used to receive the first clock signal, the first level signal and the second level signal.
  • the level signal is turned on and outputs the fifth level signal to the gate drive circuit 20, the fifth level signal is high level; it is also used when the first clock signal is low level, according to the first clock signal, the second The first-level signal and the second-level signal are turned on and output a fifth-level signal to the gate drive circuit 20, and the fifth-level signal is low;
  • the fourth switch unit 14 is connected to the third switch unit 13 and is used to receive the first clock signal, the first level signal and the second level signal.
  • the first clock signal is at a high level, according to the first clock signal, The first level signal and the second level signal are turned on and output the sixth level signal to the gate drive circuit 20, the sixth level signal is low level; it is also used when the first clock signal is low level , according to the first clock signal, the first level signal and the second level signal, turn off and stop outputting the sixth level signal.
  • the second clock signal includes a fifth level signal and a sixth level signal.
  • the third switch unit is turned on and outputs the fifth level signal to the gate drive circuit, at this time the fifth level signal is high level level, the fourth switch unit is turned off and stops outputting the sixth level signal to the gate drive circuit, at this time the sixth level signal is not output, therefore, the second clock signal is at high level at this time; when the first clock signal When the level is high, the third switch unit is turned on and outputs the fifth level signal to the gate drive circuit; at this time, the fifth level signal is low level, the fourth switch unit is turned on and outputs the sixth level signal The level signal is sent to the gate drive circuit. At this time, the sixth level signal is at low level. Therefore, at this time, the second clock signal is at low level, thereby realizing the phase shift of the first clock signal, and the phase shift is obtained The phase difference between the second clock signal and the first clock signal is 90 degrees.
  • the third switch unit 13 includes a ninth electronic switch 131, a tenth electronic switch 132, an eleventh electronic switch 133, a twelfth A switch 134, a thirteenth electronic switch 135, a second capacitor 136 and a third capacitor 137;
  • the drain of the ninth electronic switch 131 is respectively connected to the gate of the tenth electronic switch 132, the source of the thirteenth electronic switch 135 and the first pole of the second capacitor 136, and the source of the ninth electronic switch 131 is used to receive first level signal;
  • the drain of the tenth electronic switch 132 is connected to the second pole of the second capacitor 136 and the source of the twelfth electronic switch 134, and the source of the tenth electronic switch 132 is used to receive the first level signal;
  • the gate and source of the eleventh electronic switch 133 are used to receive the first clock signal
  • the gate of the twelfth electronic switch 134 is respectively connected to the first pole of the third capacitor 137 and the drain of the eleventh electronic switch 133;
  • the gate of the thirteenth electronic switch 135 is used to receive the first clock signal
  • the gate of the ninth electronic switch 131 , the drain of the twelfth electronic switch 134 , the drain of the thirteenth electronic switch 135 and the second pole of the third capacitor 137 are respectively electrically connected to the fourth switch unit.
  • the component types of the ninth electronic switch to the thirteenth electronic switch are consistent with the component types of the above-mentioned first electronic switch to the fifth electronic switch, and the types of the second capacitor and the third capacitor are the same as the above-mentioned first The capacitors are of the same type, and will not be repeated here.
  • the capacitance values of the second capacitor and the third capacitor can be set according to actual needs.
  • the fourth switch unit 14 includes a fourteenth electronic switch 141, a fifteenth electronic switch 142, and a sixteenth electronic switch 143;
  • the drain of the fourteenth electronic switch 141 is connected to the gate of the ninth electronic switch and the source of the fifteenth electronic switch 142, and the gate and source of the fourteenth electronic switch 141 are used to receive the first level signal;
  • the drain of the fifteenth electronic switch 142 is respectively connected to the drain of the thirteenth electronic switch and the source of the sixteenth electronic switch 143, the gate of the fifteenth electronic switch 142 is used to receive the first clock signal, and the gate of the tenth electronic switch 142 is used to receive the first clock signal.
  • the drain of the five electronic switch 142 is used to receive the second level signal;
  • the drain of the sixteenth electronic switch 143 is respectively connected to the drain of the twelfth electronic switch and the second pole of the third capacitor, and the gate of the sixteenth electronic switch 143 is used to receive the first clock signal.
  • the types of components of the fourteenth electronic switch to the sixteenth electronic switch are the same as those of the above-mentioned first electronic switch to the fifth electronic switch, and will not be repeated here.
  • Fig. 10 exemplarily shows the first clock signal, the gate level of the tenth electronic switch, the drain level of the tenth electronic switch, the gate level of the twelfth electronic switch, the fifth level signal, Timing diagram of the sixth level signal and the second clock signal.
  • the first level signal always outputs a high level signal
  • the second level signal always outputs a low level signal
  • the first clock signal is a periodic clock signal
  • the adjacent rising edges of the first clock signal and The phase difference of the falling edge is 90 degrees
  • the drain level of the fourteenth electronic switch is always high level
  • the control circuit enters Before the working state, it needs to go through the preparation state
  • the control circuit enters the first preparation state, the first clock signal is input at low level, the eleventh electronic switch, the thirteenth electronic switch, the fifteenth electronic switch and the fifth electronic switch
  • the sixteenth electronic switch is turned off; the high level of the drain of the fourteenth electronic switch is output to the grid of the ninth electronic switch, so that the ninth electronic switch is turned on, and the source of the ninth electronic switch receives the first level signal, so the drain level of the ninth electronic switch is high, so that the gate level of the tenth electronic switch is high, the tenth electronic switch is
  • the control circuit enters the second preparation state in the sixth time period, and the first clock signal changes from the input low level in the fifth time period to the input high level, because the gate of the fifteenth electronic switch receives a high voltage flat first clock signal, the fifteenth electronic switch is turned on, and the high level output by the drain of the fourteenth electronic switch can be released through the fifteenth electronic switch and the second level signal, so that the gate of the ninth electronic switch The level is lowered from high level to low level, the ninth electronic switch is turned off, and because the gate of the thirteenth electronic switch receives the high level first clock signal, the thirteenth electronic switch is turned on, and the thirteenth electronic switch is turned on.
  • the high level at the source of the electronic switch is released through the thirteenth electronic switch and the second level signal, combined with the ninth electronic switch being turned off, the gate level of the tenth electronic switch is reduced from high level to low level , the tenth electronic switch is turned off, and the voltage at the drain of the tenth electronic switch will decrease due to the coupling effect of the second capacitor, therefore, the level of the drain of the tenth electronic switch is low level; since the first clock signal is High level, the eleventh electronic switch is turned on, the grid level of the twelfth electronic switch is high level, the twelfth electronic switch is turned on, the drain level of the twelfth electronic switch is low level, Thus the fifth level signal is low level; since the first clock signal is high level, the sixteenth electronic switch is turned on, and the source of the sixteenth electronic switch receives the second level signal, therefore, the sixteenth electronic switch The level of the drain of the switch is low level, so the sixth level signal is low level; since both the fifth level signal and the sixth level signal are low
  • the seventh time period is the time period when the second clock signal outputs a high level, the control circuit enters the first working state, and the first clock signal changes from the input high level in the sixth time period to the input low level, Therefore, the fifteenth electronic switch is turned off, the ninth electronic switch is turned on, the gate level of the tenth electronic switch is high level, and the tenth electronic switch is turned on.
  • the drain level of the tenth electronic switch is high level, and due to the coupling effect of the third capacitor, the voltage at the gate of the tenth electronic switch will further increase, and the tenth electronic switch is more fully turned on;
  • the first clock signal inputs a low level, the eleventh electronic switch is turned off, but the voltage at the gate of the twelfth electronic switch is in a floating state, assuming that the current voltage at the gate of the twelfth electronic switch is the third voltage , the gate level of the twelfth electronic switch is still high level, the twelfth electronic switch is turned on, the drain level of the twelfth electronic switch is high level, and thus the fifth level signal is high level ; Since the first clock signal is input at a low level, the thirteenth electronic switch, the fifteenth electronic switch and the sixteenth electronic switch are turned off, and because the sixteenth electronic switch is turned off, the output of the sixth level signal is stopped; The fifth level signal is
  • the eighth time period is the time period when the second clock signal outputs a low level, the control circuit is in the second working state, and the second working state of the control circuit is consistent with the first preparation state of the above-mentioned control circuit.
  • the difference is that since the first clock signal is input at a high level, the eleventh electronic switch is turned on, the voltage at the grid of the twelfth electronic switch is released from the floating state, and the voltage at the grid of the twelfth electronic switch is released. The voltage recovers from the fourth voltage to the third voltage.
  • the circuit state of the control circuit changes as the level of the first clock signal changes, specifically, when the first clock signal is at a low level , the working state of the control circuit is consistent with the first working state of the seventh time period, and when the first clock signal is at a high level, the working state of the control circuit is consistent with the second working state of the fourth time period, so that the control circuit outputs
  • the phase difference between the second clock signal and the first clock signal is 90 degrees.
  • the control circuit composed of the third switch unit and the fourth switch unit can be in In the first working state, the third switch unit is opened more fully to ensure the stability of the clock signal output obtained by phase shifting.
  • the control circuit of the display panel provided by the embodiment of the present application is used to receive the first clock signal, the first level signal and the second level signal, and according to the first level signal and the second level signal, control the Phase-shifting the first clock signal to obtain a second clock signal and outputting it to the gate drive circuit to implement phase-shifting of the clock signal to reduce the load of a single clock signal and reduce the number of clock generators in the display panel, The production cost of the display panel is reduced.
  • the embodiment of the present application further provides a display device 1 .
  • the display device 1 includes a display panel 2 and a control unit 3 , wherein the control unit 3 includes the above-mentioned control circuits.
  • the control unit includes a memory, a processor, and a computer program stored in the memory and operable on the processor.
  • the processor executes the computer program, the functions in the control circuit embodiments of the above-mentioned display panels are realized.
  • the processor can be a timing controller (Timer Control Register, TCON) or on-chip (System on Chip, SOC), or the central processing unit (Central Processing Unit, CPU), the processor can also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
  • the storage may be an internal storage unit of the terminal device in some embodiments, such as a hard disk or memory of the terminal device.
  • the memory may also be an external storage device of the terminal device, such as a plug-in hard disk equipped on the terminal device, a smart memory card (Smart Media Card, SMC), Secure Digital (Secure Digital, SD) card, Flash Card (Flash Card), etc.
  • the memory may also include both an internal storage unit of the terminal device and an external storage device.
  • the memory is used to store operating systems, application programs, boot loaders (BootLoader), data, and other programs, such as program codes of computer programs.
  • the memory can also be used to temporarily store data that has been output or will be output.

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Abstract

一种显示面板(2)的控制电路(10)和显示装置(1)，该显示面板(2)的控制电路(10)用于接收第一时钟信号、第一电平信号和第二电平信号，根据第一电平信号和第二电平信号，对第一时钟信号进行移相得到第二时钟信号并输出至栅极驱动电路(20)，实现对时钟信号的移相，以降低单个时钟信号的负载，并且可以减少显示面板(2)中时钟发生器的数量，降低显示面板(2)的生产成本。

Description

显示面板的控制电路和显示装置
本申请要求于2021年07月30日在中国专利局提交的、申请号为202110876023.9、发明名称为“显示面板的控制电路和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，具体涉及一种显示面板的控制电路和显示装置。
 背景技术
随着显示技术的快速发展，显示面板在娱乐、教育、安防等各种领域得到广泛应用。GDL(Gate Driver Less，阵列基板行驱动)技术是指将栅极驱动电路(Gate driver IC)直接制作在阵列(Array)基板上，通过输出行驱动信号实现对栅极进行逐行扫描。GDL技术能够简化显示面板的制备工序，省去水平扫描线方向的芯片邦定（Bonding）工序，并降低生产成本，同时可以提高显示面板的集成度，使显示面板更轻薄化。
采用GDL技术的显示面板需要使用多个时钟信号来控制栅极驱动电路输出行驱动信号，随着显示面板的尺寸和分辨率不断提高，每个显示面板的栅极驱动电路数量也不断提高，导致单个时钟信号的负载过高，使显示面板的运行稳定性下降。
 技术问题
本申请实施例的目的之一在于：提供一种显示面板的控制电路和显示装置，旨在解决现有的采用GDL技术的显示面板栅极驱动电路数量不断提高，导致单个时钟信号的负载过高，使显示面板的运行稳定性下降的问题。
 技术解决方案
本申请实施例采用的技术方案是：
第一方面，提供了一种显示面板的控制电路，所述控制电路用于接收第一时钟信号、第一电平信号和第二电平信号，根据所述第一电平信号和所述第二电平信号，对所述第一时钟信号进行移相得到第二时钟信号并输出至栅极驱动电路；其中，所述第二时钟信号包括第三电平信号和第四电平信号，所述第三电平信号和所述第四电平信号的电平高低不同；
所述控制电路包括第一开关单元和第二开关单元，所述第一开关单元与所述第二开关单元连接；
所述第一开关单元用于接收所述第一时钟信号、所述第一电平信号和所述第二电平信号，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，输出第三电平信号至所述栅极驱动电路；
所述第二开关单元用于接收所述第一时钟信号、所述第一电平信号和所述第二电平信号，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，输出第四电平信号至所述栅极驱动电路。
第二方面，提供了一种显示装置，包括显示面板；
以及控制单元，其中，所述控制单元包括上述第一方面所述的控制电路。
 有益效果
本申请实施例的第一方面提供一种显示面板的控制电路，用于接收第一时钟信号、第一电平信号和第二电平信号，根据所述第一电平信号和所述第二电平信号，对所述第一时钟信号进行移相得到第二时钟信号并输出至栅极驱动电路，实现对时钟信号的移相，以降低单个时钟信号的负载，并且可以减少显示面板中时钟发生器的数量，降低显示面板的生产成本。
可以理解的是，上述第二方面的有益效果可以参见上述第一方面中的相关描述，在此不再赘述。
 附图说明
图1是本申请实施例提供的显示面板的控制电路的第一种结构示意图；
图2是本申请实施例提供的显示面板的控制电路的第二种结构示意图；
图3是本申请实施例提供的显示面板的控制电路的第三种结构示意图；
图4是本申请实施例提供的显示面板的控制电路的第四种结构示意图；
图5是本申请实施例提供的显示面板的控制电路的第五种结构示意图；
图6是本申请实施例提供的第一时钟信号、第二电子开关的栅极电平、第二电子开关的漏极电平、第四电子开关的栅极电平、第三电平信号、第四电平信号和第二时钟信号的时序示意图；
图7是本申请实施例提供的显示面板的控制电路的第六种结构示意图；
图8是本申请实施例提供的显示面板的控制电路的第七种结构示意图；
图9是本申请实施例提供的显示面板的控制电路的第八种结构示意图；
图10是本申请实施例提供的第一时钟信号、第十电子开关的栅极电平、第十电子开关的漏极电平、第十二电子开关的栅极电平、第五电平信号、第六电平信号和第二时钟信号的时序示意图；
图11是本申请实施例提供的显示装置的结构示意图。
 本发明的实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本申请实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本申请。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
另外，在本申请说明书和所附权利要求书的描述中，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
在本申请说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
本申请实施例提供一种显示面板的控制电路，可以应用于显示面板，显示面板可以是基于TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器）技术的液晶显示面板、基于LCD（Liquid Crystal Display，液晶显示器）技术的液晶显示面板、基于OLED（Organic Light-Emitting Diode，有机发光二极管）技术的有机电激光显示面板、基于QLED（Quantum Dot Light Emitting Diodes，量子点发光二极管）技术的量子点发光二极管显示面板或曲面显示面板等。
如图1或图2所示，本申请实施例提供的显示面板的控制电路10，控制电路10用于接收第一时钟信号、第一电平信号和第二电平信号，根据第一电平信号和第二电平信号，对第一时钟信号进行移相得到第二时钟信号并输出至栅极驱动电路20；其中，第二时钟信号包括第三电平信号和第四电平信号，第三电平信号和第四电平信号的电平高低不同；
控制电路10包括第一开关单元11和第二开关单元12，第一开关单元11与第二开关单元12连接；
第一开关单元11用于接收第一时钟信号、第一电平信号和第二电平信号，根据第一时钟信号、第一电平信号和第二电平信号，输出第三电平信号至栅极驱动电路20；
第二开关单元12用于接收第一时钟信号、第一电平信号和第二电平信号，根据第一时钟信号、第一电平信号和第二电平信号，输出第四电平信号至栅极驱动电路20。
其中，图1仅示例性的示出了控制电路和栅极驱动电路的连接关系、控制电路的输入输出信号，以及栅极驱动电路的输入信号；图2在图1的基础上，示出了控制电路包括第一开关单元和第二开关单元，以及第一开关单元和第二开关单元的输入输出信号。
在应用中，控制电路可以包括多个晶体管、比较器、逻辑门、电阻、电容或电感等电子元器件；第一时钟信号、第一电平信号和第二电平信号可以是由时序控制器（Timer Control Register，TCON）或片上芯片（System on Chip，SOC）输入至控制电路的；控制电路可以根据第一电平信号和第二电平信号对第一时钟信号移相，移相得到的第二时钟信号和第一时钟信号的相位差的范围可以是0度至180度，第二时钟信号和第一时钟信号的相位差可以根据第一电平信号和第二电平信号的时序决定；第一时钟信号和第二时钟信号都可以用于输出至栅极驱动电路，以控制栅极驱动电路输出行驱动信号对显示面板的栅极进行逐行扫描；具体的，一个显示面板可以包括至少一个控制电路，控制电路的数量根据上述显示面板使用的时钟信号数量确定，每个控制电路和每个第一时钟信号一一对应，第n个控制电路接收第n个第一时钟信号，对第n个第一时钟信号进行移相得到第n个第一时钟信号对应的第n个第二时钟信号；每个控制电路移相得到的第二时钟信号输出至栅极驱动电路后，栅极驱动电路可以根据实际需要控制任意数量的行驱动信号输出以对显示面板的栅极进行逐行扫描，相比于使用n个第一时钟信号输入栅极驱动电路，通过控制电路生成与n个第一时钟信号一一对应的n个第二时钟信号后，可以使用n个第一时钟信号和n个第二时钟信号一共2n个时钟信号输入栅极驱动电路，由于单个时钟信号可以输入多个栅极驱动电路，当时钟信号的数量增加后，单个时钟信号可以减少输入栅极驱动电路的数量，从而可以降低单个时钟信号的负载，并可以减少用于生成时钟信号的时钟发生器的数量，降低显示面板的生产成本。其中，n为大于0的整数，控制电路的数量可以根据显示面板的实际需要进行设置。
图3示例性的示出了第一个控制电路101、第二个控制电路102至第n个控制电路103与栅极驱动电路20连接的结构示意图。
在应用中，控制电路可以包括多个开关单元，每个开关单元可以根据第一时钟信号的电平高低控制该开关单元是否输出电平信号，具体的，控制电路可以包括第一开关单元和第二开关单元，其中，第一开关单元用于根据第一时钟信号控制第三电平信号的输出，第二开关单元用于根据第一时钟信号控制第四电平信号的输出。例如，当第一时钟信号为高电平时，第一开关单元可以控制第三电平信号停止输出，第二开关单元可以控制第四电平信号开始输出；当第一时钟信号为低电平时，第一开关单元可以控制第三电平信号开始输出，第二开关单元可以控制第四电平信号停止输出。需要说明的是，在显示面板进入工作状态后，第三电平信号和第四电平信号的电平高低不同，具体的，当第三电平信号为高电平时，第四电平信号为低电平，或者，当第三电平信号为低电平时，第四电平信号为高电平，因此，通过整合第一开关单元输出的第三电平信号和第二开关单元输出的第四电平信号，可以得到连续不间断的第二时钟信号。
在一个实施例中，所述第一电平信号为高电平信号，所述第二电平信号为低电平信号。
在一个实施例中，第一开关单元11，还用于当所述第一时钟信号为低电平时，根据所述第一时钟信号、第一电平信号和第二电平信号，导通并输出第三电平信号至所述栅极驱动电路20，所述第三电平信号为高电平；还用于当所述第一时钟信号为高电平时，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，关断并停止输出所述第三电平信号至所述栅极驱动电路20；
第二开关单元12，还用于当所述第一时钟信号为高电平时，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，导通并输出第四电平信号至所述栅极驱动电路20，所述第四电平信号为低电平；还用于当所述第一时钟信号为低电平时，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，关断并停止输出所述第四电平信号至所述栅极驱动电路20。
在应用中，控制电路进入工作状态后，当第一时钟信号为低电平时，第一开关单元导通并输出第三电平信号至栅极驱动电路，此时第三电平信号为高电平，第二开关单元关断并停止输出第四电平信号至栅极驱动电路，此时第四电平信号不输出，因此，此时第二时钟信号为高电平；当第一时钟信号为高电平时，第一开关单元关断并停止输出所述第三电平信号至所述栅极驱动电路，此时第三电平信号不输出，第二开关单元导通并输出第四电平信号至所述栅极驱动电路，此时第四电平信号为低电平，因此，此时第二时钟信号为低电平，从而实现对第一时钟信号的移相，移相得到的第二时钟信号和第一时钟信号的相位差为90度。
如图4所示，在一个实施例中，基于图2所对应的实施例，所述第一开关单元11包括第一电子开关111、第二电子开关112、第三电子开关113、第四电子开关114、第五电子开关115和第一电容116；
所述第一电子开关111的漏极与所述第二电子开关112的栅极连接，所述第一电子开关111的栅极和源极用于接收所述第一时钟信号；
所述第二电子开关112的漏极与所述第四电子开关114的源极连接，所述第二电子开关112的源极用于接收所述第一电平信号；
所述第三电子开关113的漏极分别与所述第五电子开关115的源极和所述第四电子开关114的栅极连接，所述第三电子开关113的源极用于接收所述第一电平信号；
所述第一电容116的第一级分别与所述第一电子开关111的漏极和所述第二电子开关112的栅极连接，所述第五电子开关115的漏极用于接收所述第二电平信号；
所述第三电子开关113的栅极、所述第五电子开关115的漏极、所述第四电子开关114的漏极和所述第一电容116的第二极分别与所述第二开关单元电性连接。
在应用中，第一电子开关至第五电子开关可以是任意的具有电子开关功能的器件或电路，例如，三极管或金属氧化物半导体场效应晶体管（Metal Oxide Semiconductor Field Effect Transistor，MOSFET），具体的，可以是薄膜场效应晶体管（Thin Film Transistor，TFT）；第一电容可以是陶瓷电容器、铝电解电容器、云母电容器、纸介电容器、钽铌电解电容器或薄膜电容器等不同类型的电容，第一电容的类型和电容值大小可以根据实际需要进行选择。
如图5所示，在一个实施例中，基于图4所对应的实施例，第二开关单元12包括第六电子开关121、第七电子开关122、第八电子开关123；
所述第六电子开关121的漏极分别与所述第三电子开关的栅极和所述第七电子开关122的源极连接，所述第六电子开关121的栅极和源极用于接收所述第一电平信号；
所述第七电子开关122的漏极分别与所述第五电子开关的漏极和所述第八电子开关123的源极连接，所述第七电子开关122的栅极用于接收所述第一时钟信号，所述第七电子开关122的漏极用于接收所述第二电平信号；
所述第八电子开关123的漏极分别与第五电子开关的漏极和第一电容的第二级连接，所述第八电子开关123的栅极用于接收所述第一时钟信号。
在应用中，第六电子开关至第八电子开关的元器件类型和上述第一电子开关至第五电子开关的元器件类型一致，在此不再赘述。
图6示例性的示出了第一时钟信号、第二电子开关的栅极电平、第二电子开关的漏极电平、第四电子开关的栅极电平、第三电平信号、第四电平信号和第二时钟信号的时序图。
在应用中，第一电平信号始终输出高电平信号，第二电平信号始终输出低电平信号，第一时钟信号为周期性的时钟信号，第一时钟信号的相邻的上升沿和下降沿的相位差为90度；在控制电路进入工作状态前，需要经过准备状态；第一时间段内控制电路进入第一准备状态，第一时钟信号接收低电平，因此第一时间段期间第一电子开关关断，第一电子开关的漏极电平为低电平，使第二电子开关的栅极电平为低电平，第二电子开关关断，则第二电子开关的漏极电平为低电平，因此，第四电子开关的源极电平为低电平；第六电子开关的栅极和源极都接收第一电平信号，使第六电子开关导通且漏极电平为高电平，则第三电子开关的栅极电平为高电平，使第三电子开关导通，且第三电子开关的源极接收第一电平信号，因此第三电子开关的漏极电平为高电平，使第四电子开关的栅极电平为高电平，第四电子开关导通，由于第四电子开关的源极电平为低电平，因此第四电子开关的漏极电平为低电平，第四电子开关的漏极电平即为第三电平信号，从而第三电平信号为低电平；由于第一时钟信号输入低电平，第一时间段第五电子开关、第七电子开关和第八电子开关关断，第八电子开关不输出第四电平信号；由于第三电平信号为低电平，第四电平信号不输出，因此，第二时钟信号为低电平。需要说明的是，在第一准备状态下，第三电平信号和第四电平信号的电压大小不同，具体的，第三电平信号可以是低电平，低电平具体可以是-3V、-5V、-6V或-8V等，第四电平信号的电压可以是0V；本申请实施例对低电平和高电平的具体电压值不作任何限制。
在应用中，第二时间段内控制电路进入第二准备状态，第一时钟信号从第一时间段的低电平改为输入高电平，因此第二时间段内，第一电子开关导通且漏极电平为高电平，使第二电子开关的栅极电平为高电平，第二电子开关导通，且第二电子开关的源极接收第一电平信号，因此第二电子开关的漏极电平为高电平；由于第七电子开关的栅极接收高电平的第一时钟信号使其导通，第六电子开关漏极输出的高电平可以经由第七电子开关、第二电平信号释放，使第三电子开关的栅极电平由高电平降至低电平，第三电子开关关断，还由于第五电子开关的栅极接收高电平的第一时钟信号使其导通，第五电子开关源极处的高电平经由第五电子开关、第二电平信号释放，结合第三电子开关关断，使第五电子开关的源极电平由高电平降至低电平，则第四电子开关的栅极电平由高电平降至低电平，第四电子开关关断，停止输出第三电平信号；由于第八电子开关的栅极接收高电平的第一时钟信号使第八电子开关导通，由于第八电子开关的源极接收第二电平信号并为低电平，则第八电子开关的漏极电平为低电平，从而第四电平信号为低电平；由于第三电平信号停止输出，第四电平信号为低电平，因此第二时钟信号为低电平。
在应用中，第三时间段为第二时钟信号输出高电平的时间段，控制电路进入第一工作状态，第一时钟信号从第二时间段的输入高电平改为输入低电平，因此第三时间段内第一电子开关关断，但是由于第二电子开关栅极处的电压为浮空状态，假设当前第二电子开关栅极处的电压为第一电压，第二电子开关的栅极电平仍然为高电平，第二电子开关导通，第二电子开关的漏极电平和第二时间段的第二电子开关的漏极电平一致为高电平，第三电子开关的导通状态和上述第一时间段的第三电子开关的导通状态一致，在此不再赘述，由于第一时钟信号输入低电平，第五电子开关的栅极电平为低电平，第五电子开关关断，则第四电子开关的栅极电平为高电平，由于第四电子开关的源极电平为高电平，从而第三电平信号为高电平；由于第一时钟信号输入低电平，第七电子开关和第八电子开关的栅极电平为低电平，第七电子开关关断，第八电子开关关断并停止输出第四电平信号；由于第三电平信号为高电平，第四电平信号停止输出，因此，第二时钟信号为高电平；此外，由于第三电平信号为高电平，且由于第二电子开关栅极处的电压为浮空状态，第一电容的耦合作用使第二电子开关栅极处的第一电压升高至第二电压，第一电压的电压值由第一时钟信号输入高电平时的电压值确定，第二电压的电压值由第一时钟信号输出高电平时的电压值和第一电容的耦合作用确定。
在应用中，第四时间段为第二时钟信号输出低电平的时间段，控制电路进入第二工作状态，第一时钟信号从第三时间段的输入低电平改为输入高电平，因此第三时间段内第一电子开关导通，第二电子开关栅极处的电压的浮空状态解除，第二电子开关栅极处的电压由第二电压恢复到第一电压，第二电子开关导通，第四时间段内的第二电子开关的漏极电平和第三时间段内的第二电子开关的漏极电平一致并为高电平；由于第七电子开关的栅极接收高电平的第一时钟信号，使第七电子开关导通，第六电子开关漏极输出的高电平可以经由第七电子开关、第二电平信号释放，使第三电子开关的栅极电平由高电平降至低电平，第三电子开关关断，还由于第五电子开关的栅极接收高电平的第一时钟信号使其导通，第五电子开关源极处的高电平经由第五电子开关、第二电平信号释放，结合第三电子开关关断，使第五电子开关的源极电平由高电平降至低电平，则第四电子开关的栅极电平由高电平降至低电平，第四电子开关关断，停止输出第三电平信号；由于第八电子开关的栅极接收高电平的第一时钟信号使其导通，第八电子开关的源极接收第二电平信号并为低电平，则第八电子开关的漏极电平为低电平，从而第四电平信号为低电平；由于第三电平信号停止输出，第四电平信号为低电平，因此第二时钟信号为低电平。
在应用中，控制电路在第一时间段和第二时间段的准备结束后，控制电路的工作状态随着第一时钟信号的电平变化而变化，具体的，第一时钟信号为低电平时，控制电路的工作状态和上述第三时间段的第一工作状态一致，第一时钟信号为高电平时，控制电路的工作状态和上述第四时间的第二工作状态一致，从而使控制电路输出的第二时钟信号和第一时钟信号的相位差为90度，实现对时钟信号的移相，以降低单个时钟信号的负载，并且可以减少显示面板中时钟发生器的数量，降低显示面板的生产成本。
如图7所示，在一个实施例中，基于图1所对应的实施例，控制电路10包括：
第三开关单元13，用于接收第一时钟信号、第一电平信号和第二电平信号，当第一时钟信号为高电平时，根据第一时钟信号、第一电平信号和第二电平信号，导通并输出第五电平信号至栅极驱动电路20，第五电平信号为高电平；还用于当第一时钟信号为低电平时，根据第一时钟信号、第一电平信号和第二电平信号，导通并输出第五电平信号至栅极驱动电路20，第五电平信号为低电平；
第四开关单元14，与第三开关单元13连接，用于接收第一时钟信号、第一电平信号和第二电平信号，当第一时钟信号为高电平时，根据第一时钟信号、第一电平信号和第二电平信号，导通并输出第六电平信号至栅极驱动电路20，第六电平信号为低电平；还用于当第一时钟信号为低电平时，根据第一时钟信号、第一电平信号和第二电平信号，关断并停止输出第六电平信号。
其中，第二时钟信号包括第五电平信号和第六电平信号。
在应用中，控制电路进入工作状态后，当第一时钟信号为低电平时，第三开关单元导通并输出第五电平信号至栅极驱动电路，此时第五电平信号为高电平，第四开关单元关断并停止输出第六电平信号至栅极驱动电路，此时第六电平信号不输出，因此，此时第二时钟信号为高电平；当第一时钟信号为高电平时，第三开关单元导通并输出所述第五电平信号至所述栅极驱动电路，此时第五电平信号为低电平，第四开关单元导通并输出第六电平信号至所述栅极驱动电路，此时第六电平信号为低电平，因此，此时第二时钟信号为低电平，从而实现对第一时钟信号的移相，移相得到的第二时钟信号和第一时钟信号的相位差为90度。
如图8所示，在一个实施例中，基于图7所对应的实施例，第三开关单元13包括第九电子开关131、第十电子开关132、第十一电子开关133、第十二电子开关134、第十三电子开关135、第二电容136和第三电容137；
第九电子开关131的漏极分别与第十电子开关132的栅极、第十三电子开关135的源极和第二电容136的第一极连接，第九电子开关131的源极用于接收第一电平信号；
第十电子开关132的漏极与第二电容136的第二极和第十二电子开关134的源极连接，第十电子开关132的源极用于接收第一电平信号；
第十一电子开关133的栅极和源极用于接收第一时钟信号；
第十二电子开关134的栅极分别与第三电容137的第一极和第十一电子开关133的漏极连接；
第十三电子开关135的栅极用于接收第一时钟信号；
第九电子开关131的栅极、第十二电子开关134的漏极、第十三电子开关135的漏极和第三电容137的第二极分别与第四开关单元电性连接。
在应用中，第九电子开关至第十三电子开关的元器件类型和上述第一电子开关至第五电子开关的元器件类型一致，以及，第二电容和第三电容的类型和上述第一电容的类型一致，在此不再赘述，第二电容和第三电容的电容值大小可以根据实际需要进行设置。
如图9所示，在一个实施例中，基于图8所对应的实施例，第四开关单元14包括第十四电子开关141、第十五电子开关142和第十六电子开关143；
第十四电子开关141的漏极与第九电子开关的栅极和第十五电子开关142的源极连接，第十四电子开关141的栅极和源极用于接收第一电平信号；
第十五电子开关142的漏极分别与第十三电子开关的漏极和第十六电子开关143的源极连接，第十五电子开关142的栅极用于接收第一时钟信号，第十五电子开关142的漏极用于接收第二电平信号；
第十六电子开关143的漏极分别与第十二电子开关的漏极和第三电容的第二极连接，第十六电子开关143的栅极用于接收第一时钟信号。
在应用中，第十四电子开关至第十六电子开关的元器件类型和上述第一电子开关至第五电子开关的元器件类型一致，在此不再赘述。
图10示例性的示出了第一时钟信号、第十电子开关的栅极电平、第十电子开关的漏极电平、第十二电子开关的栅极电平、第五电平信号、第六电平信号和第二时钟信号的时序图。
在应用中，第一电平信号始终输出高电平信号，第二电平信号始终输出低电平信号，第一时钟信号为周期性的时钟信号，第一时钟信号的相邻的上升沿和下降沿的相位差为90度；由于第十四电子开关的栅极和源极始终接收第一电平信号，因此第十四电子开关的漏极电平始终为高电平；在控制电路进入工作状态前，需要经过准备状态；第五时间段内控制电路进入第一准备状态，第一时钟信号输入低电平，第十一电子开关、第十三电子开关、第十五电子开关和第十六电子开关关断；第十四电子开关的漏极的高电平输出至第九电子开关的栅极，使第九电子开关导通，且第九电子开关的源极接收第一电平信号，因此第九电子开关的漏极电平为高电平，使第十电子开关的栅极电平为高电平，第十电子开关导通，第十电子开关的漏极电平为高电平；由于第十一电子开关关断，则第十二电子开关的栅极电平为低电平，第十二电子开关关断，第十二电子开关的漏极电平即为第五电平信号，从而第十二电子开关不输出第五电平信号；由于第十六电子开关关断，且第十六电子漏极电平即为第六电平信号，从而第十六电子开关不输出第六电平信号；由于第五电平信号和第六电平信号都不输出，因此，第二时钟信号为低电平。
在应用中，第六时间段内控制电路进入第二准备状态，第一时钟信号从第五时间段的输入低电平改为输入高电平，由于第十五电子开关的栅极接收高电平的第一时钟信号，第十五电子开关导通，第十四电子开关漏极输出的高电平可以经由第十五电子开关、第二电平信号释放，使第九电子开关的栅极电平由高电平降至低电平，第九电子开关关断，还由于第十三电子开关的栅极接收高电平的第一时钟信号，第十三电子开关导通，第十三电子开关源极处的高电平经由第十三电子开关、第二电平信号释放，结合第九电子开关关断，使第十电子开关的栅极电平由高电平降至低电平，第十电子开关关断，并且第十电子开关漏极处的电压会由于第二电容的耦合作用降低，因此，第十电子开关的漏极电平为低电平；由于第一时钟信号为高电平，第十一电子开关导通，第十二电子开关的栅极电平为高电平，第十二电子开关导通，第十二电子开关的漏极电平为低电平，从而第五电平信号为低电平；由于第一时钟信号为高电平，第十六电子开关导通，第十六电子开关的源极接收第二电平信号，因此，第十六电子开关的漏极电平为低电平，从而第六电平信号为低电平；由于第五电平信号和第六电平信号都为低电平，因此第二时钟信号为低电平。
在应用中，第七时间段为第二时钟信号输出高电平的时间段，控制电路进入第一工作状态，第一时钟信号从第六时间段的输入高电平改为输入低电平，因此第十五电子开关关断，第九电子开关导通，当前第十电子开关的栅极电平为高电平，第十电子开关导通，由于第十电子开关的源极接收第一电平信号，则第十电子开关的漏极电平为高电平，由于第三电容的耦合作用，第十电子开关栅极处的电压会进一步升高，第十电子开关导通更充分；由于第一时钟信号输入低电平，第十一电子开关关断，但是第十二电子开关的栅极处的电压为浮空状态，假设当前第十二电子开关栅极处的电压为第三电压，第十二电子开关的栅极电平仍然为高电平，第十二电子开关导通，第十二电子开关的漏极电平为高电平，从而第五电平信号为高电平；由于第一时钟信号输入低电平，第十三电子开关、第十五电子开关和第十六电子开关关断，由于第十六电子开关关断，从而停止输出第六电平信号；由于第五电平信号为高电平，第六电平信号停止输出，第二时钟信号为高电平；此外，由于第五电平信号为高电平，且由于第十二电子开关栅极处的电压为浮空状态，当前第十二电子开关栅极处的电压为第三电压，第三电容的耦合作用使第十二电子开关栅极处的电压升高至第四电压，第十二电子开关导通更充分，第三电压的电压值由第一时钟信号输出高电平时的电压值确定，第四电压的电压值由第一时钟信号输出高电平时的电压值、第一电平信号的电压值和第三电容的耦合作用确定。
在应用中，第八时间段为第二时钟信号输出低电平的时间段，控制电路处于第二工作状态，控制电路的第二工作状态和上述控制电路的第一准备状态一致，在此不再赘述，区别在于，由于第一时钟信号输入高电平，第十一电子开关导通，第十二电子开关的栅极处的电压为浮空状态解除，第十二电子开关栅极处的电压由第四电压恢复至第三电压。
在应用中，控制电路在第五时间段和第六时间段的准备结束后，控制电路的电路状态随着第一时钟信号的电平变化而变化，具体的，第一时钟信号为低电平时，控制电路的工作状态和上述第七时间段的第一工作状态一致，第一时钟信号为高电平时，控制电路的工作状态和上述第四时间的第二工作状态一致，从而使控制电路输出的第二时钟信号和第一时钟信号的相位差为90度，相对于由第一开关单元和第二开关单元组成的控制电路，由第三开关单元和第四开关单元组成的控制电路可以在第一工作状态内使第三开关单元打开更充分，保证移相得到的时钟信号输出的稳定性。
本申请实施例提供的显示面板的控制电路，用于接收第一时钟信号、第一电平信号和第二电平信号，根据所述第一电平信号和所述第二电平信号，对所述第一时钟信号进行移相得到第二时钟信号并输出至栅极驱动电路，实现对时钟信号的移相，以降低单个时钟信号的负载，并且可以减少显示面板中时钟发生器的数量，降低显示面板的生产成本。
如图11所示，本申请实施例还提供一种显示装置1，显示装置1包括显示面板2以及控制单元3，其中，控制单元3包括上述各个控制电路。
控制单元包括存储器、处理器以及存储在存储器中并可在处理器上运行的计算机程序，处理器执行计算机程序时实现上述各个显示面板的控制电路实施例中的功能。
在应用中，处理器可以是时序控制器（Timer Control Register，TCON）或片上芯片（System on Chip，SOC），也可以是中央处理单元（Central Processing Unit，CPU），该处理器还可以是其他通用处理器、数字信号处理器（Digital Signal Processor，DSP）、专用集成电路（Application Specific Integrated Circuit，ASIC）、现成可编程门阵列（Field-Programmable Gate Array，FPGA）或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
在应用中，存储器在一些实施例中可以是终端设备的内部存储单元，例如终端设备的硬盘或内存。存储器在另一些实施例中也可以是终端设备的外部存储设备，例如终端设备上配备的插接式硬盘，智能存储卡（Smart Media Card，SMC），安全数字（Secure Digital，SD）卡，闪存卡（Flash Card）等。进一步地，存储器还可以既包括终端设备的内部存储单元也包括外部存储设备。存储器用于存储操作系统、应用程序、引导装载程序（BootLoader）、数据以及其他程序等，例如计算机程序的程序代码等。存储器还可以用于暂时地存储已经输出或者将要输出的数据。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (15)

  1. 一种显示面板的控制电路，其中，所述控制电路用于接收第一时钟信号、第一电平信号和第二电平信号，根据所述第一电平信号和所述第二电平信号，对所述第一时钟信号进行移相得到第二时钟信号并输出至栅极驱动电路；其中，所述第二时钟信号包括第三电平信号和第四电平信号，所述第三电平信号和所述第四电平信号的电平高低不同；
    所述控制电路包括第一开关单元和第二开关单元，所述第一开关单元与所述第二开关单元连接；
    所述第一开关单元用于接收所述第一时钟信号、所述第一电平信号和所述第二电平信号，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，输出第三电平信号至所述栅极驱动电路；
    所述第二开关单元用于接收所述第一时钟信号、所述第一电平信号和所述第二电平信号，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，输出第四电平信号至所述栅极驱动电路。
  2. 如权利要求1所述的显示面板的控制电路，其中，所述第一开关单元，还用于当所述第一时钟信号为低电平时，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，导通并输出第三电平信号至所述栅极驱动电路，所述第三电平信号为高电平。
  3. 如权利要求1所述的显示面板的控制电路，其中，所述第一开关单元，还用于当所述第一时钟信号为高电平时，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，关断并停止输出所述第三电平信号至所述栅极驱动电路。
  4. 如权利要求1所述的显示面板的控制电路，其中，所述第二开关单元，还用于当所述第一时钟信号为高电平时，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，导通并输出第四电平信号至所述栅极驱动电路，所述第四电平信号为低电平。
  5. 如权利要求1所述的显示面板的控制电路，其中，所述第二开关单元，还用于当所述第一时钟信号为低电平时，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，关断并停止输出所述第四电平信号至所述栅极驱动电路。
  6. 如权利要求1所述的显示面板的控制电路，其中，所述第一开关单元包括第一电子开关、第二电子开关、第三电子开关、第四电子开关、第五电子开关和第一电容；
    所述第一电子开关的漏极与所述第二电子开关的栅极连接，所述第一电子开关的栅极和源极用于接收所述第一时钟信号；
    所述第二电子开关的漏极与所述第四电子开关的源极连接，所述第二电子开关的源极用于接收所述第一电平信号；
    所述第三电子开关的漏极分别与所述第五电子开关的源极和所述第四电子开关的栅极连接，所述第三电子开关的源极用于接收所述第一电平信号；
    所述第一电容的第一级分别与所述第一电子开关的漏极和所述第二电子开关的栅极连接，所述第五电子开关的漏极用于接收所述第二电平信号；
    所述第三电子开关的栅极、所述第五电子开关的漏极、所述第四电子开关的漏极和所述第一电容的第二极分别与所述第二开关单元电性连接。
  7. 如权利要求1所述的显示面板的控制电路，其中，所述第二开关单元包括第六电子开关、第七电子开关、第八电子开关；
    所述第六电子开关的漏极分别与第三电子开关的栅极和所述第七电子开关的源极连接，所述第六电子开关的栅极和源极用于接收所述第一电平信号；
    所述第七电子开关的漏极分别与第五电子开关的漏极和所述第八电子开关的源极连接，所述第七电子开关的栅极用于接收所述第一时钟信号，所述第七电子开关的漏极用于接收所述第二电平信号；
    所述第八电子开关的漏极分别与所述第五电子开关的漏极和第一电容的第二级连接，所述第八电子开关的栅极用于接收所述第一时钟信号。
  8. 如权利要求1所述的显示面板的控制电路，其中，所述控制电路包括：
    第三开关单元，用于接收所述第一时钟信号、所述第一电平信号和所述第二电平信号，当所述第一时钟信号为高电平时，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，导通并输出第五电平信号至所述栅极驱动电路，所述第五电平信号为高电平；还用于当所述第一时钟信号为低电平时，根据所述第一时钟信号、第一电平信号和第二电平信号，导通并输出第五电平信号至所述栅极驱动电路，所述第五电平信号为低电平。
  9. 如权利要求1所述的显示面板的控制电路，其中，所述控制电路包括：第四开关单元，与第三开关单元连接，用于接收所述第一时钟信号、所述第一电平信号和所述第二电平信号，当所述第一时钟信号为高电平时，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，导通并输出第六电平信号至所述栅极驱动电路，所述第六电平信号为低电平；还用于当所述第一时钟信号为低电平时，根据所述第一时钟信号、所述第一电平信号和所述第二电平信号，关断并停止输出所述第六电平信号；
    其中，所述第二时钟信号包括第五电平信号和所述第六电平信号。
  10. 如权利要求8所述的显示面板的控制电路，其中，所述第三开关单元包括第九电子开关、第十电子开关、第十一电子开关、第十二电子开关、第十三电子开关、第二电容和第三电容；
    所述第九电子开关的漏极分别与所述第十电子开关的栅极、所述第十三电子开关的源极和所述第二电容的第一极连接，所述第九电子开关的源极用于接收所述第一电平信号；
    所述第十电子开关的漏极与所述第二电容的第二极和所述第十二电子开关的源极连接，所述第十电子开关的源极用于接收所述第一电平信号；
    所述第十一电子开关的栅极和源极用于接收所述第一时钟信号；
    所述第十二电子开关的栅极分别与所述第三电容的第一极和所述第十一电子开关的漏极连接；
    所述第十三电子开关的栅极用于接收所述第一时钟信号；
    所述第九电子开关的栅极、所述第十二电子开关的漏极、所述第十三电子开关的漏极和所述第三电容的第二极分别与第四开关单元电性连接。
  11. 如权利要求9所述的显示面板的控制电路，其中，第四开关单元包括第十四电子开关、第十五电子开关和第十六电子开关；
    所述第十四电子开关的漏极与第九电子开关的栅极和所述第十五电子开关的源极连接，所述第十四电子开关的栅极和源极用于接收所述第一电平信号；
    所述第十五电子开关的漏极分别与第十三电子开关的漏极和第十六电子开关的源极连接，所述第十五电子开关的栅极用于接收所述第一时钟信号，所述第十五电子开关的漏极用于接收所述第二电平信号；
    所述第十六电子开关的漏极分别与第十二电子开关的漏极和第三电容的第二极连接，所述第十六电子开关的栅极用于接收所述第一时钟信号。
  12. 如权利要求1所述的显示面板的控制电路，其中，所述第一电平信号为高电平信号，所述第二电平信号为低电平信号。
  13. 如权利要求1所述的显示面板的控制电路，其中，所述第二时钟信号和所述第一时钟信号的相位差的范围为0度至180度。
  14. 如权利要求1所述的显示面板的控制电路，其中，所述控制电路用于，根据所述第一电平信号和第二电平信号的时序确定所述第二时钟信号和所述第一时钟信号的相位差。
  15. 一种显示装置，其中，包括：
    显示面板；
    以及控制单元，其中，所述控制单元包括如权利要求1所述的控制电路。
PCT/CN2022/097860 2021-07-30 2022-06-09 显示面板的控制电路和显示装置 WO2023005443A1 (zh)

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