WO2022249855A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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WO2022249855A1
WO2022249855A1 PCT/JP2022/019342 JP2022019342W WO2022249855A1 WO 2022249855 A1 WO2022249855 A1 WO 2022249855A1 JP 2022019342 W JP2022019342 W JP 2022019342W WO 2022249855 A1 WO2022249855 A1 WO 2022249855A1
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Prior art keywords
region
type
semiconductor layer
insulating film
semiconductor device
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English (en)
French (fr)
Japanese (ja)
Inventor
光央 岡本
惇 八尾
弘 佐藤
信介 原田
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National Institute of Advanced Industrial Science and Technology AIST
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National Institute of Advanced Industrial Science and Technology AIST
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Priority to JP2023523382A priority Critical patent/JP7563802B2/ja
Priority to CN202280037917.1A priority patent/CN117413366A/zh
Priority to DE112022002803.3T priority patent/DE112022002803T5/de
Priority to US18/563,937 priority patent/US20240266351A1/en
Publication of WO2022249855A1 publication Critical patent/WO2022249855A1/ja
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Definitions

  • the present invention relates to a semiconductor device and its manufacturing method, and for example, to a technology effectively applied to a semiconductor device using a SiC substrate and its manufacturing method.
  • SiC silicon carbide
  • Fig. of Patent Document 1. 6 and Fig. 7 discloses a semiconductor device in which a vertical power MOSFET having a planar gate structure and a CMOS gate driver for driving the vertical power MOSFET are mounted on a SiC substrate.
  • a CMOS gate driver has a configuration in which an n-type MOSFET and a p-type MOSFET are connected in series.
  • FIG. 1 of Patent Document 2 discloses a trench MOSFET having an n layer 15b, an n ⁇ layer 15a, and a p-type channel region 16 formed using epitaxial growth and ion implantation. By setting the impurity concentration ratio of 15a within a desired range, the short channel effect is suppressed.
  • Patent Document 3 describes a semiconductor device in which a CMOS gate driver and a vertical p-type power MOS with a trench gate structure are monolithically integrated, mainly in a silicon-based semiconductor.
  • Non-Patent Document 1 discloses a p-type MOSFET structure of SiC, and describes that threshold voltage and mobility can be adjusted by a buried channel structure (EBC: Epitaxial Burried Channel) provided in a p-type epitaxial growth layer.
  • EBC Epitaxial Burried Channel
  • Patent document 1 discloses integration of a CMOS gate driver and a power transistor for the same purpose, but sufficient consideration is not given to structural matching between the power transistor and the gate driver, and there is a problem in cost reduction. rice field.
  • a semiconductor device includes a stacked semiconductor substrate in which an n-type drift layer, a p-type buried base layer and a p-type base layer are stacked on an n-type semiconductor substrate, and a power transistor, an n-type transistor and a p-type transistor are provided on the stacked semiconductor substrate.
  • a semiconductor device having transistors wherein a power transistor has a trench gate electrode penetrating a base layer, a p-type transistor is formed in an n-type well region formed in the base layer, and an n-type transistor is: Formed in a p-type well region further formed in the base layer or in the n-type well region, the p-type impurity concentration of the buried channel region of the p-type transistor is equal to the p-type impurity concentration of the base layer.
  • a method of manufacturing a semiconductor device includes a step of preparing a semiconductor substrate having a first main surface including a power transistor region and a CMOS region and a second main surface facing the first main surface; forming an n-type drift layer on the first main surface of the by epitaxial growth; selectively forming a p-type buried base layer on the drift layer by ion implantation; forming a p-type base layer by epitaxial growth in the CMOS region; forming an n-type well region by ion implantation in the CMOS region; forming a trench; forming a power transistor in a power transistor region by providing a power source region in a base layer; providing a trench gate insulating film and a trench gate electrode in a trench; , a first source region, a buried channel region and a first drain region, and a first gate insulating film and a first gate electrode are provided on the buried channel region to form a p-type MOSFET, and in the
  • FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment
  • FIG. 1 is a plan view of a semiconductor device according to an embodiment
  • FIG. 2 is an equivalent circuit diagram of the semiconductor device of this embodiment
  • FIG. FIG. 4 is a diagram showing the relationship between gate voltage and drain current of an n-type transistor and a p-type transistor according to the present embodiment
  • It is a figure which shows the relationship of the input voltage of a CMOS inverter of this Embodiment, and an output voltage.
  • It is a sectional view showing a manufacturing process of a semiconductor device of this embodiment
  • 7 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 6;
  • FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment
  • FIG. 1 is a plan view of a semiconductor device according to an embodiment
  • FIG. 2 is an equivalent circuit diagram of the semiconductor device of this embodiment
  • FIG. FIG. 4 is a diagram showing the relationship between gate voltage
  • FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 7;
  • FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 8;
  • FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 9;
  • 11 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 10;
  • FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 10;
  • FIG. FIG. 12 is a cross-sectional view showing a manufacturing process of a semiconductor device that is a modification of FIG. 11;
  • 10 is a cross-sectional view of a semiconductor device of Modification 1;
  • FIG. 4 is an equivalent circuit diagram showing an example of countermeasures against false ignition
  • FIG. 11 is a cross-sectional view of a semiconductor device of Modification 2
  • FIG. 11 is a plan view of a semiconductor device of Modification 3
  • FIG. 12 is a plan view for explaining the effect of the semiconductor device of Modification 3
  • FIG. 11 is a plan view of a semiconductor device of Modification 4;
  • FIG. 1 is a sectional view of the semiconductor device of this embodiment
  • FIG. 2 is a plan view of the semiconductor device of this embodiment
  • FIG. 3 is an equivalent circuit diagram of the semiconductor device of this embodiment.
  • FIG. 4 is a diagram showing the relationship between the gate voltage and the drain current of the n-type transistor and the p-type transistor of this embodiment
  • FIG. 5 is a diagram showing the relationship between the input voltage and the output voltage of the CMOS inverter of this embodiment.
  • FIG. 1 is a cross-sectional view taken along lines AA', BB' and CC' of FIG. 2, and continuously shows the cross-sectional structure of the unit transistor in each region.
  • the semiconductor device 100 includes a power transistor (power MOSFET) UMOS, and a p-type transistor (p-type MOSFET) PMOS and an n-type transistor (n-type MOSFET) NMOS that constitute a gate drive circuit for the power transistor UMOS.
  • the gate drive circuit is a CMOS inverter, the p-type transistor PMOS and the n-type transistor NMOS are connected in series, the source of the p-type transistor PMOS is connected to the CMOS power supply potential VDD, and the source of the n-type transistor NMOS is connected to the CMOS reference potential VSS.
  • the power transistor UMOS has its source connected to the power source Vs and its drain connected to the power drain Vd.
  • the gate of the p-type transistor PMOS and the gate of the n-type transistor NMOS are connected to the input signal Vin, and the drain of the p-type transistor PMOS and the drain of the n-type transistor NMOS are connected to the gate of the power transistor UMOS.
  • the output Vout of the driving circuit having the CMOS inverter configuration is input to the gate of the power transistor UMOS as the input signal Vg of the power transistor UMOS.
  • the semiconductor device 100 includes an input signal terminal TVin, a CMOS reference potential terminal TVSS, a CMOS power potential terminal TVDD, power source terminals TVs, a CMOS area ARC and a power transistor area ARU.
  • the CMOS region ARC is arranged in the central portion, and on one side (left side) of the CMOS region ARC, there are an input signal terminal TVin, a CMOS reference potential terminal TVSS, a CMOS power supply potential terminal TVDD, and a CMOS region ARC.
  • a power transistor area ARU is arranged on the other side (right side) of the .
  • the power source TVs is located within the power transistor area ARU and above the power transistor UMOS shown in FIG.
  • the CMOS area (drive circuit area) ARC includes multiple PMOS areas ARP and multiple NMOS areas ARN.
  • a large number of p-type transistors PMOS are arranged in the X direction in the PMOS region ARP. That is, a large number of gate electrodes EGP extending, for example, 100 ⁇ m in the Y direction orthogonal to the X direction are arranged in the X direction, and the drain region RDP and the source region RSP shown in FIG. 1 are arranged so as to sandwich each gate electrode EGP. are placed.
  • the X direction is the gate length direction of the p-type transistor PMOS
  • the Y direction is the gate width direction
  • many p-type transistor PMOS are connected in parallel, they can be regarded as one p-type transistor PMOS.
  • redundant description is omitted, a large number of n-type transistors NMOS arranged in the NMOS region ARN have the same configuration as the p-type transistor PMOS described above.
  • the plurality of PMOS regions ARP and the plurality of NMOS regions ARN are alternately arranged in the Y direction.
  • the plurality of p-type transistors PMOS formed in the CMOS region ARC constitute one p-type transistor PMOS with a high amplification gain as a whole. is doing.
  • a plurality of n-type transistors NMOS formed in the CMOS region ARC also constitute one n-type transistor NMOS having a high amplification gain.
  • the PMOS regions ARP and NMOS regions ARN are alternately arranged in multiple stages in the Y direction, the present invention is not limited to this, and a plurality of PMOS regions ARP and a plurality of NMOS regions ARN may be collectively arranged. Further, the amplification gain ratio may be adjusted by adjusting the stage number ratio between the PMOS region ARP and the NMOS region ARN.
  • a large number of power transistors UMOS are arranged in the power transistor region ARU, and as shown in FIG. A region RSU is provided.
  • a large number of trench grooves TG (in other words, gate electrodes EGU) extend in the X direction, and source regions RSU are arranged on both sides of each trench groove TG in the Y direction. there is That is, the source region RSU also extends in the X direction along the trench groove TG.
  • a large number of source regions RSU extending in the X direction are connected to each other by metal wiring (source electrodes ESU in FIG. 1), and a large number of gate electrodes EGU extending in the X direction are also different from the source electrodes ESU. Connected with metal wiring.
  • the extending direction of the trench groove TG is the X direction (in other words, the direction orthogonal to the extending direction of the gate electrode EGN of the n-type transistor NMOS and the gate electrode EGP of the p-type transistor PMOS), it is not limited to this. Instead, it may be the Y direction (in other words, the direction parallel to the extending direction of the gate electrode EGN of the n-type transistor NMOS and the gate electrode EGP of the p-type transistor PMOS).
  • a semiconductor device 100 includes a power transistor area ARU and a CMOS area (drive circuit area) ARC.
  • a transistor PMOS is formed.
  • the power transistor UMOS is a trench gated power MOSFET with gate, source and drain
  • the n-type transistor NMOS is a surface channel MOSFET with gate, source and drain
  • the p-type transistor PMOS is a buried with gate, source and drain. It is a channel type MOSFET.
  • a power transistor UMOS, an n-type transistor NMOS and a p-type transistor PMOS are formed on the laminated semiconductor substrate SB.
  • the laminated semiconductor substrate SB includes a semiconductor substrate SUB having a first main surface (main surface) SUBa and a second main surface (back surface) SUBb facing each other, and a drift layer (n type semiconductor layer) DL, a buried base layer (p-type semiconductor layer) BBL formed on the drift layer DL, and a base layer (p-type semiconductor layer) BL formed on the buried base layer BBL.
  • the laminated semiconductor substrate SB has a first main surface (main surface) SBa and a second main surface (back surface) SBb facing each other.
  • the second main surface (back surface) SBb coincides with the second main surface SUBb of the semiconductor substrate SB.
  • a power transistor area ARU and a CMOS area ARC are provided on the first main surface SBa (or first main surface SUBa) of the laminated semiconductor substrate SB (or semiconductor substrate SUB).
  • the semiconductor substrate SUB is an n-type silicon carbide substrate and its polytype is 4H. That is, the semiconductor substrate SUB is n-type 4H-SiC.
  • the first main surface SUBa of the semiconductor substrate SUB is, for example, a surface provided with an off angle of 4° from the (0001) plane in the ⁇ 11-20> direction, which is the off direction of the crystal. It is called the (0001) plane.
  • the drift layer DL is an n-type semiconductor layer having an n-type impurity concentration of about 1e16 cm ⁇ 3 , and has a thickness of about 9.5 ⁇ m formed on the first main surface SUBa of the semiconductor substrate SUB by epitaxial growth. epitaxial layer.
  • the embedded base layer BBL is a p-type semiconductor layer having a p-type impurity concentration of about 1e18 cm ⁇ 3 formed on the drift layer DL by epitaxial growth and ion implantation.
  • the film thickness of the embedded base layer BBL is about 1 ⁇ m.
  • the embedded base layer BBL has a laminated structure of an embedded base layer BBL1 and an embedded base layer BBL2, and the film thickness of each of the embedded base layers BBL1 and BBL2 is approximately 0.5 ⁇ m.
  • the base layer BL is a p-type semiconductor layer having a p-type impurity concentration of about 1.3e17 cm ⁇ 3 and is an epitaxial layer having a thickness of about 1.8 ⁇ m formed on the buried base layer BBL by epitaxial growth. is.
  • the film thickness of the base layer BL is thicker than the film thickness of the embedded base layer BBL.
  • the p-type impurity concentration of the base layer BL is lower than that of the embedded base layer BBL.
  • a channel forming region of the power transistor UMOS is formed in the power transistor region ARU, and an n-type transistor NMOS and a p-type transistor PMOS are formed in the CMOS region ARC.
  • the base layer BL as an epitaxial layer formed by an epitaxial growth method, a relatively thick base layer BL can be formed without using a special ion implantation apparatus capable of outputting MeV-class ion implantation energy. This improves the degree of freedom in designing the breakdown voltage in the CMOS region ARC.
  • the semiconductor substrate SUB, the drift layer DL and the base layer BL are provided over the entire power transistor area ARU and the CMOS area ARC.
  • the embedded base layer BBL is provided throughout the CMOS region ARC and selectively provided in the power transistor region ARU.
  • a trench protection region (p-type semiconductor region) TPR is provided at the bottom of the trench groove TG, and JFET layer 1 (n-type semiconductor layer) DLS1 and JFET layer 2 (n-type semiconductor layer) DLS2 is provided.
  • the buried base layer BBL is arranged in a region other than the region where the trench protection region TPR, JFET layer 1DLS1 and JFET layer 2DLS2 are provided.
  • a drain electrode ED is formed over the entire power transistor region ARU and the CMOS region ARC on the second main surface SUBb of the semiconductor substrate SUB.
  • a trench groove TG is formed penetrating the source region RSU and the base layer BL from the first main surface SBa of the laminated semiconductor substrate SB.
  • a film) GIU and a gate electrode (trench gate electrode) EGU are formed.
  • the gate insulating film GIU is a silicon oxide film deposited using the CVD method and has a film thickness of 50 to 150 nm.
  • Gate electrode EGU is formed of a polycrystalline silicon film containing an n-type impurity.
  • a source region (n-type semiconductor region) RSU and a p-type region (p-type semiconductor region) RPU are formed in the base layer BL on the first main surface SBa side of the laminated semiconductor substrate SB.
  • the source regions RSU are arranged on both sides of the trench groove TG so as to sandwich the trench groove TG.
  • the p-type region (p-type semiconductor region) RPU is arranged on the side opposite to the trench groove TG or the gate electrode EGU with respect to the source region RSU. In other words, it can be said that the p-type region RPU is arranged between the source regions RSU of adjacent unit transistors.
  • the source region RSU and p-type region RPU are connected to the source electrode ESU.
  • the p-type impurity concentration of the trench protection region (p-type semiconductor region) TPR provided at the bottom of the trench groove TG is equal to the p-type impurity concentration of the embedded base layer BBL (particularly, the embedded base region BBL1), and is equal to the p-type impurity concentration of the base layer BL. Higher than the p-type impurity concentration.
  • the trench protection region (p-type semiconductor region) TPR is an electric field relaxation layer. cuts into the trench protection region TPR. That is, it is essential that the depth of the trench groove TG is larger than the total film thickness of the base layer BL and the buried base layer BBL2 and smaller than the total film thickness of the base layer BL and the buried base layer BBL.
  • the trench protection region TPR is sandwiched between JFET layers 1 (n-type semiconductor layers) DLS1, and the trench grooves TG are sandwiched between JFET layers 2 (n-type semiconductor layers) DLS2. . Since the gate insulating film GIU is covered with the trench protection region TPR at the bottom of the trench TG, dielectric breakdown of the gate insulating film GIU can be prevented. Further, by optimizing the n-type impurity concentrations of the JFET layers 1DLS1 and 2DLS2, dielectric breakdown of the gate insulating film GIU can be prevented without increasing the JFET resistance.
  • the buried base layer BBL having a higher p-type impurity concentration than the p-type impurity concentration of the base layer BL between the drift layer DL and the base layer BL, Withstand pressure can be improved. Furthermore, by forming the base layer BL, in which the channel of the power transistor UMOS is formed, from an epitaxial layer with a low impurity concentration, high channel mobility can be secured and the on-resistance of the power transistor UMOS can be reduced. That is, by providing the embedded base layer BBL and the base layer BL with different p-type impurity concentrations, it is possible to improve the breakdown voltage between the drain and the source and reduce the on-resistance without being affected by each other.
  • the trench protection region TPR is not essential for achieving the effects of the present invention. Also, other electric field relaxation structures can be applied to the power transistor UMOS without departing from the gist of the present invention.
  • the n-type transistor NMOS and the p-type transistor PMOS formed in the CMOS region ARC will be described.
  • the n-type transistor NMOS and the p-type transistor PMOS are formed in the base layer BL.
  • the n-type transistor NMOS is formed in the NMOS area ARN within the CMOS area ARC
  • the p-type transistor PMOS is formed in the PMOS area ARP within the CMOS area ARC.
  • the n-type transistor NMOS has a source region (n-type semiconductor region) RSN and a drain region (n-type semiconductor region) RDN formed in the base layer BL, and a channel provided between the source region RSN and the drain region RDN. It has a region RCN and a gate electrode EGN formed over the channel region RCN via a gate insulating film GIN.
  • the n-type transistor NMOS is a surface channel type MOSFET, and when a desired voltage is applied to the gate electrode EGN, a channel is formed in the channel region RCN immediately below the interface between the base layer BL and the gate insulating film GIN.
  • a channel region RCN provided between the source region RSN and the drain region RDN of the n-type transistor NMOS is a part of the p-type base layer BL, and the channel region RCN is ion-implanted with impurities for threshold voltage adjustment. Therefore, the p-type impurity concentration of the channel region RCN is equal to the p-type impurity concentration of the base layer BL.
  • “equal” includes “substantially equal”. This means that no p-type or n-type impurity ions are intentionally implanted into the channel region RCN, and the base layer BL, which is an epitaxial layer that is not ion-implanted, remains.
  • the p-type impurity concentration of the base layer BL means, for example, the p-type impurity concentration in the channel forming region of the power transistor UMOS.
  • a surface channel type n-type transistor NMOS has been described here, for example, a buried channel type n-type transistor NMOS in which n-type ions are implanted into the channel region RCN may be used. Since the n-type ion implantation causes little damage to the crystal and does not cause a decrease in channel mobility as seen in aluminum ion implantation, which will be described later, it is possible to control the characteristics by means of buried channels.
  • the p-type transistor PMOS is formed in an n-type well region (n-type semiconductor region) NW formed in the base layer BL.
  • the p-type transistor PMOS has a source region (p-type semiconductor region) RSP and a drain region (p-type semiconductor region) RDP formed in the n-type well region NW, and a gate on the first main surface SBa of the laminated semiconductor substrate SB. and a gate electrode EGP formed via an insulating film GIP.
  • the p-type transistor PMOS is a buried channel MOSFET and has a buried channel region EBC with a thickness of about 0.2 ⁇ m from the first main surface SBa of the laminated semiconductor substrate SB.
  • the embedded channel region EBC which is a p-type semiconductor region, is a region in the n-type well NW, where n-type impurities are not substantially ion-implanted.
  • a desired voltage is applied to the gate electrode EGP, a channel is formed not directly under the interface between the buried channel region EBC and the gate insulating film GIP but at a position deeper than the interface.
  • the n-type well region NW is composed of an n-type well layer 1 (n-type semiconductor layer) NW1, an n-type well layer 2 (n-type semiconductor layer) NW2, and an n-type well layer 3 (n-type semiconductor layer) NW3. .
  • the n-type well layer 1NW1 is provided at a relatively deep position from the first main surface SBa of the laminated semiconductor substrate SB, and the n-type well layer 2NW2 is provided on the n-type well layer 1NW1.
  • the n-type well layer 1NW1 and the n-type well layer 2NW2 are formed, for example, by implanting nitrogen ions into the base layer BL.
  • the n-type well layer 1NW1 has a depth of 0.7 to 0.5 ⁇ m from the first main surface SBa, and the n-type well layer 2NW2 has a depth of 0.5 to 0.2 ⁇ m from the first main surface SBa.
  • the p-type impurity concentration of the embedded channel region EBC is equal to the p-type impurity concentration of the base layer BL.
  • the p-type impurity concentration of the base layer BL means, for example, the p-type impurity concentration in the channel forming region of the power transistor UMOS.
  • “equal” includes “substantially equal”. It is important that no p-type or n-type impurity ions are intentionally implanted into the buried channel region EBC.
  • an appropriate error range is ⁇ 50% or less (range of 0.65 to 1.95e17 cm ⁇ 3 ).
  • the defect density of the base layer BL means, for example, the defect density in the channel formation region of the power transistor UMOS.
  • the n-type impurity concentration of the n-type well layer 2NW2 is 2e17 cm ⁇ 3 to 5e17 cm ⁇ 3
  • the n-type impurity concentration of the n-type well layer 1NW1 is 5e17 cm ⁇ 3 to 1e19 cm ⁇ 3
  • the n-type well layer 1NW1 has an n-type impurity concentration of
  • the n-type impurity concentration is set equal to or higher than the n-type impurity concentration of the n-type well layer 2NW2.
  • the n-type well layer 3NW3 is arranged outside the source region RSP and the drain region RDP so as to surround the source region RSP and the drain region RDP.
  • the n-type impurity concentration of the n-type well layer 2NW2 is made lower than the n-type impurity concentration of the n-type well layer 1NW1.
  • the n-type well layer 3NW3 has the same n-type impurity concentration as that of the n-type well layer 1NW1, and is formed continuously from the first main surface SBa of the laminated semiconductor substrate SB to reach the n-type well layer 1NW1.
  • the controllability of the p-type impurity concentration of the embedded channel region EBC and the degree of design freedom can be improved, and the p-type transistor PMOS can be improved. Threshold voltage controllability can be improved.
  • the n-type impurity concentration of the n-type well layer 1NW1 it is possible to prevent the depletion layer from the drain region RDP from punching through the n-type well region NW due to the drain voltage. Also, it is possible to prevent the parasitic Bip transistor composed of the source region RSP/n-type well region NW/base layer BL from being turned on.
  • the trapped holes behave as an effective positive fixed charge, shifting the PMOS threshold voltage negatively. That is, the threshold voltage of PMOS is increased.
  • This hole trap also exists in the NMOS, and when a negative gate bias is applied, an effective positive fixed charge is generated.
  • a positive gate bias is applied to induce inversion electrons in the channel, the inversion electrons and the holes in the hole traps recombine to return to neutrality, which does not affect the electrical characteristics.
  • the inventor of the present application considered forming a buried channel using an ion implantation method in order to avoid the influence of the above positive fixed charge.
  • the embedded channel region EBC of the p-type transistor PMOS is formed of an epitaxial layer and no impurity is implanted by ion implantation, so the on-resistance and threshold voltage of the p-type transistor PMOS can be reduced.
  • FIG. 4 is a diagram showing the relationship between the gate voltage and the drain current of the n-type transistor NMOS and the p-type transistor PMOS of this embodiment.
  • INV-PMOS and INV-NMOS are surface channel type p-type transistor PMOS and n-type transistor NMOS
  • EBC-PMOS1 and EBC-PMOS2 are buried channel type p-type transistor PMOS.
  • the EBC-PMOS1 has a structure in which the thickness of the buried channel region EBC is 0.15 ⁇ m
  • the EBC-PMOS2 has a structure in which the thickness of the buried channel region EBC is 0.2 ⁇ m.
  • a MOSFET with a gate length of 100 ⁇ m and a gate width of 150 ⁇ m is used for electrical characteristic measurement.
  • the drain current is increased (in other words, the on-resistance is reduced) and the threshold voltage is reduced as compared with the surface channel p-type transistor PMOS. A reduction was confirmed.
  • FIG. 5 is a diagram showing the relationship between the input voltage and the output voltage of the CMOS inverter of this embodiment.
  • the switching voltage of the CMOS inverter becomes almost half of the CMOS power supply voltage compared to the case of using the surface channel type p-type transistor PMOS, and LOW level noise It can be seen that the balance between the margin and the HIGH level noise margin is improved.
  • ⁇ Method for Manufacturing the Semiconductor Device of the Present Embodiment> 6 to 12 are cross-sectional views showing manufacturing steps of the semiconductor device 100 of this embodiment.
  • the embedded base layer BBL has a laminated structure of an embedded base layer 1BBL1 and an embedded base layer 2BBL2.
  • a semiconductor substrate SUB having a first main surface (main surface) SUBa and a second main surface (back surface) SUBb facing each other is prepared.
  • the semiconductor substrate SUB is an n-type silicon carbide (4H-SiC) substrate, and the first main surface SUBa is the above-mentioned 4° off (0001) plane.
  • the drift layer DL is formed over the first main surface SUBa of the semiconductor substrate SUB by epitaxial growth.
  • the drift layer DL is an n-type epitaxial layer doped with nitrogen (N) or phosphorus (P), and has an n-type impurity concentration of 1e16 cm ⁇ 3 and a film thickness of approximately 10 ⁇ m.
  • a buried base layer BBL1 and a trench protection region TPR are selectively formed on the surface of the drift layer DL.
  • the embedded base layer BBL1 and the trench protection region TPR are formed by selectively providing a mask layer on the drift layer DL, and ion-implanting p-type impurities (Al ions) into regions exposed from the mask layer to form a p-type semiconductor layer. do.
  • a buried base layer BBL1 and a trench protection region TPR are formed in the power transistor region ARU, and a buried base layer BBL1 is formed in the CMOS region ARC.
  • the buried base layer BBL1 and the trench protection region TPR have a p-type impurity concentration of 1e18 cm ⁇ 3 and a film thickness of approximately 0.5 ⁇ m.
  • a part of the drift layer DL remains in the area covered with the mask layer, and the JFET layer 1DLS1 is formed on both sides of the trench protection area TPR.
  • the n-type impurity concentration of the JFET layer 1DLS1 is 1e16 cm ⁇ 3 .
  • a buried base layer 2BBL2 is formed on the buried base layer 1BBL1, and a JFET layer 2DLS2 is formed on the trench protection region TPR and the JFET layer 1DLS1.
  • an n-type epitaxial layer is formed on the embedded base layer 1BBL1, the trench protection region TPR and the JFET layer 1DLS1 by epitaxial growth.
  • the epitaxial layer has an n-type impurity concentration of 1e16 cm ⁇ 3 and a film thickness of approximately 0.5 ⁇ m.
  • a mask layer is selectively provided on this epitaxial layer, and p-type impurities (Al ions) are ion-implanted into regions exposed from the mask layer to form a p-type semiconductor layer.
  • the buried base layer 2BBL2 is formed in the region exposed from the mask layer, and the JFET layer 2DLS2 is formed in the region covered with the mask layer.
  • the buried base layer 2BBL2 overlapping the buried base layer 1BBL1 has a p-type impurity concentration of 1e18 cm ⁇ 3 , a film thickness of approximately 0.5 ⁇ m, is connected to the base layer 1BBL1, and overlaps the trench protection region TPR and the JFET layer 1DLS1.
  • the JFET layer 2DLS2 has an n-type impurity concentration of 1e16 cm ⁇ 3 and a film thickness of approximately 0.5 ⁇ m.
  • the drift layer DL, JFET layer 1DLS1, and JFET layer 2DLS2 have the same impurity concentration.
  • the type impurity concentration may be set individually.
  • a p-type base layer BL is formed on the embedded base layer BBL and the JFET layer 2DLS2 by epitaxial growth.
  • the base layer BL is a p-type epitaxial layer doped with a p-type impurity such as aluminum (Al), and has a p-type impurity concentration of 1.3e17 cm ⁇ 3 and a film thickness of approximately 1.8 ⁇ m.
  • the base layer BL is formed over the power transistor area ARU and the CMOS area ARC.
  • the n-type well region NW is composed of an n-type well layer 1NW1, an n-type well layer 2NW2 and an n-type well layer 3NW3.
  • nitrogen (N) ions are implanted into the base layer BL to form an n-type well layer 1NW1 and an n-type well layer 2NW2.
  • a buried channel region EBC having a thickness of 0.2 ⁇ m is formed in a range having a depth of 0.2 ⁇ m from the surface of the base layer BL.
  • the threshold voltage of the p-type transistor PMOS changes depending on the balance between the concentration and thickness of the buried channel region EBC and the concentration and thickness of the n-type well layer 2NW2. These conditions can be adjusted to obtain desired properties.
  • the embedded channel region EBC is a region where the p-type semiconductor layer, which is an epitaxial layer, remains without n-type impurity ions being implanted into the base layer BL.
  • an n-type well layer 3NW3 reaching the n-type well layer 1NW1 from the surface of the base layer BL is formed.
  • the n-type well layer 3NW3 is continuously formed in a depth range of 0.5 ⁇ m or more from the surface of the base layer BL.
  • the n-type well layer 3NW3 is formed by ion-implanting nitrogen (N) ions, for example, by a multistage ion-implantation process with different implantation energies.
  • the n-type well layer 3NW3 is in contact with the n-type well layer 2NW2 and the embedded channel region EBC and is formed annularly in plan view so as to surround the periphery thereof.
  • the n-type impurity concentration of the n-type well layer 2NW2 is 2e17 cm ⁇ 3 to 5e17 cm ⁇ 3
  • the n-type impurity concentrations of the n-type well layers 1NW1 and 3NW3 are 5e17 cm ⁇ 3 to 1e19 cm ⁇ 3
  • the n-type impurity concentrations of the n-type well layers 1NW1 and 3NW3 are set equal to or higher than the n-type impurity concentration of the n-type well layer 2NW2.
  • the n-type impurity concentration of the n-type well layer 2NW2 is made lower than the n-type impurity concentration of the n-type well layer 1NW1.
  • the steps of manufacturing the source region RSU of the power transistor UMOS, the source region RSN and drain region RDN of the n-type transistor NMOS, and the source region RSP and drain region RDP of the p-type transistor PMOS are performed.
  • an n-type semiconductor region and a p-type semiconductor region are selectively formed in the surface of the base layer BL by ion implantation.
  • the n-type semiconductor region has an n-type impurity concentration of 1e20 cm ⁇ 3 and is continuously formed in a range from the first main surface SBa to a depth of 0.25 ⁇ m.
  • the n-type impurity concentration should be in the range of 1e19 to 1e22 cm ⁇ 3 and the depth should be in the range of 0.1 to 0.4 ⁇ m.
  • the n-type impurity regions constitute the source region RSU of the power transistor UMOS in the power transistor region ARU, the source region RSN and the drain region RDN of the n-type transistor NMOS in the NMOS region ARN, and the n-type region RNC in the PMOS region ARP. .
  • the p-type semiconductor region has a p-type impurity concentration of 1e21 cm ⁇ 3 and is continuously formed in a range from the first main surface SBa to a depth of 0.25 ⁇ m.
  • the p-type impurity concentration should be in the range of 1e19 to 1e22 cm ⁇ 3 and the depth should be in the range of 0.1 to 0.4 ⁇ m.
  • the p-type semiconductor regions constitute the p-type region RPU of the power transistor UMOS in the power transistor region ARU, the source region RSP and the drain region RDP of the p-type transistor PMOS in the PMOS region ARP, and the p-type region RPC in the NMOS region ARN. do.
  • the n-type semiconductor region and p-type semiconductor region of the power transistor area ARU and the CMOS area ARC may be formed in the same process or in different processes. Further, the steps of forming the n-type well region NW, forming the n-type semiconductor region, and forming the p-type semiconductor region described above are in no particular order.
  • a process for manufacturing trench grooves TG is carried out.
  • a reactive dry etching method a plurality of trench grooves TG are formed in the power transistor area ARU.
  • the trench groove TG has a width of 0.8 ⁇ m, a depth of 2.5 to 2.6 ⁇ m, and a length (perpendicular to the paper surface) of 1500 to 2000 ⁇ m. It penetrates DLS2 and bites into trench protection region TPR.
  • Annealing may be performed after the formation of the trench groove TG to correct the shape such as rounding of the corners.
  • activation annealing is performed in an argon (Ar) atmosphere at 1800.degree.
  • This activation annealing also contributes to recovering the crystal damage of the buried channel region EBC.
  • the embedded channel region EBC passes through without nitrogen ions remaining in the ion implantation process when the n-type well layer 1NW1 and the n-type well layer 2NW2 are formed in the p-type base layer BL. Therefore, a certain degree of crystal damage such as crystal defects occurs. It is known that crystal damage to SiC semiconductors caused during nitrogen ion implantation can be recovered by the aforementioned activation annealing.
  • gate insulating films GIU, GIN and GIP and the gate electrodes EGU, EGN and EGP are performed.
  • gate insulating film GIU is formed on the sidewall and bottom of trench TG, and in CMOS region ARC, gate insulating films GIP and GIN are formed on first main surface SBa.
  • the gate insulating films GIU, GIP and GIN are composed of a silicon oxide film formed using a CVD deposition method, and the film thickness thereof is in the range of 50 to 150 nm, eg 90 nm.
  • an annealing process is performed in a nitrogen monoxide atmosphere in order to reduce the interface states.
  • the gate electrode EGU is formed on the gate insulating film GIU, and in the CMOS region ARC, the gate electrode EGP is formed on the gate insulating film GIP, and the gate electrode EGN is formed on the gate insulating film GIN.
  • the gate electrodes EGU, EGP and EGN are formed of an n-type polysilicon film with a thickness of 0.3 to 1 ⁇ m, for example, 0.5 ⁇ m. It is essential that the thickness of the n-type polysilicon film is such that the trench groove TG is filled.
  • the buried channel region EBC terminates in contact with the n-type well layer NW3 at both ends, and the gate insulating film GIP and the gate electrode EGP extend over the n-type well layer NW3 at both ends.
  • both ends of the source region RSP and the drain region RDP extending in the gate width direction are also terminated in contact with the n-type well layer NW3.
  • the gate insulating film GIU of the power transistor UMOS is a laminated film of a gate insulating film GIU1 and a gate insulating film GIU2 formed thereon.
  • the gate insulating film GIU2 is a CVD oxide film formed on the side wall of the trench TG using the CVD method, and the gate insulating film GIU1 is formed by thermal oxidation between the side wall of the trench TG and the gate insulating film GIU2. It is a thermal oxide film formed in between.
  • the gate insulating film GIP of the p-type transistor PMOS is a laminated film of a gate insulating film GIP1 and a gate insulating film GIP2 formed thereon.
  • the gate insulating film GIP2 is a CVD oxide film formed over the first main surface SBa using the CVD method, and the gate insulating film GIP1 is formed by thermal oxidation between the first main surface SBa and the gate insulating film GIU2. It is a thermal oxide film formed in between.
  • the film thicknesses of the gate insulating film GIU2 and the gate insulating film GIP2, which are CVD oxide films, are equal to each other.
  • the thickness of the sidewall portion of the gate insulating film GIU1, which is a thermal oxide film, is thicker than the thickness of the gate insulating film GIP1, which is a thermal oxide film. Therefore, the thickness of the gate insulating film GIU on the sidewall portion of the power transistor UMOS is thicker than the thickness of the gate insulating film GIP of the p-type transistor PMOS. Since a higher electric field is applied to the gate insulating film GIU of the power transistor UMOS than to the gate insulating film GIP of the p-type transistor PMOS, such film thickness relationships are effective.
  • the gate insulating film GIU of the power transistor UMOS it is possible to realize a high withstand voltage of the gate insulating film GIU of the power transistor UMOS and a high speed operation of the p-type transistor PMOS.
  • the bottom portion of the gate insulating film GIU1 of the power transistor UMOS is thin like the gate insulating film GIP1 of the p-type transistor PMOS, reliability is ensured because the electric field is sufficiently relaxed by the trench protection region TPR. .
  • the gate insulating film GIU1 and the gate insulating film GIP1 are formed in a thermal oxidation process after forming the gate insulating films GIU2 and GIP2 by the CVD method.
  • the growth rate of the thermal oxide film is greatly different between the first main surface SBa and the side wall of the trench groove TG. Since the growth rate of the thermal oxide film depends on the crystal plane, the growth rate of the thermal oxide film on the side walls of the trench groove TG is approximately ten times the growth rate of the thermal oxide film on the first main surface SBa.
  • the gate insulating films GIU1 and GIP1 having different film thicknesses are formed in a self-forming manner without increasing manufacturing steps such as photolithography and etching. It is also possible to perform the heat treatment process at once in combination with the annealing treatment (baking or nitrogen monoxide annealing) performed after the formation of the gate insulating film GIU2.
  • the gate insulating film GIN of the n-type transistor NMOS in the CMOS region ARC can also be a laminated film, like the gate insulating film GIP of the p-type transistor PMOS.
  • the interlayer insulating film IL is formed over the first main surface SBa.
  • the interlayer insulating film IL is composed of, for example, a silicon oxide film having a thickness of 1.0 ⁇ m deposited using the CVD method.
  • a metal film is deposited and patterned to form a first wiring layer including source electrodes ESU, ESP and ESN and drain electrodes EDP and EDN.
  • the metal film is, for example, a laminated film of a titanium (Ti) film and an aluminum (Al) film on the titanium film.
  • the film thickness of the titanium film is assumed to be 0.1 ⁇ m
  • the film thickness of the aluminum film is assumed to be 2 ⁇ m.
  • the source electrode ESU is connected to the source region RSU and the p-type region RPU.
  • the source electrode ESP is connected to the source region RSP and the n-type region RNC
  • the drain electrode EDP is connected to the drain region RDP.
  • the source electrode ESN is connected to the source region RSN and the p-type region RPC, and the drain electrode EDN is connected to the drain region RDN.
  • a second wiring layer formed on the upper layer of the first wiring layer is also used to connect the connection relationship shown in FIG. and an input signal terminal TVin.
  • a drain electrode ED is formed over the second main surface SUBb of the semiconductor substrate SUB.
  • the semiconductor device of this embodiment incorporates a power transistor UMOS, and a p-type transistor PMOS and an n-type transistor NMOS that constitute a CMOS drive circuit, on a semiconductor substrate SUB. Then, by forming the n-type transistor NMOS and the p-type transistor PMOS with the buried channel region EBC in the base layer BL, which is the channel formation region of the power transistor UMOS, the cost reduction of the semiconductor device is realized.
  • the p-type transistor PMOS can be made to have a low threshold voltage and a low on-resistance, and the drive current of the CMOS drive circuit can be increased and the HIGH/LOW Improved noise margin balance.
  • a relatively high concentration and relatively thin embedded base layer BBL is provided on the drift layer DL, a relatively low concentration and relatively thick base layer BL is provided thereon, and the base layer BL is used as a channel forming region of the power transistor UMOS.
  • an n-type transistor NMOS and a p-type transistor PMOS arranged in the n-type well region NW were formed in the base layer BL.
  • the PN junction reverse bias withstand voltage of the n-type transistor NMOS and the p-type transistor PMOS, etc. design freedom can be improved.
  • the n-type well region NW is composed of a relatively high-concentration n-type well layer NW1 and a relatively low-concentration n-type well layer NW2 disposed thereon. Since the n-type well layer NW2 in contact with the buried channel region EBC has a relatively low concentration, it is possible to improve the controllability of the impurity concentration of the buried channel region EBC and the degree of design freedom, and improve the threshold voltage controllability of the p-type transistor PMOS. . Also, by providing the relatively high-concentration n-type well layer NW1, it is possible to prevent the depletion layer from the drain region RDP from punching through the n-type well region NW due to the drain voltage in the PMOS region ARP. Also, it is possible to prevent the parasitic Bip transistor composed of the source region RSP/n-type well region NW/base layer BL from being turned on.
  • the gate insulating film GIU of the power transistor UMOS, the gate insulating film GIP of the p-type transistor PMOS, and the gate insulating film GIN of the n-type transistor NMOS each have a laminated structure of a thermal oxide film and a CVD oxide film, thereby reducing photolithography.
  • the gate insulating film GIU having a film thickness greater than that of the gate insulating films GIN and GIP can be formed in a self-forming manner without increasing manufacturing steps such as lithography and etching.
  • FIG. 14 is a cross-sectional view of a semiconductor device 200 of Modification 1. As shown in FIG. The difference between Modification 1 and the above embodiment is that in CMOS region ARC, n-type transistor NMOS and p-type transistor PMOS are provided in n-type well region DNW.
  • the n-type transistor NMOS is formed within a p-type well region (p-type semiconductor region) PW provided within the n-type well region DNW.
  • the n-type well region DNW is composed of an n-type well layer 1DNW1, an n-type well layer 2DNW2 and an n-type well layer 3DNW3.
  • n-type impurity concentrations of n-type well layer 1DNW1, n-type well layer 2DNW2 and n-type well layer 3DNW3 are the same as those of n-type well layer 1NW1, n-type well layer 2NW2 and n-type well layer 3NW3 in the above embodiment. .
  • n-type well layer 1DNW1, n-type well layer 2DNW2 and n-type well layer 3DNW3 have depths sufficient to enclose p-type well region PW.
  • the n-type well layer 3DNW3 is arranged in a ring so as to continuously surround the NMOS region ARN and the PMOS region ARP in plan view.
  • the source electrode ESU of the power transistor UMOS and the source electrode ESN of the CMOS region ARC are electrically separated by forming a PNP junction via the n-type well region DNW inside the laminated semiconductor substrate SB. Therefore, even if a potential difference occurs between the source electrode ESU and the source electrode ESN, it is possible to prevent current from flowing between them via the inside of the laminated semiconductor substrate SB.
  • the source electrode ESU of the power transistor UMOS and the source electrode ESN of the CMOS region ARC are formed by a p-type region RPU/base layer (p-type semiconductor region ) BL and the buried base layer (p-type semiconductor region) BBL/p-type region RPC are electrically connected as indicated by the dotted line in FIG. Therefore, when a potential difference occurs between the source electrode ESU of the power transistor UMOS and the source electrode ESN of the CMOS region ARC, the current continues to flow through this path, increasing the loss and increasing the device (power transistor UMOS, n-type transistor leading to destruction of the NMOS or p-type transistor PMOS).
  • FIG. 15 is an equivalent circuit diagram showing an example of countermeasures against false ignition.
  • a high voltage fluctuation dV/dt occurs between the drain and source of the power transistor UMOS on the non-switching side in accordance with the operation of the power transistor UMOS on the switching side.
  • erroneous ignition self turn-on.
  • the semiconductor device 200 of Modification 1 even if a potential difference occurs between the source electrode ESU and the source electrode ESN, the current flows between them via the inside of the laminated semiconductor substrate SB. can be blocked.
  • FIG. 16 is a cross-sectional view of a semiconductor device 300 of Modification 2.
  • an isolation region ISO is provided between the power transistor region ARU and the CMOS region ARC.
  • a trench groove TGD, a JFET layer 1DLD1, a JFET layer 2DLD2, and a trench protection region TPRD are provided in the isolation region ISO. are electrically isolated.
  • the JFET layer 1DLD1 and the JFET layer 2DLD2 electrically isolate the power transistor region ARU and the embedded base layer BBL in the CMOS region ARC.
  • the structures of the trench groove TGD, the gate insulating film GID, the gate electrode EGD, the trench protection region TPRD, the JFET layer 1DLD1 and the JFET layer 2DLD2 in the isolation region ISO are the trench groove TG, the gate insulating film GIU and the gate electrode EGU in the power transistor region ARU.
  • trench protection region TPR, JFET layer 1DLS1 and JFET layer 2DLS2 and the manufacturing process is also the same.
  • the isolation region ISO is arranged in a ring shape so as to continuously surround the power transistor region ARU or the CMOS region ARC in plan view.
  • the structure of the isolation region ISO is formed using the manufacturing process of the power transistor UMOS, there is no increase in the manufacturing process.
  • FIG. 17 is a plan view of the semiconductor device 400 of Modification 3
  • FIG. 18 is a plan view for explaining the effects of the semiconductor device 400 of Modification 3.
  • the difference between Modification 3 and the above embodiment is the layout of the power transistor area ARU, the CMOS area ARC, and others.
  • a CMOS region ARC is arranged in the central portion of the first main surface SBa of the laminated semiconductor substrate SB. , the CMOS power supply potential terminal VDD, the input signal terminal Vin, and the CMOS reference potential terminal VSS.
  • the CMOS circuit area ARC may be provided with a drive circuit control circuit, a protection circuit, a sensor circuit, and the like. Further, according to the layout of Modified Example 3, since the power transistor regions ARU are dispersedly arranged on the first main surface SBa, compared with the layout shown in FIG. 2, the heat generation density from the power transistor UMOS is reduced. effective.
  • FIG. 19 is a plan view of a semiconductor device 500 of Modification 4.
  • FIG. 19 The difference between Modification 4 and the above embodiment is the arrangement of the CMOS reference potential terminal VSS, the CMOS power supply potential terminal VDD, and the input signal terminal Vin.
  • the CMOS reference potential terminal VSS, the CMOS power supply potential terminal VDD and the input signal terminal Vin are arranged in the CMOS area ARC and on the PMOS area ARP or the NMOS area ARN. With such an arrangement, miniaturization of the semiconductor device 500 can be realized.
  • the semiconductor substrate SUB of Modification 4 is n-type 4H-SiC.
  • the first main surface SUBa of the semiconductor substrate SUB is, for example, a surface provided with an off angle of ⁇ ° from the (0001) plane in the ⁇ 11-20> direction, which is the off direction of the crystal. It is called the (0001) plane.
  • ⁇ ° is 0 ⁇ 8°.
  • the first main surface SUBa of the semiconductor substrate SUB is a 4° off (0001) plane.
  • the extending direction of the trench groove TG in which the gate electrode (EGU) of the power transistor UMOS is formed is parallel to the off-direction of the crystal, the channel forming surface of the trench groove TG is the (1-100) plane and the (- 1100) surface and is not affected by the off-angle.
  • the extending direction of the trench groove TG is perpendicular to the ⁇ 11-20> direction, which is the off direction
  • the channel formation surface of the trench groove TG is 4 ⁇ 4 in the (11-20) plane in the ⁇ 0001> direction.
  • the extending direction of the trench groove TG in which the gate electrode (EGU) of the power transistor UMOS is formed is preferably parallel to the off-direction of the crystal.
  • the off direction is not limited to the ⁇ 11-20> direction, and may be the ⁇ 01-10> direction or between the ⁇ 11-20> and ⁇ 01-10> directions.
  • ⁇ layer refers not only to a layer extending over the entire main surface of a semiconductor substrate such as an epitaxial semiconductor growth layer, but also to an epitaxial semiconductor growth layer. It also includes portions and regions of different conductivity types that are partially formed using a mask and ion implantation.
  • the expressions "on” and “on the layer” do not mean only the structure directly in contact with the layer, but they retain the effects of the embodiment. It also includes structures with one or more other layers intervening. For example, when epitaxially growing a drift layer on a semiconductor substrate, a buffer layer may be interposed. A structure in which the impurity concentration is changed stepwise in the layer direction may also be adopted.

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102024201914A1 (de) * 2024-03-01 2025-09-04 Robert Bosch Gesellschaft mit beschränkter Haftung Transistorchip und Verfahren zur Herstellung
FR3160051A1 (fr) * 2024-03-05 2025-09-12 Stmicroelectronics International N.V. Procédé de fabrication d’un dispositif électronique

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024017784A (ja) * 2022-07-28 2024-02-08 ルネサスエレクトロニクス株式会社 半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022140A (ja) * 1998-06-26 2000-01-21 Nissan Motor Co Ltd 半導体装置及びその製造方法
JP2002313945A (ja) * 2001-04-11 2002-10-25 Seiko Instruments Inc 半導体集積回路装置の製造方法
JP2004173292A (ja) * 2003-12-08 2004-06-17 Renesas Technology Corp 半導体装置
US20070298563A1 (en) * 2002-10-17 2007-12-27 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor integrated circuit device
JP2009088220A (ja) * 2007-09-28 2009-04-23 Rohm Co Ltd 半導体装置の製造方法および半導体装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4678902B2 (ja) * 1999-09-02 2011-04-27 富士電機システムズ株式会社 炭化けい素ｕｍｏｓ半導体素子およびその製造方法
JP4236848B2 (ja) 2001-03-28 2009-03-11 セイコーインスツル株式会社 半導体集積回路装置の製造方法
JP4906238B2 (ja) * 2003-04-11 2012-03-28 富士電機株式会社 半導体装置
JP4640436B2 (ja) * 2008-04-14 2011-03-02 株式会社デンソー 炭化珪素半導体装置の製造方法
US8933507B2 (en) * 2012-07-10 2015-01-13 Taiwan Semiconductor Manufacturing Co., Ltd. Metal/polysilicon gate trench power mosfet
US9184237B2 (en) * 2013-06-25 2015-11-10 Cree, Inc. Vertical power transistor with built-in gate buffer
WO2016148156A1 (ja) * 2015-03-17 2016-09-22 富士電機株式会社 半導体装置および半導体装置の製造方法
US20160351699A1 (en) * 2015-05-26 2016-12-01 Nxp B.V. Field-effect transistors with body dropdowns
JP6751866B2 (ja) * 2016-04-22 2020-09-09 国立研究開発法人産業技術総合研究所 半導体強誘電体記憶素子の製造方法及び半導体強誘電体記憶トランジスタ
JP6802454B2 (ja) * 2016-08-05 2020-12-16 富士電機株式会社 半導体装置およびその製造方法
JP6972691B2 (ja) * 2017-06-19 2021-11-24 富士電機株式会社 半導体装置および半導体装置の製造方法
DE112018008105T5 (de) * 2018-10-25 2021-09-09 Mitsubishi Electric Corporation Halbleitereinheit, leistungswandler und verfahren zur herstellung einer halbleitereinheit
CN112185959B (zh) * 2020-08-28 2024-03-29 西安电子科技大学 一种与GaN HEMT电力电子器件单片集成的CMOS反相器及制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022140A (ja) * 1998-06-26 2000-01-21 Nissan Motor Co Ltd 半導体装置及びその製造方法
JP2002313945A (ja) * 2001-04-11 2002-10-25 Seiko Instruments Inc 半導体集積回路装置の製造方法
US20070298563A1 (en) * 2002-10-17 2007-12-27 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor integrated circuit device
JP2004173292A (ja) * 2003-12-08 2004-06-17 Renesas Technology Corp 半導体装置
JP2009088220A (ja) * 2007-09-28 2009-04-23 Rohm Co Ltd 半導体装置の製造方法および半導体装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
OKAMOTO MITSUO; YAO ATSUSHI; SATO HIROSHI; HARADA SHINSUKE: "First Demonstration of a Monolithic SiC Power IC Integrating a Vertical MOSFET with a CMOS Gate Buffer", 2021 33RD INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), THE INSTITUTE OF ELECTRICAL ENGINEERING OF JAPAN, 30 May 2021 (2021-05-30), pages 71 - 74, XP033925016, DOI: 10.23919/ISPSD50666.2021.9452262 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102024201914A1 (de) * 2024-03-01 2025-09-04 Robert Bosch Gesellschaft mit beschränkter Haftung Transistorchip und Verfahren zur Herstellung
FR3160051A1 (fr) * 2024-03-05 2025-09-12 Stmicroelectronics International N.V. Procédé de fabrication d’un dispositif électronique

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