JP7563802B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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JP7563802B2
JP7563802B2 JP2023523382A JP2023523382A JP7563802B2 JP 7563802 B2 JP7563802 B2 JP 7563802B2 JP 2023523382 A JP2023523382 A JP 2023523382A JP 2023523382 A JP2023523382 A JP 2023523382A JP 7563802 B2 JP7563802 B2 JP 7563802B2
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semiconductor layer
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insulating film
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JPWO2022249855A5 (https=
JPWO2022249855A1 (https=
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光央 岡本
惇 八尾
弘 佐藤
信介 原田
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National Institute of Advanced Industrial Science and Technology AIST
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/637—Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/159—Shapes
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01366—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the semiconductor being silicon carbide
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/035—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon carbide [SiC] technology
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

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PCT/JP2022/019342 WO2022249855A1 (ja) 2021-05-26 2022-04-28 半導体装置およびその製造方法

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US (1) US20240266351A1 (https=)
JP (1) JP7563802B2 (https=)
CN (1) CN117413366A (https=)
DE (1) DE112022002803T5 (https=)
TW (1) TWI895613B (https=)
WO (1) WO2022249855A1 (https=)

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Publication number Priority date Publication date Assignee Title
JP2024017784A (ja) * 2022-07-28 2024-02-08 ルネサスエレクトロニクス株式会社 半導体装置
DE102024201914A1 (de) * 2024-03-01 2025-09-04 Robert Bosch Gesellschaft mit beschränkter Haftung Transistorchip und Verfahren zur Herstellung
FR3160051A1 (fr) * 2024-03-05 2025-09-12 Stmicroelectronics International N.V. Procédé de fabrication d’un dispositif électronique

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JP2000022140A (ja) 1998-06-26 2000-01-21 Nissan Motor Co Ltd 半導体装置及びその製造方法
JP2002313945A (ja) 2001-04-11 2002-10-25 Seiko Instruments Inc 半導体集積回路装置の製造方法
JP2004173292A (ja) 2003-12-08 2004-06-17 Renesas Technology Corp 半導体装置
US20070298563A1 (en) 2002-10-17 2007-12-27 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor integrated circuit device
JP2009088220A (ja) 2007-09-28 2009-04-23 Rohm Co Ltd 半導体装置の製造方法および半導体装置

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JP4236848B2 (ja) 2001-03-28 2009-03-11 セイコーインスツル株式会社 半導体集積回路装置の製造方法
JP4906238B2 (ja) * 2003-04-11 2012-03-28 富士電機株式会社 半導体装置
JP4640436B2 (ja) * 2008-04-14 2011-03-02 株式会社デンソー 炭化珪素半導体装置の製造方法
US8933507B2 (en) * 2012-07-10 2015-01-13 Taiwan Semiconductor Manufacturing Co., Ltd. Metal/polysilicon gate trench power mosfet
US9184237B2 (en) * 2013-06-25 2015-11-10 Cree, Inc. Vertical power transistor with built-in gate buffer
WO2016148156A1 (ja) * 2015-03-17 2016-09-22 富士電機株式会社 半導体装置および半導体装置の製造方法
US20160351699A1 (en) * 2015-05-26 2016-12-01 Nxp B.V. Field-effect transistors with body dropdowns
JP6751866B2 (ja) * 2016-04-22 2020-09-09 国立研究開発法人産業技術総合研究所 半導体強誘電体記憶素子の製造方法及び半導体強誘電体記憶トランジスタ
JP6802454B2 (ja) * 2016-08-05 2020-12-16 富士電機株式会社 半導体装置およびその製造方法
JP6972691B2 (ja) * 2017-06-19 2021-11-24 富士電機株式会社 半導体装置および半導体装置の製造方法
DE112018008105T5 (de) * 2018-10-25 2021-09-09 Mitsubishi Electric Corporation Halbleitereinheit, leistungswandler und verfahren zur herstellung einer halbleitereinheit
CN112185959B (zh) * 2020-08-28 2024-03-29 西安电子科技大学 一种与GaN HEMT电力电子器件单片集成的CMOS反相器及制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022140A (ja) 1998-06-26 2000-01-21 Nissan Motor Co Ltd 半導体装置及びその製造方法
JP2002313945A (ja) 2001-04-11 2002-10-25 Seiko Instruments Inc 半導体集積回路装置の製造方法
US20070298563A1 (en) 2002-10-17 2007-12-27 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor integrated circuit device
JP2004173292A (ja) 2003-12-08 2004-06-17 Renesas Technology Corp 半導体装置
JP2009088220A (ja) 2007-09-28 2009-04-23 Rohm Co Ltd 半導体装置の製造方法および半導体装置

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Title
OKAMOTO, Mitsuo et al.，First Demonstration of a Monolithic SiC Power IC Integrating a Vertical MOSFET with a CMOS Gate Buff，2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD)，2021年06月15日，pp. 71-74，DOI: 10.23919/ISPSD50666.2021.9452262

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CN117413366A (zh) 2024-01-16
DE112022002803T5 (de) 2024-04-11
TW202301679A (zh) 2023-01-01
JPWO2022249855A1 (https=) 2022-12-01
US20240266351A1 (en) 2024-08-08
TWI895613B (zh) 2025-09-01

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